Find all hazards in this circuit. Redesign the circuit as a three-le.pdf
- 1. Find all hazards in this circuit. Redesign the circuit as a three-level NOR circuit that is free of all hazards Show how four 2-to-1 and one 4-to-1 multiplexers could be connected to form an 8- to-1 MUX with three control inputs Solution 1 University of Wisconsin - Madison ECE/Comp Sci 352 Digital Systems Fundamentals Charles R. Kime Section 2 – Fall 2001 Chapter 2 – Combinational Logic Circuits – Part 7 Charles Kime & Thomas Kaminski © 2001 Prentice Hall, Inc Logic and Computer Design Fundamentals Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 2-Part 7 2 NAND and NOR Implementation We found that we could implement general Boolean equations with these three primitives: • AND • OR • NOT In this section we will find that either of two gates, the NAND gate or the NOR gate can be used to implement arbitrary logic functions. We use the Positive Logic Convention (where all signals are active high) and a small circle to on a symbol to represent NOT or invert. 2 Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 2-Part 7 3 NAND Gates The basic positive logic NAND gate is denoted by the following symbol: • AND-Invert (NAND) NAND comes from NOT AND, I. e., the AND function with a NOT applied. We call this symbol for a NAND gate an AND-Invert. The small circle represents the invert function. If we apply DeMorgan's Law we get: X Y Z X YZ = X + Y + Z F(X, Y,Z) = X Y Z Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 2-Part 7 4 NAND Gates (Cont.) Applying DeMorgan's Law gives: • Invert-OR (NAND) We call this symbol for a NAND gate the Invert - OR since all inputs are inverted, followed by the OR function. Both symbols represent the NAND gate - it is sometimes more logically descriptive to use one form over the other. A NAND gate with one input degenerates to an inverter. X Y Z F(X, Y,Z) = X + Y + Z 3 Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 2-Part 7 5 NAND Function Implementation NAND gates can implement a simplified Sum-ofProducts form. Constructing two level NAND-NAND gate circuit: The first level is two 2-input NAND gates using ANDInvert. The second level is one 2- input NAND gate using Invert-OR. Using the NAND relationship, we have: G(A,B,C,D) = AB CD = AB + CD = A B + CD A B C D G(A,B,C,D) = AB + CD Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 2-Part 7 6 NAND Implementation (Cont.) In the implementation, note that the bubbles are on opposite ends of the same line. Thus, they can be combined and deleted: A B C D G(A,B,C,D) This form of the implementation is the Sum-of- Products form. 4 Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 2-Part 7 7 NAND Implementation (Cont.) In the implementation, the bubbles are on opposite ends of the same line. By , they can be combined and deleted: A sum-of-products (SOP) form
- 2. results To implement an equation like: F(A,B,C) = A + BC, the NAND for A degenerates to a NOT since there is only one input A B C D G(A,B,C,D) X = X Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 2-Part 7 8 Degenerate AND Term The degenerate NAND becomes an inverter: To implement the complement of F using NAND gates, add an inverter to the output: A B C F(A,B,C) A B C F'(A,B,C) 5 Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 2-Part 7 9 NAND-NAND Example Implement: x z w 0132 4576 12 13 15 14 8 9 11 10 1111 1 1 1 1 1 0 0 000 0 0 y F’ (w,x,y,z) x y z w 0132 4576 12 13 15 14 8 9 11 10 1111 1 1 1 1 1 0 0 000 0 0 F(w,x,y,z) F(w, x, y, z) = y z + w x + x y + w z Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 2-Part 7 10 Summary: Two-Level NAND Circuits Find minimum literal SOP form for F and F Select SOP form with smallest literal count Convert selected form to NAND circuit using AND-invert (inverters for single literal AND terms) and invert-OR symbols If SOP form for F used, add inverter to circuit output. 6 Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 2-Part 7 11 NOR Gates The basic positive logic NOR gate (Not-OR) is denoted by the following symbol: OR-Invert (NOR) This is called the OR-Invert, since it is logically an OR function followed by an invert. By DeMorgan's Law we have the following Invert-AND symbol for a NOR gate: X Y Z Invert-AND A single-input NOR gate is an inverter, too. X Y Z F(X,Y,Z) = X+Y+Z Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 2-Part 7 12 NOR Gates The basic positive logic NOR gate is denoted by the following symbol: • OR- Invert (NOR) NOR comes from NOT OR, I. e., the OR function with a NOT applied. We call this symbol for a NOR gate an OR-Invert. The small circle represents the invert function. If we apply DeMorgan's Law we get: X +Y+Z = X Y Z X Y Z F(X,Y,Z) = X+Y+Z 7 Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 2-Part 7 13 NOR Gates (Cont.) Applying DeMorgan's Law gives: • Invert-AND (NOR) We call this symbol for a NOR gate the InvertAND since all inputs are inverted, followed by the AND function. Both symbols represent the NOR gate - it is sometimes more logically descriptive to use one form over the other. A NOR gate with one input degenerates to an inverter. F(X,Y,Z) = X Y Z X Y Z Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 2-Part 7 14 (A+B)+(C+D) NOR Function Implementation NAND gates can implement a simplified Sum- ofProducts form. Constructing two-level NOR-NOR circuit: The first level is two 2-input NOR gates using ORInvert. The second level is one 2-input NOR gate using Invert-AND. Using the NOR relationship, we have: G(A,B,C, D) = = = (A+B) (C+D) G(A,B,C,D) = ( ) A + B ( ) C + D A B C D (A+B) (C+D) 8 Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 2-Part 7 15 Useful Transformations From Involution (i.e. (A')' = A) and DeMorgan's Law, we get the following useful equivalences: (A•B) = ((A•B)')' (A'+B')' (A+B) = ((A+B)')' (A'•B')' (A•B)' (A'+B') (A+B)' (A'•B') These simple transformations can be
- 3. used to manipulate a two level network. Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 2-Part 7 16 Graphical Transformations The relations from the previous slide lead to the following transformations: Recall that two bubbles in series can be removed from the circuit (A •B) = ((A•B)')' (A'+B')' (A+B) = ((A+B)')' (A'•B')' (A •B)' (A'+B') (A+B)' (A'•B') 9 Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 2-Part 7 17 General Two-level Implementations We need to consider whether the form of a two-level implementation is to be: 1. SOP (AND-OR) or 2. POS (OR-AND). Complemented output functions (i.e. AND-NOR or ORNAND) can be handled by complementing the function. Given a function F expressed as a Karnaugh Map, we can use the same general procedures we have used before to minimize the function and express it in SOP or POS form. Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 2-Part 7 18 General Implementations (Cont.) Given a two level implementation desired, use the previous transfromations to get it into one of the below forms. Then follow the steps to transform the function to the desired form: For Type: Use: AND-OR (SOP Form) Circle 1's in the K-Map and minimize (Also use for NAND-NAND) AND-NOR (SOP complemented) Circle 0's in the K-Map and minimize OR-AND (POS Form) Circle 0's in the K-Map and minimize SOP. Use DeMorgan's to transform to POS. (Also use for NOR-NOR) OR-NAND (POS complemented) Circle 1's in the K-Map and minimize SOP. Use DeMorgan's to transform to POS. 10 Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 2-Part 7 19 Implementation Example 1 Implement the function in NOR-OR. A B C 1 1 1 1 1 0 0 0 We can remove the "Inverter" and replace it with the complement of the input variable Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 2-Part 7 20 Implementation Example 2 A B 1 1 1 1 1 0 0 0 Implement the function in AND-NOR. 11 Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 2-Part 7 21 Multi-level NAND Implementations Add inverters in two-level implementation into the cost picture Attempt to “combine” inverters to reduce the term count Attempt to reduce literal + term count by factoring expression into POSOP or SOPOS Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 2-Part 7 22 Multi-level NAND Example 1 F = A B’ + A C’ + B A’ + B C’ = A A’ + A B’ + A C’ + B A’ + B B’ + B C’ = A (A’ + B’ + C’) + B (A’ + B’ + C’) F A C B 7 inputs and 4 gates 15 inputs and 8 gates* * Counting inverters (NOTS) as 1 input and 1 gate 12 Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 2-Part 7 23 Multilevel NAND Example 2 F = AB + AD’ + BC + CD’