Fixed-point Multi-Core DSP Platform
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The document provides an overview of the EVP6472 embedded multicore solution, highlighting its dual TI 320C6472 DSP capabilities and development platform features. It includes technical specifications, programmable hardware, and descriptions of the integrated development environment for designing multi-DSP and FPGA applications. Additionally, it emphasizes the system's efficiency, performance, and flexibility for high-speed signal processing applications.
Fixed-point Multi-Core DSP Platform
- 1. Sundance Multiprocessor Technology EVP6472 Embedded TI MultiCore Solution Easy development platform for Dual ‘TI 320C6472 DSPs C6472 Multicore DSP C6472 Multicore DSP
- 2. 2 Outlines TMS320C6472 MultiCore DSP • http://processors.wiki.ti.com/index.php/C6472 Diamond software architecture for MultiCore DSP • http://www.3l.com/ Model-based design concept for DSP + FPGA ‘C’-based design concept for FPGA EVP6472 Evaluation Platform • Technical Overview • Prices
- 3. EDMA3.0 with Switch Fabric Shared L2 memory 10/100/1G Ethernet sRIODDR-2 GPIO I2CPLL Timers Others BootROM High Density Memory System 6 High Speed C64x+ CPUs “Switch Fabric” DMA Engine Communications Subsystem DDR-2 Memory Interface DSP based system provides programmability, flexibility, extensibility. • Small Footprint allows high board density • 24x24, FC-BGA C64x+ Core L1 Prog L1 Data C64x+ Core L1 Prog L1 Data C64x+ Core L1 Prog L1 Data C64x+ Core L1 Prog L1 Data C64x+ Core L1 Prog L1 Data C64x+ Core L1 Prog L1 Data L2 memory L2 memory L2 memory L2 memory L2 memoryL2 memory TSIPHPI Utopia II • 3 different speed versions – 500MHz, 625MHz, & 700MHz Deliver 24,000, 30,000, & 33,600 (16-bit) MMAC) • Based on TI’s flagship C64x+ DSP core (achieved BDTI’s highest speed score) • 100% backward compatibility with other C64x DSPs enables legacy code re-use for development efficiency & faster time-to-market • Memory architecture enables highest CPU performance • Separate L1 Program and Data Memory per CPU • 32KB L1 Program • 32KB L1 Data • Configurable as Cache or Memory • Unified L2 Memory per CPU • 608KB each • Can be Program or Data • Configurable as Cache or Memory • Shared L2 Memory • 768KB in total • Memory available to all cores • Can be Program or Data • Access managed by separate controller • High bandwidth communications between peripherals, memories and CPUs. • Handles multiple concurrent transfers • Communication peripherals can initiate transfers without CPU • High throughput for high bandwidth peripherals • Various Peripherals enhance data communication • UTOPIA 2 – supports telecom networks • 10/100/1G Ethernet – supporting IP networks and systems • MII, rMII, S3MII • GMII, rGMII • TDM ports allow up to 3072 Timeslots • sRIO for DSP-DSP communications • Direct connect or through switch. • Host port allows DSP memory probe. • EMIF for DDR-2 Standard • Low Cost memory in market window • 32-bit memory bus • 8 and 16-bit DDR memories only • 400-533 MHz data rate
- 4. 4 Computer architecture Design flow strategy and methodology Sundance’sHardwareDiamondTasksDiamondIDECompilerTools Network of heterogeneous processor devices DSPs, FPGAs, PowerPC, Host processor... Platform abstraction and communication links DSP Tasks FPGA Tasks Code Composer Studio Compiler & Linker XILINX ISE Synthesis, Implementation and PAR 3L Diamond DSP 3L Diamond FPGA Electronic System Level tools PARS, System Generator, HDL coder, Impulse C, IP cores... ESL
- 5. 5 3L Diamond Development System Multi-DSP RTOS and FPGA task-based co-design tool www.3L.com/IDE/IDE%20Demo.htm What is 3L Diamond? Multiprocessor devices co-design tool optimised for the Sundance hardware Designed for multiprocessor systems, simplicity and efficiency • During development and execution Reduce the application development time and integration burden • Automatically invoke Xilinx ISE to build hardware tasks • Automatically call Texas Instruments Code Composer to compile software tasks • Automatically creates one single application • Automatically configure your network of processor devices Key features: • Interactive development environment • Support for DSP, FPGA, Embedded PowerPC cores… • Real-time operating system for DSP processors • Design structure for reusable FPGA IP cores • Leverage system complexity and reduce time-to-market
- 6. Six Processor Cores Six Processor Cores A complex 3L Diamond Multicore application ... in just one file! Diamond processor a Diamond task A 3L Diamond Multicore application: a Diamond channel Twelve C64x+ DSP Cores:Software Tasks to execute:Interconnection Channels:
- 7. 7 3L Diamond IDE Integrated development environment framework Describe the application only, everything else is automatically done.
- 8. 8 Impulse CoDeveloper for 3L Diamond Electronic system level (ESL) design tool What is Impulse C? Development tool for FPGA-accelerated computing C-programming language to FPGA design approach Hardware Acceleration for High-Performance Systems • For embedded digital signal processing systems • For high-performance computing Key features: • Design of FPGA devices • Made for dataflow-oriented applications • Software-to-hardware compiler • Interactive parallel optimizer • Increase code execution performance from 10x up to 30x • Platform support package for the Sundance hardware http://www.impulsec.com/app_web_training.htm
- 9. 9 PARS Model-based design Parallel application from rapid simulation Simulink design environment PARS pluggin Target hardware Multi-DSP and FPGA applications from Simulink® Hardware-in-the-loop testing for real-time simulations
- 10. 10 PARS Model-based design Why is PARS efficient and how does it work? Build a model with MATLAB Simulink® Verify and simulate the Simulink model created Use PARS to partition the model into: • DSP Tasks • FPGA Tasks • HOST Tasks PARS creates a 3L Diamond project (Diamond generates a single application) The test vectors are generated from the Simulink testbench model The application is loaded and runs on the Sundance hardware The simulation model is executed on the real hardware system The test results are sent back to Simulink for data analysis Hardware-in-the-loop testing is the most efficient technique for: • Rapid simulation • Efficient proof of concept for algorithm • Fast prototyping system
- 11. 11 PARS Model-based design Design environment from MATLAB Simulink® http://www.youtube.com/user/SundanceDSPVideos
- 12. 12 SMT372T Dual ‘C6472 DSPs, FPGA, Ethernet,109 LVDS I/O pins, TIM Module SMT372T is the heart of the Evaluation Platform for TI’s TMS320C6472 DSP and can be used on a range of carriers, from PCI104 to Compact PCI.
- 13. 13 SMT372T Dual ‘C6472 DSPs, FPGA, 109 LVDS I/O pins, TIM Module SMT372T is the Module that EVP6472 is based on and can be used for OEM customers as a components Sundance IP-Cores VHDL Sources GTX / RSL SRIO IP-Core (Optional) Ethernet Router Comport Timers Interupts VIRTEX 5 (Power PC) Flash control and FPGA configuration EMAC SLB 4x 8-bit differential SundanceLocalBus RSL Connectors (2 bottom, 1 top) Primary TIM connector C6472 DSP1 500 – 625 MHz C6472 DSP2 500 – 625 MHz CPLD CFG/BOOT DDR2 256MBytes @533MHz DDR2 256MBytes @533MHz Clocks PHY RJ45 Header FLASH 64MBytes FPGA Configuration DSP Application 109 I/O SRIO EMAC McBSP HPI SRIO SRIO HPI EMAC DDR2 26.66MHz SRIO 125/156MHz Core / EMAC 25MHz
- 14. 14 EVP6472 Dual ‘C6472 ,FPGA, USB2.0, Ethernet, RS232C, 109 LVDS I/O pins EVP6472 is a stand-alone platform for experimenting with algorithms for high-speed signal processing for various applications. LEDS USB 2.0 Micro SD JTAG IN JTAG Out TTL I/O QUAD UART 4x RS232 VIRTEX 5 POWER PC SundanceLocalBus FLASH MEMORY PHY RJ45 header C6472 DSP1 500 – 700MHz C6472 DSP2 500 – 700MHz DDR2 256MBytes 533MHz DDR2 256MBytes 533MHz CPLD CFG/BOOT RSL Connectors FPGA SPARTAN 3 FLASH MEMORY Sundance IP Cores Ethernet Router FLASH control and FPGA Config SRIO IP CORE SLB 4x 8bit differential GTX / RSL Comport Timers Interupts EMAC Clocks SundanceLocalBus Power Supplies +/-12V +5V +3.3V EVP6472 Overview
- 15. 15 EVP6472 Dual ‘C6472 DSPs, FPGA, USB2.0, RS232C,109 LVDS I/O pins EVP6472 is a stand-alone platform for experimenting with algorithms for high-speed signal processing for various applications.
- 18. 18 Thank you! Flemming Christensen Managing Director Sundance Multiprocessor Technology www.sundance.com Contact details: Flemming.C@Sundance.com + 44 7850 911 417 Skype: Flemming_Skype