FPGA Based V/f Control of Three Phase Induction Motor Drives Integrating Super-Lift Luo Converter

International Journal of Power Electronics and Drive System (IJPEDS)
Vol. 5, No. 3, February 2015, pp. 393~403
ISSN: 2088-8694  393
Journal homepage: http://iaesjournal.com/online/index.php/IJPEDS
FPGA Based V/f Control of Three Phase Induction Motor
Drives Integrating Super-Lift Luo Converter
P. Elangovan*, Nalin Kant Mohanty**
* Departement of Electrical and Electronics Engineering, S.K.P. Engineering College, Anna University
** Departement of Electrical and Electronics Engineering, Sri Venkateswara College of Engineering, Anna University
Article Info ABSTRACT
Article history:
Received Dec 5, 2014
Revised Jan 12, 2015
Accepted Jan 21, 2015
The significance of Elementary Positive Output Super-Lift Luo Converter
(EPOSLLC) in constant Voltage/Hertz (V/f) controlled Induction Motor (IM)
drive is presented. The traditional IM drive which integrates phase controlled
rectifier or boost converter in the facade end upshot tribulations like DC link
fluctuations and deprived DC link voltage level. To overcome the problem,
the conventional DC-DC converter is replaced with Proportional plus
Integral (PI) controlled EPOSLLC in the front end of IM drive that produces
the DC link voltage in geometric progression. The Voltage Source Inverter
(VSI) of the suggested system renders both open loop and closed loop V/f
control scheme for IM by feedback regulated Sinusoidal Pulse Width
Modulation (SPWM) technique. Simulation and experimental works are
conceded and results presented to demonstrate the viability of the proposed
approach. Simulation is carried out using MATLAB /SIMULINK software
and the experimental setup is built with Field Programmable Gate Array
(FPGA) Spartan-6 processor. The anticipated EPOSLLC is found fit for V/f
controlled IM drives considering the DC link Voltage, Speed response of IM
and Total Harmonic Distorion (THD) in IM current.
Keyword:
DC link Voltage
EPOSLLC
Induction Motor Drives
PI controller
Total Harmonic Distortion
Copyright © 2015 Institute of Advanced Engineering and Science.
All rights reserved.
Corresponding Author:
P.Elangovan,
Research Scholar & Assistant Professor,
Departement of Electrical and Electronics Engineering,
S.K.P. Engineering College, Anna University, Tiruvannamalai - 606611
Email: elangoeee2007@gmail.com
1. INTRODUCTION
Induction Motors are the Workhorse of the Industry due to its economy of procurement, installation
and use. Recent development in the field of Power Electronics planted a wide usage of Induction Motor (IM)
in the adjustable speed drives where speed control of the motor is highly required and squirrel cage type of
IM is very popular in that case.The basic control involved in variable speed control of IM is application of a
variable frequency and variable magnitude of AC voltage to the motor for the attainment of variable speed
operation. Many techniques are already introduced to control the IM parameters [1]. However, the method by
name constant Voltage/Hertz (V/f) is versatile in use. Further, the V/f technique is classified into open loop
and closed loop control. The open loop V/f control of IM presented in [2] use the arrangement of Voltage
Source Inverter (VSI) fed IM with source input as DC which fails to discuss the influence of DC link
fluctuations in the IM drive due to load disturbance and also the results obtained are ideal. The closed loop
V/f control overcomes the problem with the load disturbance that prevails in open loop V/f control of IM.
However, the focus on quality DC link voltage for feedback processing is handled by means of a braking
circuit [3] which complicates the system design. To introduce the importance of DC link voltage, a new
model [4] is developed to utilize the DC link voltage in more efficient way, but the maximum starting current
and Total Harmonic Distortion (THD) in stator current of IM are still the barrier factors of practical
implementation.

 ISSN: 2088-8694
IJPEDS Vol. 5, No. 3, February 2015 : 393 – 403
394
In addition, using a DC link capacitor to reduce the THD in stator current of IM is developed [5] but
the DC link flickering which is not suitable for feedback controlled system is not eliminated. Instead of
adding a passive element to the IM drive system for the purpose of reducing THD, the view turned on to the
Pulse Width Modulation (PWM) technique used to generate gate pulse for VSI through which the required
variable voltage and variable frequency is attained simultaneously reducing the THD. Among different PWM
techniques, the Sinusoidal Pulse Width Modulation (SPWM) [6], [7] is most popular and simple technique
applicable for IM drives. In SPWM technique, two signals (a sinusoidal reference signal and a high triangular
carrier signal) are compared to provide two statuses (high or low) of output. On the other hand, the ripple
content in the DC link voltage destroys the feature of SPWM technique by distorting the output current of
VSI. The research work [8] developed a separate DC link voltage control in addition with complex PWM
control for back-back converter fed IM drive, but it is not economic for low power IM drives. The influence
of DC link fluctuations over the THD of IM current and voltage is very clearly presented in [9] under
different working conditions and concluded that the DC fluctuations has an effect on IM parameters. To
triumph over the above mentioned drawbacks, the simple DC-DC converters such as boost, buck and buck-
boost converters were introduced in the façade end of VSI fed IM drive [10], [11]. Using boost converter in
IM drives, only twice the input DC is attainable in DC link [12] and hence another factor, DC link voltage
level comes into play.
An advanced DC-DC converter in Super-Lift Luo converter series [13], [14] by name Elementary
Positive Output Super-Lift Luo Converter (EPOSLLC) produce output voltage in geometric progression
overcomes the problem that exist in conventional boost converter. However, EPOSLLC is not competent
while used with constant conduction duty and the investigation [15] held to control EPOSLLC using PI
regulator fails to show improvement of EPOSLLC under load and line variation.
This paper implements a superior PI control of EPOSLLC in the front end of both open loop and
closed loop V/f controlled IM drives. The proposed IM drive grasp features such as DC link voltage level 1.5
times greater than the conventional boost converter reduced THD in Stator Current of IM, fluctuation free
DC link voltage and improved speed regulation of IM.
2. DESIGN OF IMPROVED PI CONTROLLER FOR PROPOSED EPOSLLC
The work presented in this paper mainly focus on regulated DC-DC conversion that feeds VSI-IM
drive. One of the advanced DC-DC converters from the family of positive output Super-lift Luo series have
been chosen for the intended scheme. The positive output Super-lift Luo converter has some sub-series such
as Main series, Additional series, Enhanced series, Re-enhanced series and Multiple-enhanced series. The
elementary circuit from Main series is implemented for the proposed arrangement. The elementary circuit
and equivalent circuit during switch ON and OFF are shown in Figure 1.
(a) (b) (c)
Figure 1. (a) Equivalent circuit of EPOSLLC, (b) EPOSLLC during switch ON, (c) EPOSLLC during switch
OFF
The voltage across C21 is charged to Vi(dc) which is the rectified input to EPOSLLC. The current
through the inductor L21 increases with Vi(dc) during switch ON and decreases with – (Vo(dc) - 2Vi(dc)) during
switch OFF of EPOSLLC. The average output voltage of EPOSLLC is:
o(dc) i(dc)
2 - γ
V = V
1 - γ
(1)

IJPEDS ISSN: 2088-8694 
FPGA Based V/f Control of Three Phase Induction Motor Drives Integrating Super-Lift… (P.Elangovan)
395
Where, o(dc)V is the average output voltage of EPOSLLC, i(dc)V is the input voltage of EPOSLLC and γ is
conduction duty.
The output current of EPOSLLC is:
o(dc) i(dc)
1 - γ
I = I
2 - γ
(2)
Where, o(dc)I is the average output current of EPOSLLC and i(dc)I is the input current of EPOSLLC. The
voltage transfer gain (G) of EPOSLLC is given by:
2 - γ
G =
1 - γ
(3)
Whereas, the voltage transfer gain of conventional boost converter is:
1
G =
1 - γ
(4)
On comparing (3) and (4), it is obvious that for the same conduction duty, EPOSLLC produce 1.5 times the
voltage transfer that of the conventional boost converter.
The control strategy of EPOSLLC using PI regulator is exposed in Figure 2. The error in the actual
DC link voltage with respect to the reference DC link voltage is the input to the PI controller.
Figure 2. Control strategy of EPOSLLC
The PI controller for anticipated EPOSLLC is designed by finding the appropriate value of
proportional gain (Kp) and integral time (Ti). The first step in determining Kp and Ti is to develop the state
model of EPOSLLC.The state model of EPOSLLC [16], [17] is determined by assuming the state variables
x1 (current flowing through L21), x2 (Voltage across C21) and x3 (Voltage across Co) and input variable u
(input voltage of EPOSLLC). Considering negligible input and output resistance of proposed EPOSLLC, the
state-space averaging model of EPOSLLC is given by:
.
1 21 21 21 21
1
.
2 2
21 21 21
. 3
3
1 1 1 1
1 2
0
1 1 1
0
o o o
x L L L Lx
x x u
C C C
x
x
C C C
 
  

    
     
      
               
            
         
(5)
Based on Zeigler – Nichols tuning method [18], Kp and Ti are resolved by applying the step input to the
mathematical model (5) of EPOSLLC to attain S – shaped curve and is shown in Figure 3. By drawing a

 ISSN: 2088-8694
396
tangential line to the S-shaped curve gives the constants delay time (L = 0.005s) and time constant (T =
0.015s). From the value of L and T, the Kp (9.36) and Ti (0.016s) are straight away resoluted from Zeigler –
Nichols chart.
Figure 3. S-shaped step response of EPOSLLC
3. DRIVE TOPOLOGY OF PROPOSED SCHEME AND CALCULATION OF IM PARAMETERS
This section explains the two different topologies of IM drive intended and followed by IM
parameters calculation. Figure 4 and Figure 5 shows the open loop and closed loop V/f control topology of
proposed scheme.
Figure 4. Proposed Scheme with Open Loop V/f Control Topology
Figure 5. Proposed Scheme with Closed Loop V/f Control Topology
0 2 4 6 8 10
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Time(x(10-
2)s)
ResponseofEPOSLLC
Step Response of EPOSLLC
T=0.015s
L=0.005s
Tangential Line

397
Both the scheme presented above incorporates PI controlled EPOSLLC arrangement in the façade
end of VSI. The open loop V/f controlled IM drive depicted in Figure 4 process the reference speed that is
multiplied with the fixed gain values of modulation index and frequency of the reference sine wave used in
SPWM technique for generating gate signals to VSI. Whereas, the closed loop V/f controlled IM drive shown
in Figure 5 uses the PI controller for regulating the error in speed of IM via SPWM technique.
Apart from the control technique discussed above, the critical parameter estimation of IM is
necessary and to assess, the per-phase equivalent circuit of IM in the proposed scheme is designed and shown
in Figure 6. In Figure 6, the different parameters of IM are Stator resistance (RS), Stator inductance (XS),
Stator phase current (IS), Mutual Inductance (XM), Magnetizing Current (IM), Rotor resistance (RR), Rotor
inductance (XR), Rotor current (IR) and Slip (S). For the case presented, the required speed of IM is 1000rpm
and the factors such as IM current, Power factor (P.F.) and efficiency (η) are calculated in this section.
Figure 6. Per-Phase Equivalent circuit of Proposed IM
Using Kirchoff’s Current law, the primary phase current of IM is specified by,
IS = IM + IR (8)
The expression for magnetizing current (IM) is,
S
M
M
E
I =
jX
(9)
Where, ES is internal e.m.f. of IM.
The rotor current is,
R
R
( )(S)(T)
I =
R (1 - S)
 (10)
Where, ω is the required speed of IM, in (rps) and T is the torque developed by IM. From (9) & (10), the
phase current of IM is determined and the efficiency of IM is given by:
O
O L
P
η =
P +P
(11)
Where, PO is power output by IM and PL is the IM losses.
The output power and losses of IM is given by:
link
O
(1 - S) P
P =
S
(12)
2 2
L S S R RP =3( I R + I R ) (13)
Where, Plink is the DC link power of the IM drive.

 ISSN: 2088-8694
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From (12), it is understandable that the deprived DC link voltage reduces the magnitude of DC link
power and tends to huge drop in output power of IM. This proves that the DC link voltage plays a vital role
in the efficiency point of IM. The various factors discussed above were calculated for the anticipated scheme
of 400V, 50Hz, 1410rpm, 0.5HP, three phase IM and are tabulated in Table 1.
Table 1. Calculated Values
IM Parameters Calculated Value
Motor Current 1.736 A
Power Factor 0.926
Efficiency 96 %
4. SIMULATION WORK AND RESULTS
To validate the effectiveness of projected scheme, the Simulink model of ‘EPOSLLC adapted V/f
control of IM drive’ is designed and the simulation is conceded using MATLAB 2012a software. The
Simulink model is developed for both Open loop and closed loop V/f controlled IM drive with same
arrangement of EPOSLLC in the front end and holds invariable simulation circuit parameters which is shown
in Table 2.
Table 2. Simulation Circuit Parameters
Parameter Rating
Input AC Supply 1 phase, 100V, 50Hz
Induction Motor (IM) 0.5 hp ,3-phase, 50Hz,400V
Stator Resistance of IM 11.1Ω
Stator Inductance of IM 18.8mH
Rotor Resistance of IM 12.3Ω
Rotor Inductance of IM 26.7mH
Mutual Inductance 467mH
Inductor L21 = 2.56mH
Capacitors C21 = 2000µF, Co = 2200µF
The Simulation results such as output voltage of EPOSLLC and line output voltage of VSI remains
same for both the simulated Open loop and closed loop V/f controlled IM drive, because the load disturbance
affects only the stator current and speed of IM in proposed scheme. To authenticate the preliminary feature of
the developed method, the DC link voltage (i.e.) the output voltage of proposed EPOSLLC is shown in
Figure 7.
Figure 7. Output Voltage of proposed EPOSLLC
The above result shows that for 100V rectified input, EPOSLLC produce ripple free 300V DC
voltage and verifies the effectiveness of PI controlled EPOSLLC ideally. The output line voltage of VSI in
the proposed scheme is shown in Figure 8.
0 0.5 1 1.5 2 2.5 3
0
100
200
300
400
Time (s)
Voltage(V)
Output Voltage of EPOSLLC

399
Figure 8. Line Output Voltage of VSI in the proposed scheme
The speed response of IM for proposed open loop and closed loop V/f controlled IM drive is
presented in Figure 9.
(a) (b)
Figure 9. Speed response of IM for 0.5N.m load disturbance at 1s (a) during open loop V/f control (b) during
closed loop V/f control
The raise time of speed to attain the reference rpm is very low for closed loop V/f controlled IM
drive when compared with open loop V/f controlled IM drive and during the load disturbance, the open loop
V/f controlled IM drive fails to attain the speed at least nearby the reference. Whereas, the closed loop V/f
control effectively regulates the error in speed during load commotion. Figure 10 shows the stator current of
IM in the proposed scheme during load disturbance.
(a) (b)
Figure 10. Stator Current of IM (a) Open loop V/f control (b) Closed Loop V/f control
2.5 2.6 2.7 2.8 2.9 3
-400
-200
0
200
400
Time (s)
Voltage(V)
Line Output Voltage of VSI
0 0.5 1 1.5 2 2.5 3
0
200
400
600
800
1000
1200
Time (s)
Speed(rpm)
Speed of IM
Reference Speed
Actual Speed
0 0.5 1 1.5 2 2.5 3
0
200
400
600
800
1000
1200
Time (s)
Speed(rpm)
Speed of IM
Reference Speed
Actual Speed
Loading Point
2.5 2.6 2.7 2.8 2.9 3
-20
-10
0
10
20
Time (s)
Current(A)
Stator Current of IM
Phase-a
Phase-b
Phase-c
2.5 2.6 2.7 2.8 2.9 3
-20
-10
0
10
20
Time (s)
Current(A)
Stator Current of IM
Phase-a
Phase-b
Phase-c

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From Figure 10, it is apparent that the undulation in the stator current of IM is high during open loop
V/f control when compared with the stator current of IM during closed loop V/f control operation and
corresponding THD in stator current for both the schemes were presented in Figure 11.
(a) (b)
Figure 11. THD in stator current of IM (a) during open loop V/f control (b) during closed loop V/f control
5. EXPERIMENTAL WORK AND RESULTS
The Hardware model of the proposed open loop and closed loop V/f controlled IM drive
incorporated with PI controlled EPOSLLC is shown in Figure 12 and Table 3 show the experimental
parameters used in the proposed configuration. The separate algorithm for open loop and closed loop V/f
control topology is developed which is embedded in FPGA spartan-6 processor for generating gate pulse to
VSI.
Figure 12. Hardware model composed of 1phase AC supply, Power Electronic converters, FPGA processor,
IM and Tektronix Oscilloscope
Tablel 3. Experimental Parameters
Parameter Rating
Input AC Supply 1 phase, 100V, 50Hz
Inductor L11 = 3mH, L21 = 2.56mH
Capacitors C21 = 200µF, Co = 1320µF
Diodes MVR3060, 600V, 30A
Voltage Source Inverter IGBT Inverter
Switches SKM100GB12T4, 1200V, 100A, 20Khz switching Frequency
Three phase Induction motor 0.5 hp ,3-phase, 50Hz,400V
Processor FPGA Spartan-6
0 200 400 600 800 1000
0
5
10
15
20
Frequency (Hz)
Fundamental (50Hz) = 2.949 , THD= 4.42%
Mag(%ofFundamental)
0 200 400 600 800 1000
0
5
10
15
20
Frequency (Hz)
Fundamental (50Hz) = 2.942 , THD= 1.63%
Mag(%ofFundamental)

401
The IM terminal voltage (line voltage of VSI) and DC link voltage is presented in Figure 13.
(a) (b)
Figure 13. (a) Line output voltage of VSI (CH2) with x-axis scale (1div. = 5ms) and y-axis scale (1div. =
100V) (b) DC link Voltage (CH2) with x-axis scale (1div. = 25ms) and y-axis scale (1div. = 50V)
The speed of IM in the experimental setup is measured at the terminals of Spartan-6 processor
through a digital to analog convertor and hence the speed response is measured in terms of voltage. Figure 14
shows the speed response (Channel-1) of IM for 1000rpm reference speed (Channel-2) and the load torque of
0.5N.m applied at 400ms. The result of speed response validates the feasibility of closed loop V/f control
over open loop V/f control for the proposed model.
(a) (b)
Figure 14. Speed response of IM for load disturbance (a) during open loop V/f control (b) during closed loop
V/f control with x-axis scale (1div. = 500ms) and y-axis scale (1div. = 166.66rpm)
The THD in the stator current during the experimental work is measured and is shown in Figure 15.
(a) (b)
Figure 15. THD in Stator current of IM (a) during open loop V/f control (b) during closed loop V/f control

 ISSN: 2088-8694
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The THD in the stator current of IM during open loop V/f control is around 5% and during closed
loop V/f control is around 2% which legalizes the simulation result presented in Figure 11.
6. CONCLUSION
This paper presents the improved PI control of EPOSLLC incorporated in the façade end of open
loop and closed loop V/f controlled IM drive. Experimental and Simulation results such as DC link voltage,
speed response of IM and THD in the stator current of IM are obtained. On observing the speed response of
IM, the regulation time for load disturbance is very low for closed loop V/f control of IM drive in both
simulation and hardware test, which validates the effectiveness of closed loop V/f control over open loop V/f
control without complex design. On the other hand, the speed response of IM during open loop V/f control
suggest that such control technique is accepted only for the applications like water pumping, compressors,
etc., where the speed change of IM is not required. The DC link ripple free voltage waveform verifies the
usefulness of proposed EPOSLLC in both the arrangements of IM drives. The scheme suggested utilize
minimum rectified DC voltage for driving a three phase IM and therefore, the design using renewable energy
as a source by eliminating the single phase AC supply cascading diode rectifier is possible. Basis of future
work has been left for the alteration and implementations of experimental drives under involvement of some
other control techniques.
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403
BIOGRAPHIES OF AUTHORS
P.Elangovan did his BE in Electrical and Electronics Engineering at Kamban Engineering
College under Anna University, Tamil Nadu, India. He has completed ME in Power Electronics
and Drives at Arunai Engineering College under Anna University, Tamil Nadu, India. Presently,
he is pursuing Doctoral degree at Anna University, Tamil Nadu, India and also working as
Assistant Professor in the department of EEE at S.K.P. Engineering College, Tamil Nadu, India.
He has research publications in refereed International Journals and Conference. His research area
includes Power Electronics, Induction Motor Drives and Advanced DC- DC converters.
Nalin Kant Mohanty has secured M.Tech degree in Computer Applications In Industrial Drives
from Visveswaraiah Technological University, Karnataka. He received Ph.D from Anna
University, Tamil Nadu, India. He is a fellow and registered Chatard Engineer of the Institution
of Engineers India. He is Life Member of ISTE, ISCA and SESI. Presently he is working as
Professor in the department of Electrical and Electronics Engineering of Sri Venkateswara
College of Engineering, Tamilnadu, India. He has more than 15 years teaching experience and
published 20 research papers in refereed international journals and Conferences. His research
area includes Power Electronics, Electric motor drives and contol, power quality and renewable
energy systems.

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