fpgartl-verilog-coding-for-sequential-circuit.pptx

• Register transfer level (RTL) Design
and Examples
• Register transfer level (RTL) Design
• Examples of RTL Verilog code
1
Register transfer level (RTL) Design

Register transfer level (RTL) Design Digital Circuit
2
Structural Verilog code is not practicable for designing complex circuit. In that case,
RTLVerilog code
is used to design digital circuit. RTL Verilog code of a digital design can be written in
two ways:
1) Using continuous assignment structures.
2) Using Procedural assignment structures.
RTL Coding using continuous assignment
• Modeling of digital circuit using continuous assignment structure is higher level of
abstraction than
structural Verilogcoding.
• It is named as continuous assignment because the assignments written in this
procedure are evaluated continuously whereas in procedural assignment
structure execution of a statement waits for the clock or other parameter. The
expression (in continuous assignment structure) is evaluated whenever any of
the operands changes.
• RTL coding using continuous assignment is usually used to model
combinational circuit which is
more complex than can be handled by structural modeling.
• The declaration ‘module’, ‘input’, ‘output’ and ‘endmodule’ are same as they

Examples RTL Verilog coding using continuous
Assignment
Example 1: Write Verilog code to represent the digital circuit that follows the
following logic equations.
Verilog
Code:
3

Assignment (Cont.)
Example 2: A single bit adder (full
adder).
Verilog
Code:
4

Assignment (Cont.)
Example 3: Write Verilog code to design 4-bit adder-subtractor circuit using
continuous assignment structure.
Verilog
Code:
5

Assignment (Cont.)
Example 3: Write Verilog code to design a 2/1 MUX using continuous
assignment structure.
Verilog
Code:
6

RTL Verilog Code using Procedural
Assignment
7
• Structural Verilog coding and Verilog coding using continuous assignment
structure are used to design simple digital circuit.This approach is practical
when functional complexities are not much (gate count within few hundred).
• With the increase of functional complexities, the above two approaches are not
suitable approach. In designing complex digital circuit, procedural assignment
approach is used.
• In this approach, the functional behavior of the circuit is described using keyword
‘always’.
• Sensitivity list is used with the ‘always’ statement. Sensitivity list indicates ‘output is
sensitive to
what?’. It contains the list of specific inputs, which have effect on the outputs.
• Whenever any event (change) occurs in any of the parameter in the sensitivity list,
the always loop
will be executed.
How to write RTL Verilog code using Procedural assignment
• The declaration ‘module’, ‘input’, ‘output’ and ‘endmodule’ are same as used in
structural Verilog coding and RTL Verilog coding using continuous assignment
structure.
• It is important to remember that all the outputs have to be declare as register using
the keyword ‘reg’.
• The keyword ‘always’ is used to describe the behavior of the circuit. Sensitivity list
has been placed inside the first bracket. The keyword ‘begin and ‘end’ indicates

Example of RTL Verilog Coding using Procedural
Assignment
Example 1: RTL Verilog code using procedural assignment to
design a 2/1 MUX
Verilog Code:
8

Example of RTL Verilog Coding using Procedural Assignment
(Continued)
Example 2: RTL Verilog code using procedural assignment to
design a 4/1 MUX
Verilog Code:
9

(Continued)
Example 3: RTL Verilog code using procedural assignment to design
a 2/4 Decoder
Verilog Code:
10

4'b0011:
out=7'b0110000;
4'b0100:
out=7'b0011001;
4'b0101:
out=7'b0010010;
4'b0110:
out=7'b0000010;
4'b0111:
out=7'b1111000;
4'b1000:
out=7'b0000000;
4'b1001:
out=7'b0010000;
default:
(Continued)
Example 4: RTL Verilog code using procedural assignment to design a 7-
segment Decoder (for
common anode display).
Verilog Code:
module decoder(en, in,
out); input en;
input [3:0] in;
output [6:0] out;
reg [6:0] out;
always @(en or in)
begin
if(en==0) out=0;
else
begin
case(in)
4'b0000:
out=7'b1000000;
4'b0001:
out=7'b1111001;
11

RTL Verilog Coding for sequential
circuit
• Usually procedural assignment structure is used in designing sequential circuit.
• Declaration of ‘module’,‘input’,‘output’,‘reg’, ‘always’ and ‘endmodule’ are same
as used in RTL
Verilog code using procedural assignment for combinational circuit.
• The positive edge and negative edge of the clock and other signal (rst) are
indicated using the
keyword ‘posedge’ and ‘negedge’ respectively.
Examples of RTL Verilog Coding for sequential circuit
Example 1: D type flip-flop with Reset (Active Low)
12

(Continued)
Example 2: Design of a 4-bit binary up
counter.
13

Examples of RTL Verilog Coding for sequential circuit (Continued)
14
Example 3: Design of a 4-bit binary up-down
counter.

(Continued)
Example 4: Design of a counter having data loading facility.
Note: In some applications, it is necessary to have a counter to start counting from a
particular value (not
from zero). In this case the starting value needs to be loaded in the counter.
15

(Continued)
Example 5: Design a 4-bit Shift
Register
Module shift_4 (IN, OUT, clk, rst);
input IN, clk, rst;
output OUT;
reg M, N, O,OUT;
always @(posedge clk or posedge
rst) begin if(rst) begin
OUT=0
; M=0;
N=0;
O=0;
end
else begin
OUT=M
; M=N;
N=O;
O=IN;
end
end
endmod
ule
16

fpgartl-verilog-coding-for-sequential-circuit.pptx

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