This document provides an introduction and overview of ASIC functional verification. It is intended for both beginner and intermediate verification engineers who want to learn the full functional verification flow and write testbenches. The document contains many examples of SystemVerilog constructs with detailed explanations to help readers explore and learn different aspects of the language. It also provides links to additional tutorials on specific verification topics and methodologies. Experienced engineers can use it as a reference to experiment with examples of different SystemVerilog features. The document is intended to be updated continuously as the author gains more experience with verification.