SlideShare a Scribd company logo

The Verification Methodology Landscape

D
DVClub

This document discusses verification methodologies like OVM, VMM, and eRM. It provides an overview of their key features such as constrained random stimulus, coverage-driven verification, and reusable verification environments. It also examines standards development efforts and looks at trends like growing adoption of verification IP and efforts to improve interoperability between methodologies.

TechnologyDesign
1 of 24
Downloaded 96 times
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1 Copyright © 2008 by Doulos. All rights reserved. The Verification Methodology Landscape Jonathan Bromley, Doulos DVClub Bristol 22-April-2009
2 Copyright © 2008 by Doulos. All rights reserved. The Verification Methodology Landscape CONTENTS The M-word Languages, methodologies, tools and standards The big players: OVM, VMM, eRM Interoperability and convergence Conclusions?
3 Copyright © 2008 by Doulos. All rights reserved. TLM DUT Monitor Driver Verification Environment Stimulus generator Transactions Coverage collector Transaction recording Test controller Scoreboard / Checker
4 Copyright © 2008 by Doulos. All rights reserved. Design Under Test Constrained Random Verification 11001001 01001010 00001001 01110110 01100110 01001001 01001110 000010 010011 000010 100100 001000 110010 000011 Constrained random stimulus Checker Did we see a bug? Functional Coverage Are we done?Header Payload Checksum Constraints Increase coverage
5 Copyright © 2008 by Doulos. All rights reserved. The Verification Space Verification Acceleration + Emulation Formal Verification Simulation Equivalence Checking Property Checking Dynamic Formal Coverage Transaction Level Modelling Constrained Random Assertions Simulation Simulation Simulation Formal Simulation Formal Intelligent Testbench
6 Copyright © 2008 by Doulos. All rights reserved. What Our Customers Want • Ease of deployment • Customizable environment • but it must do something useful straight out of the box • Simple, uniform interface to any verification IP block • Gentle learning curve for the whole team • Power • Complex testcases co-ordinated across the whole environment • Randomization • Sophisticated coverage analysis • Interoperability • Every customer we meet has legacy verification IP
7 Copyright © 2008 by Doulos. All rights reserved. Methodology (or just a toolkit?) • Tame the language monster • e, SystemVerilog, C++ are big and complicated • Many ways to solve a problem • Wheel reinvention is a hazard • Toolkit • OOP encourages encapsulation of standard functionality in base classes • Ideal for component hierarchy, reporting, block-to-block communication, DUT connectivity • Methodology • Published methodology encourages interoperability and re-use • Promote best practice
8 Copyright © 2008 by Doulos. All rights reserved. Mature Language Standards • IEEE 1076 VHDL • IEEE 1850™ PSL • IEEE 1364 Verilog • IEEE 1800™ SystemVerilog • IEEE 1647™ e • ISO/IEC 14882 C++ • IEEE 1666™ SystemC • Tcl/Tk, Perl List unchanged for 4 years... 8 FPGA, RTL, Europe, Mil-Aero ASIC, RTL, USA/RoW Hardware verification Virtual hardware prototypes for S/W dev Hardware verification Crude Caricature Modelling, verification Scripting
9 Copyright © 2008 by Doulos. All rights reserved. New Standards Activity • Verilog and SystemVerilog unified • LRM this year, currently in ballot feedback • Major enhancements to assertions • Verification methodology • OVM 2.0, OVM-SC • VMM open-source • eRM3 - e / SV interoperability (Cadence) • OVM / VMM interoperability (Accellera) • SystemC TLM-2.0
10 Copyright © 2008 by Doulos. All rights reserved. The Big Methodology Players www.ovmworld.org www.vmmcentral.org www.cadence.comeRM
11 Copyright © 2008 by Doulos. All rights reserved. Environment Static View of Testbench DUT active agent Driver BFM Monitor BFM Sequ- encer passive agent Driver BFM Monitor BFM Sequ- encer checkerConfiguration simple ports (e) virtual interfaces (SV) eRM
12 Copyright © 2008 by Doulos. All rights reserved. Static View of Testbench (VMM) DUT Generator ... test_env env = new; env.run(); ... Transactor Driver Self Check Monitor High level transactions Checker Monitor Functional Coverage Properties Checker Atomic transactions Constraints; directed tests
13 Copyright © 2008 by Doulos. All rights reserved. OVM Key Features • Constrained random, coverage-driven verification • Separation of tests from verification environment • Configuration of verification environment • through a table • Verification IP reuse (canonical structure and guidelines) • TLM communication • Automation (where missing from SystemVerilog language) • Hierarchical sequential stimulus (sequences) • Standardized messaging
14 Copyright © 2008 by Doulos. All rights reserved. eRM Key Features • Constrained random, coverage-driven verification • Separation of tests from verification environment • Configuration of verification environment • through AOP extension and pre-run constraints • Verification IP reuse (rigorously standardized rules) • Communication via ports • Automation (using e language's macro features) • Hierarchical sequential stimulus (sequences) • Standardized messaging
15 Copyright © 2008 by Doulos. All rights reserved. VMM Key Features • Constrained random, coverage-driven verification • Configuration of verification environment • through configuration objects passed to verification components • Verification IP reuse (conventions) • Communication via channels, callbacks, notifications • Automation (scripts and macros) • Hierarchical sequential stimulus (scenarios) • Standardized messaging • Strongly influenced by RVM (Synopsys Vera)
16 Copyright © 2008 by Doulos. All rights reserved. Structure of an OVM Component class my_driver extends ovm_driver #(my_transaction); // ovm_seq_item_pull_port #(...) seq_item_port; my_dut_if_wrapper m_dut_if; function new(string name, ovm_component parent); super.new(name, parent); endfunction: new function void build; super.build(); endfunction: build virtual task run; forever begin ... end endtask: run endclass: my_driver TLM port (inherited) Connection to DUT Constructor Build phase callback Run phase callback Base class
17 Copyright © 2008 by Doulos. All rights reserved. Phase Methods (OVM) build connect end_of_elaboration start_of_simulation run extract check report Call factory Make TLM connections After connections hardened Post-processing Task (executed concurrently) Get ready to run Similar phase arrangements in VMM, eRM
18 Copyright © 2008 by Doulos. All rights reserved. Reconfigurable Environment (OVM) DUT Reusable verification environment Scoreboard Virtual sequencer Monitor Existing verification component Existing verification component Sequencer DriverMonitor Config Test Test set_config_* Customize environments set_inst_override_* set_type_override_* Customize types By type or instance path
19 Copyright © 2008 by Doulos. All rights reserved. Layered Sequential Stimulus DUTDriverDrive transactions into DUT tx1 tx2 tx3 Constrained random sequence of transactions seq1 seq2seq2 Virtual or layered sequences tx1 Tests enumerate possible top-level sequences Randomized transactions are not enough
20 Copyright © 2008 by Doulos. All rights reserved. ovm_env ovm_agent Virtual Sequences ovm_sequencer ovm_driver ovm_sequencer Component hierarchy Stimulus hierarchy (co-ordinated interfaces) DUT dut_if ovm_agent ovm_sequencer ovm_driver dut_if ovm_sequence ovm_sequence_item ovm_sequence
21 Copyright © 2008 by Doulos. All rights reserved. Scenario Generator (VMM) Verification environment Scenario generator Downstream transactor generator's output channel atomic scenario_set burst[1] [0] RMW[2] burst items select_scenario select copies of items
22 Copyright © 2008 by Doulos. All rights reserved. Now and Next • VMM: rapidly growing collection of "applications" • register abstraction layer, hierarchy, ... • OVM/VMM interoperability toolkits/standards • OVM/eRM mixed-language tools • OVM-SC • Increasing availability of verification IP
23 Copyright © 2008 by Doulos. All rights reserved. Conclusion • Interesting times • standards don't always keep up with user needs • Challenges for users choosing a new approach: • tools? • methodology? • decisions are not yet completely decoupled • Training is important: • VMM, OVM, eRM are not difficult ... • ... but jump-starting your efforts pays dividends
24 Copyright © 2008 by Doulos. All rights reserved.

More Related Content

PDF
Fpga Verification Methodology and case studies - Semisrael Expo2014
Avi Caspi
 
PDF
Challenges in Using UVM at SoC Level
DVClub
 
PDF
Formal Verification Techniques
DVClub
 
DOCX
Design Verification
Ishwaki Thakkar
 
PPTX
Verilog
Mohamed Rayan
 
PDF
Functional verification techniques EW16 session
Sameh El-Ashry
 
PPTX
Verilog presentation final
Ankur Gupta
 
PDF
Verification challenges and methodologies - SoC and ASICs
Dr. Shivananda Koteshwar
 
Fpga Verification Methodology and case studies - Semisrael Expo2014
Avi Caspi
 
Challenges in Using UVM at SoC Level
DVClub
 
Formal Verification Techniques
DVClub
 
Design Verification
Ishwaki Thakkar
 
Verilog
Mohamed Rayan
 
Functional verification techniques EW16 session
Sameh El-Ashry
 
Verilog presentation final
Ankur Gupta
 
Verification challenges and methodologies - SoC and ASICs
Dr. Shivananda Koteshwar
 

What's hot (20)

PDF
Session 9 advance_verification_features
Nirav Desai
 
PDF
How to create SystemVerilog verification environment?
Sameh El-Ashry
 
PDF
Verification Strategy for PCI-Express
DVClub
 
PDF
Basics of Functional Verification - Arrow Devices
Arrow Devices
 
PDF
2019 2 testing and verification of vlsi design_verification
Usha Mehta
 
PDF
Efficient Methodology of Sampling UVM RAL During Simulation for SoC Functiona...
Sameh El-Ashry
 
PPT
system verilog
Vinchipsytm Vlsitraining
 
PDF
Mixed signal verification challenges - slides
Régis SANTONJA
 
PDF
System verilog assertions (sva) ( pdf drive )
sivasubramanian manickam
 
PPTX
SOC Verification using SystemVerilog
Ramdas Mozhikunnath
 
PPTX
Uart
Aditee Apurvaa
 
PPTX
AXI Protocol.pptx
Yazan Yousef
 
PPTX
ASIC design verification
Gireesh Kallihal
 
PDF
Uvm presentation dac2011_final
sean chen
 
PPT
USB 3.0
Ali Habeeb
 
PDF
Verification Engineer - Opportunities and Career Path
Ramdas Mozhikunnath
 
PDF
Session 8 assertion_based_verification_and_interfaces
Nirav Desai
 
PDF
Design for Testability
kumar gavanurmath
 
PDF
Verilog ques
mrinalmishra21
 
PDF
CPU Verification
Ramdas Mozhikunnath
 
Session 9 advance_verification_features
Nirav Desai
 
How to create SystemVerilog verification environment?
Sameh El-Ashry
 
Verification Strategy for PCI-Express
DVClub
 
Basics of Functional Verification - Arrow Devices
Arrow Devices
 
2019 2 testing and verification of vlsi design_verification
Usha Mehta
 
Efficient Methodology of Sampling UVM RAL During Simulation for SoC Functiona...
Sameh El-Ashry
 
system verilog
Vinchipsytm Vlsitraining
 
Mixed signal verification challenges - slides
Régis SANTONJA
 
System verilog assertions (sva) ( pdf drive )
sivasubramanian manickam
 
SOC Verification using SystemVerilog
Ramdas Mozhikunnath
 
Uart
Aditee Apurvaa
 
AXI Protocol.pptx
Yazan Yousef
 
ASIC design verification
Gireesh Kallihal
 
Uvm presentation dac2011_final
sean chen
 
USB 3.0
Ali Habeeb
 
Verification Engineer - Opportunities and Career Path
Ramdas Mozhikunnath
 
Session 8 assertion_based_verification_and_interfaces
Nirav Desai
 
Design for Testability
kumar gavanurmath
 
Verilog ques
mrinalmishra21
 
CPU Verification
Ramdas Mozhikunnath
 
Ad

Viewers also liked (8)

PDF
Functial Verification Tutorials
guestbcfac5
 
PDF
System Verilog Functional Coverage
rraimi
 
PPT
VinTrain VLSI Training Academy
VinChip Systems - VinTrain VLSI Academy
 
PDF
System verilog verification building blocks
Nirav Desai
 
PDF
vlsi design flow
Anish Gupta
 
PPTX
vlsi design summer training ppt
Bhagwan Lal Teli
 
PPT
Introduction to VLSI
illpa
 
PPT
Basics Of VLSI
Avanish Agarwal
 
Functial Verification Tutorials
guestbcfac5
 
System Verilog Functional Coverage
rraimi
 
VinTrain VLSI Training Academy
VinChip Systems - VinTrain VLSI Academy
 
System verilog verification building blocks
Nirav Desai
 
vlsi design flow
Anish Gupta
 
vlsi design summer training ppt
Bhagwan Lal Teli
 
Introduction to VLSI
illpa
 
Basics Of VLSI
Avanish Agarwal
 
Ad

Similar to The Verification Methodology Landscape (20)

PPTX
SystemVerilog based OVM and UVM Verification Methodologies
Ramdas Mozhikunnath
 
PPTX
UVM_Full_Print_n.pptx
nikitha992646
 
PDF
UVM basics Arm Cpu verificationThis lecture aims to: ▪ demonstrate the need f...
kotasaitejaece225a04
 
PDF
UVM Basics.pdf
yaazhiniyanm1
 
PDF
Transaction Based Verification Methodology - 2000
Steve Cox
 
PDF
UVM ARCHITECTURE FOR VERIFICATION
IAEME Publication
 
PDF
UVM BASED REUSABLE VERIFICATION IP FOR WISHBONE COMPLIANT SPI MASTER CORE
VLSICS Design
 
PDF
UVM BASED REUSABLE VERIFICATION IP FOR WISHBONE COMPLIANT SPI MASTER CORE
VLSICS Design
 
PDF
UVM BASED REUSABLE VERIFICATION IP FOR WISHBONE COMPLIANT SPI MASTER CORE
VLSICS Design
 
PDF
Advanced Verification Methodology for Complex System on Chip Verification
VLSICS Design
 
PPTX
Workshop Outline ppt on UVM using sv.pptx
BEVARAVASUDEVAAP1813
 
PDF
MixedSignal UVM Demo CDNLive
Robert O. Peruzzi, PhD, PE, DFE
 
PDF
Ovm vs-uvm
Tuấn Nguyễn
 
PDF
Getting started with RISC-V verification what's next after compliance testing
RISC-V International
 
PDF
Tutorial getting started with RISC-V verification
RISC-V International
 
PPTX
arrow-devices-uvm-session-tutorial-150507071221-lva1-app6891.pptx
vasudeva873639
 
PPTX
Research Questions for Validation and Verification in the Context of Model-Ba...
Michalis Famelis
 
PDF
I Never Thought I Would Grow Up to be This Formal
DVClub
 
PDF
Harton-Presentation
Heather Harton
 
PDF
TMPA-2017: Technology and Tools for Developing Industrial Software Test Suite...
Iosif Itkin
 
SystemVerilog based OVM and UVM Verification Methodologies
Ramdas Mozhikunnath
 
UVM_Full_Print_n.pptx
nikitha992646
 
UVM basics Arm Cpu verificationThis lecture aims to: ▪ demonstrate the need f...
kotasaitejaece225a04
 
UVM Basics.pdf
yaazhiniyanm1
 
Transaction Based Verification Methodology - 2000
Steve Cox
 
UVM ARCHITECTURE FOR VERIFICATION
IAEME Publication
 
UVM BASED REUSABLE VERIFICATION IP FOR WISHBONE COMPLIANT SPI MASTER CORE
VLSICS Design
 
UVM BASED REUSABLE VERIFICATION IP FOR WISHBONE COMPLIANT SPI MASTER CORE
VLSICS Design
 
UVM BASED REUSABLE VERIFICATION IP FOR WISHBONE COMPLIANT SPI MASTER CORE
VLSICS Design
 
Advanced Verification Methodology for Complex System on Chip Verification
VLSICS Design
 
Workshop Outline ppt on UVM using sv.pptx
BEVARAVASUDEVAAP1813
 
MixedSignal UVM Demo CDNLive
Robert O. Peruzzi, PhD, PE, DFE
 
Ovm vs-uvm
Tuấn Nguyễn
 
Getting started with RISC-V verification what's next after compliance testing
RISC-V International
 
Tutorial getting started with RISC-V verification
RISC-V International
 
arrow-devices-uvm-session-tutorial-150507071221-lva1-app6891.pptx
vasudeva873639
 
Research Questions for Validation and Verification in the Context of Model-Ba...
Michalis Famelis
 
I Never Thought I Would Grow Up to be This Formal
DVClub
 
Harton-Presentation
Heather Harton
 
TMPA-2017: Technology and Tools for Developing Industrial Software Test Suite...
Iosif Itkin
 

More from DVClub (20)

PDF
IP Reuse Impact on Design Verification Management Across the Enterprise
DVClub
 
PDF
Cisco Base Environment Overview
DVClub
 
PDF
Intel Xeon Pre-Silicon Validation: Introduction and Challenges
DVClub
 
PDF
Verification of Graphics ASICs (Part II)
DVClub
 
PDF
Verification of Graphics ASICs (Part I)
DVClub
 
PDF
Stop Writing Assertions! Efficient Verification Methodology
DVClub
 
PPT
Validating Next Generation CPUs
DVClub
 
PPT
Verification Automation Using IPXACT
DVClub
 
PDF
Validation and Design in a Small Team Environment
DVClub
 
PDF
Trends in Mixed Signal Validation
DVClub
 
PDF
Verification In A Global Design Community
DVClub
 
PDF
Design Verification Using SystemC
DVClub
 
PDF
SystemVerilog Assertions (SVA) in the Design/Verification Process
DVClub
 
PDF
Efficiency Through Methodology
DVClub
 
PDF
Pre-Si Verification for Post-Si Validation
DVClub
 
PDF
OpenSPARC T1 Processor
DVClub
 
PDF
Intel Atom Processor Pre-Silicon Verification Experience
DVClub
 
PDF
Using Assertions in AMS Verification
DVClub
 
PDF
Low-Power Design and Verification
DVClub
 
PDF
UVM Update: Register Package
DVClub
 
IP Reuse Impact on Design Verification Management Across the Enterprise
DVClub
 
Cisco Base Environment Overview
DVClub
 
Intel Xeon Pre-Silicon Validation: Introduction and Challenges
DVClub
 
Verification of Graphics ASICs (Part II)
DVClub
 
Verification of Graphics ASICs (Part I)
DVClub
 
Stop Writing Assertions! Efficient Verification Methodology
DVClub
 
Validating Next Generation CPUs
DVClub
 
Verification Automation Using IPXACT
DVClub
 
Validation and Design in a Small Team Environment
DVClub
 
Trends in Mixed Signal Validation
DVClub
 
Verification In A Global Design Community
DVClub
 
Design Verification Using SystemC
DVClub
 
SystemVerilog Assertions (SVA) in the Design/Verification Process
DVClub
 
Efficiency Through Methodology
DVClub
 
Pre-Si Verification for Post-Si Validation
DVClub
 
OpenSPARC T1 Processor
DVClub
 
Intel Atom Processor Pre-Silicon Verification Experience
DVClub
 
Using Assertions in AMS Verification
DVClub
 
Low-Power Design and Verification
DVClub
 
UVM Update: Register Package
DVClub
 

Recently uploaded (20)

PPT
Module 1.ppt Iot fundamentals and Architecture
nanditha7766
 
PDF
A comparative study of natural language inference in Swahili using monolingua...
IAESIJAI
 
PDF
ENT215_Completing-a-large-scale-migration-and-modernization-with-AWS.pdf
ssuser28425f
 
PDF
Hindi spoken digit analysis for native and non-native speakers
IAESIJAI
 
PDF
Zenith AI: Advanced Artificial Intelligence
Biz Preneurs
 
PPTX
The various Industrial Revolutions .pptx
bandileshozi3
 
PDF
A contest of sentiment analysis: k-nearest neighbor versus neural network
IAESIJAI
 
PPTX
TechTalks-8-2019-Service-Management-ITIL-Refresh-ITIL-4-Framework-Supports-Ou...
bonakiduza1024
 
PDF
NewMind AI Weekly Chronicles – August ’25 Week III
NewMind AI
 
PPTX
Final SEM Unit 1 for mit wpu at pune .pptx
anishtilekar08
 
PDF
August Patch Tuesday
Ivanti
 
PDF
project resource management chapter-09.pdf
ssuser00e6e21
 
PPTX
Programs and apps: productivity, graphics, security and other tools
4mqw9zch22
 
PDF
DP Operators-handbook-extract for the Mautical Institute
LeonelMejiaLarios
 
PDF
Univ-Connecticut-ChatGPT-Presentaion.pdf
ry7r52mzb4
 
PDF
Developing a website for English-speaking practice to English as a foreign la...
IAESIJAI
 
PPT
What is a Computer? Input Devices /output devices
GulJan8
 
PDF
gpt5_lecture_notes_comprehensive_20250812015547.pdf
Chinchu40
 
PDF
Getting started with AI Agents and Multi-Agent Systems
Maxim Salnikov
 
PDF
WOOl fibre morphology and structure.pdf for textiles
Rajendrakumar868651
 
Module 1.ppt Iot fundamentals and Architecture
nanditha7766
 
A comparative study of natural language inference in Swahili using monolingua...
IAESIJAI
 
ENT215_Completing-a-large-scale-migration-and-modernization-with-AWS.pdf
ssuser28425f
 
Hindi spoken digit analysis for native and non-native speakers
IAESIJAI
 
Zenith AI: Advanced Artificial Intelligence
Biz Preneurs
 
The various Industrial Revolutions .pptx
bandileshozi3
 
A contest of sentiment analysis: k-nearest neighbor versus neural network
IAESIJAI
 
TechTalks-8-2019-Service-Management-ITIL-Refresh-ITIL-4-Framework-Supports-Ou...
bonakiduza1024
 
NewMind AI Weekly Chronicles – August ’25 Week III
NewMind AI
 
Final SEM Unit 1 for mit wpu at pune .pptx
anishtilekar08
 
August Patch Tuesday
Ivanti
 
project resource management chapter-09.pdf
ssuser00e6e21
 
Programs and apps: productivity, graphics, security and other tools
4mqw9zch22
 
DP Operators-handbook-extract for the Mautical Institute
LeonelMejiaLarios
 
Univ-Connecticut-ChatGPT-Presentaion.pdf
ry7r52mzb4
 
Developing a website for English-speaking practice to English as a foreign la...
IAESIJAI
 
What is a Computer? Input Devices /output devices
GulJan8
 
gpt5_lecture_notes_comprehensive_20250812015547.pdf
Chinchu40
 
Getting started with AI Agents and Multi-Agent Systems
Maxim Salnikov
 
WOOl fibre morphology and structure.pdf for textiles
Rajendrakumar868651
 

The Verification Methodology Landscape

  • 1. 1 Copyright © 2008 by Doulos. All rights reserved. The Verification Methodology Landscape Jonathan Bromley, Doulos DVClub Bristol 22-April-2009
  • 2. 2 Copyright © 2008 by Doulos. All rights reserved. The Verification Methodology Landscape CONTENTS The M-word Languages, methodologies, tools and standards The big players: OVM, VMM, eRM Interoperability and convergence Conclusions?
  • 3. 3 Copyright © 2008 by Doulos. All rights reserved. TLM DUT Monitor Driver Verification Environment Stimulus generator Transactions Coverage collector Transaction recording Test controller Scoreboard / Checker
  • 4. 4 Copyright © 2008 by Doulos. All rights reserved. Design Under Test Constrained Random Verification 11001001 01001010 00001001 01110110 01100110 01001001 01001110 000010 010011 000010 100100 001000 110010 000011 Constrained random stimulus Checker Did we see a bug? Functional Coverage Are we done?Header Payload Checksum Constraints Increase coverage
  • 5. 5 Copyright © 2008 by Doulos. All rights reserved. The Verification Space Verification Acceleration + Emulation Formal Verification Simulation Equivalence Checking Property Checking Dynamic Formal Coverage Transaction Level Modelling Constrained Random Assertions Simulation Simulation Simulation Formal Simulation Formal Intelligent Testbench
  • 6. 6 Copyright © 2008 by Doulos. All rights reserved. What Our Customers Want • Ease of deployment • Customizable environment • but it must do something useful straight out of the box • Simple, uniform interface to any verification IP block • Gentle learning curve for the whole team • Power • Complex testcases co-ordinated across the whole environment • Randomization • Sophisticated coverage analysis • Interoperability • Every customer we meet has legacy verification IP
  • 7. 7 Copyright © 2008 by Doulos. All rights reserved. Methodology (or just a toolkit?) • Tame the language monster • e, SystemVerilog, C++ are big and complicated • Many ways to solve a problem • Wheel reinvention is a hazard • Toolkit • OOP encourages encapsulation of standard functionality in base classes • Ideal for component hierarchy, reporting, block-to-block communication, DUT connectivity • Methodology • Published methodology encourages interoperability and re-use • Promote best practice
  • 8. 8 Copyright © 2008 by Doulos. All rights reserved. Mature Language Standards • IEEE 1076 VHDL • IEEE 1850™ PSL • IEEE 1364 Verilog • IEEE 1800™ SystemVerilog • IEEE 1647™ e • ISO/IEC 14882 C++ • IEEE 1666™ SystemC • Tcl/Tk, Perl List unchanged for 4 years... 8 FPGA, RTL, Europe, Mil-Aero ASIC, RTL, USA/RoW Hardware verification Virtual hardware prototypes for S/W dev Hardware verification Crude Caricature Modelling, verification Scripting
  • 9. 9 Copyright © 2008 by Doulos. All rights reserved. New Standards Activity • Verilog and SystemVerilog unified • LRM this year, currently in ballot feedback • Major enhancements to assertions • Verification methodology • OVM 2.0, OVM-SC • VMM open-source • eRM3 - e / SV interoperability (Cadence) • OVM / VMM interoperability (Accellera) • SystemC TLM-2.0
  • 10. 10 Copyright © 2008 by Doulos. All rights reserved. The Big Methodology Players www.ovmworld.org www.vmmcentral.org www.cadence.comeRM
  • 11. 11 Copyright © 2008 by Doulos. All rights reserved. Environment Static View of Testbench DUT active agent Driver BFM Monitor BFM Sequ- encer passive agent Driver BFM Monitor BFM Sequ- encer checkerConfiguration simple ports (e) virtual interfaces (SV) eRM
  • 12. 12 Copyright © 2008 by Doulos. All rights reserved. Static View of Testbench (VMM) DUT Generator ... test_env env = new; env.run(); ... Transactor Driver Self Check Monitor High level transactions Checker Monitor Functional Coverage Properties Checker Atomic transactions Constraints; directed tests
  • 13. 13 Copyright © 2008 by Doulos. All rights reserved. OVM Key Features • Constrained random, coverage-driven verification • Separation of tests from verification environment • Configuration of verification environment • through a table • Verification IP reuse (canonical structure and guidelines) • TLM communication • Automation (where missing from SystemVerilog language) • Hierarchical sequential stimulus (sequences) • Standardized messaging
  • 14. 14 Copyright © 2008 by Doulos. All rights reserved. eRM Key Features • Constrained random, coverage-driven verification • Separation of tests from verification environment • Configuration of verification environment • through AOP extension and pre-run constraints • Verification IP reuse (rigorously standardized rules) • Communication via ports • Automation (using e language's macro features) • Hierarchical sequential stimulus (sequences) • Standardized messaging
  • 15. 15 Copyright © 2008 by Doulos. All rights reserved. VMM Key Features • Constrained random, coverage-driven verification • Configuration of verification environment • through configuration objects passed to verification components • Verification IP reuse (conventions) • Communication via channels, callbacks, notifications • Automation (scripts and macros) • Hierarchical sequential stimulus (scenarios) • Standardized messaging • Strongly influenced by RVM (Synopsys Vera)
  • 16. 16 Copyright © 2008 by Doulos. All rights reserved. Structure of an OVM Component class my_driver extends ovm_driver #(my_transaction); // ovm_seq_item_pull_port #(...) seq_item_port; my_dut_if_wrapper m_dut_if; function new(string name, ovm_component parent); super.new(name, parent); endfunction: new function void build; super.build(); endfunction: build virtual task run; forever begin ... end endtask: run endclass: my_driver TLM port (inherited) Connection to DUT Constructor Build phase callback Run phase callback Base class
  • 17. 17 Copyright © 2008 by Doulos. All rights reserved. Phase Methods (OVM) build connect end_of_elaboration start_of_simulation run extract check report Call factory Make TLM connections After connections hardened Post-processing Task (executed concurrently) Get ready to run Similar phase arrangements in VMM, eRM
  • 18. 18 Copyright © 2008 by Doulos. All rights reserved. Reconfigurable Environment (OVM) DUT Reusable verification environment Scoreboard Virtual sequencer Monitor Existing verification component Existing verification component Sequencer DriverMonitor Config Test Test set_config_* Customize environments set_inst_override_* set_type_override_* Customize types By type or instance path
  • 19. 19 Copyright © 2008 by Doulos. All rights reserved. Layered Sequential Stimulus DUTDriverDrive transactions into DUT tx1 tx2 tx3 Constrained random sequence of transactions seq1 seq2seq2 Virtual or layered sequences tx1 Tests enumerate possible top-level sequences Randomized transactions are not enough
  • 20. 20 Copyright © 2008 by Doulos. All rights reserved. ovm_env ovm_agent Virtual Sequences ovm_sequencer ovm_driver ovm_sequencer Component hierarchy Stimulus hierarchy (co-ordinated interfaces) DUT dut_if ovm_agent ovm_sequencer ovm_driver dut_if ovm_sequence ovm_sequence_item ovm_sequence
  • 21. 21 Copyright © 2008 by Doulos. All rights reserved. Scenario Generator (VMM) Verification environment Scenario generator Downstream transactor generator's output channel atomic scenario_set burst[1] [0] RMW[2] burst items select_scenario select copies of items
  • 22. 22 Copyright © 2008 by Doulos. All rights reserved. Now and Next • VMM: rapidly growing collection of "applications" • register abstraction layer, hierarchy, ... • OVM/VMM interoperability toolkits/standards • OVM/eRM mixed-language tools • OVM-SC • Increasing availability of verification IP
  • 23. 23 Copyright © 2008 by Doulos. All rights reserved. Conclusion • Interesting times • standards don't always keep up with user needs • Challenges for users choosing a new approach: • tools? • methodology? • decisions are not yet completely decoupled • Training is important: • VMM, OVM, eRM are not difficult ... • ... but jump-starting your efforts pays dividends
  • 24. 24 Copyright © 2008 by Doulos. All rights reserved.