FYBSC IT Digital Electronics Unit IV Chapter II Sequential Circuits- Flip-Flops

SEQUENTIAL
CIRCUITS:
FLIP-FLOPS
UNIT IV
DIGITAL
ELECTRONICS
PROF.ARTI GAVAS-PARAB
ANNA LEELA COLLEGE OF COMMERCE AND ECONOMICS, SHOBHA
JAYARAM SHETTY COLLEGE FOR BMS
CHAPTER II

UNIT IV: CONTENTS
 Multiplexer, De-multiplexer,ALU, Encoder and Décoder:
 Introduction,
 Multiplexer, De-multiplexer,
 Encoder, Décoder,
 ALUs
 Sequential Circuits: Flip-Flop:
 Introduction,Terminologies used, S-R flip-flop, D flip-fop, JK flip-flop,
 Race-around condition,
 Master – slave JK flip-flop,
 T flip-flop,
 conversion from one type of flip-flop to another,
 Application of flip-flops
C
H
A
P
T
E
R
I
C
H
A
P
T
E
R
II

SEQUENTIAL CIRCUITS: INTRODUCTION
 Combinational circuits have a set of outputs s, which
depends only on the combination of present inputs.
 This sequential circuit contains a set of inputs and
outputs s.The outputs s of sequential circuit depends
not only on the combination of present inputs but
also on the previous outputs s. Previous output is
nothing but the present state.Therefore, sequential
circuits contain combinational circuits along with
memory storage elements.
 Some sequential circuits may not contain
combinational circuits, but only memory elements.
 The figure shows the block diagram of sequential
circuit.

SEQUENTIAL CIRCUITS: INTRODUCTION
 Following table shows the differences between combinational circuits and sequential circuits.
Combinational Circuits Sequential Circuits
Outputs depend only on present inputs. Outputs depend on both present inputs and present state.
Feedback path is not present. Feedback path is present.
Memory elements are not required. Memory elements are required.
Clock signal is not required. Clock signal is required.
Easy to design. Difficult to design.
 Following are the two types of sequential circuits −
 Asynchronous sequential circuits
 Synchronous sequential circuits

SYNCHRONOUS /ASYNCHRONOUS SEQUENTIAL CIRCUITS
 Synchronous sequential circuits
 If all the outputs of a sequential circuit change/affect with respect to active transition of clock signal, then that sequential
circuit is called as Synchronous sequential circuit.
 That means, all the outputs of synchronous sequential circuits change/affect at the same time.
 Therefore, the outputs of synchronous sequential circuits are in synchronous with either only positive edges or only
negative edges of clock signal.
 Asynchronous sequential circuits
 If some or all the outputs of a sequential circuit do not change/affect with respect to active transition of clock signal, then
that sequential circuit is called as Asynchronous sequential circuit.
 That means, all the outputs of asynchronous sequential circuits do not change/affect at the same time.
 Therefore, most of the outputs of asynchronous sequential circuits are not in synchronous with either only positive edges
or only negative edges of clock signal.

CLOCK SIGNAL AND TRIGGERING
 Clock signal
 Clock signal is a periodic signal and its ON time and OFF
time need not be the same.
 We can represent the clock signal as a square wave, when
both its ON time and OFF time are same.This clock signal
is shown in the following figure.
 The reciprocal of the time period of clock signal is known as the frequency of the clock signal.
 All sequential circuits are operated with clock signal.
 So, the frequency at which the sequential circuits can be operated accordingly the clock signal frequency has to
be chosen.
 Types ofTriggering
 Level triggering
 Edge triggering

TYPES OFTRIGGERING: LEVEL TRIGGERING
 There are two levels, namely logic High and logic Low
in clock signal. Following are the two types of level
triggering.
 Positive level triggering
 Negative level triggering
 If the sequential circuit is operated with the clock
signal when it is in Logic High, then that type of
triggering is known as Positive level triggering. It is
highlighted in First figure.
 If the sequential circuit is operated with the clock
signal when it is in Logic Low, then that type of
triggering is known as Negative level triggering. It
is highlighted in the Second figure.

TYPES OFTRIGGERING: EDGE TRIGGERING
 There are two types of transitions that occur in clock signal.
That means, the clock signal transitions either from Logic
Low to Logic High or Logic High to Logic Low.
 Following are the two types of edge triggering based on
the transitions of clock signal.
 Positive edge triggering
 Negative edge triggering
 If the sequential circuit is operated with the clock signal that
is transitioning from Logic Low to Logic High, then that type
of triggering is known as Positive edge triggering. It is also
called as rising edge triggering. It is shown in the first figure.
 If the sequential circuit is operated with the clock signal that
is transitioning from Logic High to Logic Low, then that type
of triggering is known as Negative edge triggering. It is
also called as falling edge triggering. It is shown in the second
figure.

FLIP-FLOP
 The combinational circuit does not use any memory.
Hence the previous state of input does not have any effect
on the present state of the circuit.
 But sequential circuit has memory so output can vary
based on input.This type of circuits uses previous input,
output, clock and a memory element.
 Flip Flop
 Flip flop is a sequential circuit which generally samples its
inputs and changes its outputs only at particular instants
of time and not continuously.
 Flip flop is said to be edge sensitive or edge triggered
rather than being level triggered like latches.

S-R FLIP FLOP
 It is basically S-R latch using NAND gates with an additional enable input.
 It is also called as level triggered SR-FF.
 For this, circuit in output will take place if and only if the enable input (E) is made active.
 In short this circuit will operate as an S-R latch if E = 1 but there is no change in the output if E = 0.
Block Diagram Circuit Diagram Truth Table

S-R FLIP FLOP: OPERATION
S.N. Condition Operation
1 S = R = 0 : No change If S = R = 0 then output of NAND gates 3 and 4 are forced to become 1.
Hence R' and S' both will be equal to 1. Since S' and R' are the input of the basic S-R latch
using NAND gates, there will be no change in the state of outputs.
2 S = 0, R = 1, E = 1 Since S = 0, output of NAND-3 i.e. R' = 1 and E = 1 the output of NAND-4 i.e. S' = 0.
Hence Qn+1 = 0 and Qn+1 bar = 1.This is reset condition.
3 S = 1, R = 0, E = 1 Output of NAND-3 i.e. R' = 0 and output of NAND-4 i.e. S' = 1.
Hence output of S-R NAND latch is Qn+1 = 1 and Qn+1 bar = 0.This is the Set condition.
4 S = 1, R = 1, E = 1 As S = 1, R = 1 and E = 1, the output of NAND gates 3 and 4 both are 0 i.e. S' = R' = 0.
Hence the Race condition will occur in the basic NAND latch.

DELAY FLIP FLOP / D FLIP FLOP
 Delay Flip Flop or D Flip Flop is the simple gated S-R latch with a NAND inverter connected between S and R
inputs. It has only one input.The input data is appearing at the output after some time. Due to this data delay
between i/p and o/p, it is called delay flip flop. S and R will be the complements of each other due to NAND
inverter. Hence S = R = 0 or S = R = 1, these input condition will never appear.This problem is avoid by SR = 00
and SR = 1 conditions.
Block Diagram Circuit Diagram Truth Table

D FLIP FLOP: OPERATION
1 E = 0 Latch is disabled. Hence no change in output.
2 E = 1 and D = 0 If E = 1 and D = 0 then S = 0 and R = 1. Hence irrespective of the present state, the next
state is Qn+1 = 0 and Qn+1 bar = 1.This is the reset condition.
3 E = 1 and D = 1 If E = 1 and D = 1, then S = 1 and R = 0. This will set the latch and Qn+1 = 1 and Qn+1 bar
= 0 irrespective of the present state.

TOGGLE FLIP FLOP / T FLIP FLOP
 Toggle flip flop is basically a JK flip flop with J and K terminals permanently connected together. It has only input
denoted by T as shown in the Symbol Diagram.The symbol for positive edge triggeredT flip flop is shown in the
Block Diagram.
Symbol/ Block Diagram Circuit Diagram Truth Table

T FLIP FLOP: OPERATION
1 T = 0, J = K = 0 The output Q and Q bar won't change
2 T = 1, J = K = 1 Output will toggle corresponding to every leading edge of clock signal.

JK FLIP FLOP
 JK Flip flop is the ideal and important memory element which behaves the same fashion as RS flip flop except the
condition where R & S equals to 1.
 A JK-FF is a simplification of the SR-flip flop.The inputs of the J and K flip flops behave like the inputs S & R.When
input 1 is applied to both the inputs J and K, then the FF switches to its complement state.
 It is a forbidden in RS flip flop, the JK flip flop is an improved version which avoids this prohibited or impracticable
state and converts in to toggle state. i.e. when J=1 and K=1 the output is the inversion of the last state.
 J and K in the JK flip flop means Jack and Kilby who invented this flip flop combination.
 This toggling condition is mostly used in the counters.

JK FLIP-FLOP
 JK flip-flop is the modified version of SR flip-flop. It operates with only positive clock transitions or negative clock transitions.
 The circuit diagram of JK flip-flop is shown in the following figure.
 This circuit has two inputs J & K and two outputs Qt & Qt’.The operation of JK flip-flop is similar to SR flip-flop.
J K Qt+1
0 0 Qt (No change)
0 1 0 (Reset)
1 0 1 (Set)
1 1 Qt‘ (Toggle)
 Here, Qt & Qt+1 are present state &
next state respectively.
 So, JK flip-flop can be used for one of
these four functions such as Hold,
Reset, Set & Complement of present
state based on the input conditions,
when positive transition of clock signal
is applied.
 The truth table shows the
characteristic table of JK flip-flop.
Circuit Diagram Truth Table

RACE-AROUND CONDITION OF JK FLIP FLOP
 In JK flip flop as long as clock is high for the input conditions J&K equals to the output changes or complements
its output from 1–>0 and 0–>1.
 This is called toggling output or uncontrolled changing or racing condition.
 As long as clock is high and J&K=11 then two upper and lower AND gates are only triggered by the
complementary outputs Q and Q(bar). I.e. in any condition according to the propagation delay one gate will be
enabled and another gate is disabled.
 If upper gate is disabled then it sets the output and in the next lower gate will be enabled which resets the flip
flop output.
 If the flip flop is made to toggle over one clock period then racing can be avoided.This introduced the concept of
Master Slave JK flip flop.

MASTER SLAVE JK FLIP FLOP
 Master slave JK FF is a cascade of two S-R FF with feedback from the output of second to input of first.
 Master is a positive level triggered. But due to the presence of the inverter in the clock line, the slave will respond
to the negative level. Hence when the clock = 1 (positive level) the master is active and the slave is inactive.
Whereas when clock = 0 (low level) the slave is active and master is inactive.
Circuit Diagram Truth Table

MASTER SLAVE JK FLIP FLOP: OPERATION
1 J = K = 0
(No change)
When clock = 0, the slave becomes active and master is inactive. But since the S and R inputs have not changed,
the slave outputs will also remain unchanged.Therefore outputs will not change if J = K =0.
2 J = 0 and K = 1
(Reset)
Clock = 1 − Master active, slave inactive. Therefore outputs of the master become Q1 = 0 and Q1 bar = 1. That
means S = 0 and R =1.
Clock = 0 − Slave active, master inactive.Therefore outputs of the slave become Q = 0 and Q bar = 1.
Again clock = 1 − Master active, slave inactive. Therefore even with the changed outputs Q = 0 and Q bar = 1 fed
back to master, its output will be Q1 = 0 and Q1 bar = 1.That means S = 0 and R = 1.
Hence with clock = 0 and slave becoming active the outputs of slave will remain Q = 0 and Q bar = 1. Thus we get
a stable output from the Master slave.
3 J = 1 and K = 0
(Set)
Clock = 1 − Master active, slave inactive. Therefore outputs of the master become Q1 = 1 and Q1 bar = 0. That
means S = 1 and R =0.
Clock = 0 − Slave active, master inactive.Therefore outputs of the slave become Q = 1 and Q bar = 0.
Again clock = 1 − then it can be shown that the outputs of the slave are stabilized to Q = 1 and Q bar = 0.
4 J = K = 1
(Toggle)
Clock = 1 − Master active, slave inactive. Outputs of master will toggle. So S and R also will be inverted.
Clock = 0 − Slave active, master inactive. Outputs of slave will toggle.
These changed output are returned back to the master inputs. But since clock = 0, the master is still inactive. So it
does not respond to these changed outputs. This avoids the multiple toggling which leads to the race around
condition.The master slave flip flop will avoid the race around condition.

CONVERSION FROM ONE TYPE OF FLIP-FLOP TO ANOTHER
 Flip flop conversions, where one type of flip flop is converted to another type.
 For the conversion of one flip flop to another, a combinational circuit has to be designed first. If a JK Flip Flop is
required, the inputs are given to the combinational circuit and the output of the combinational circuit is connected to
the inputs of the actual flip flop.Thus, the output of the actual flip flop is the output of the required flip flop.
 Following flip flop conversions will be explained.
 SR Flip Flop to JK Flip Flop
 JK Flip Flop to SR Flip Flop
 SR Flip Flop to D Flip Flop
 D Flip Flop to SR Flip Flop
 JK Flip Flop toT Flip Flop
 JK Flip Flop to D Flip Flop
 D Flip Flop to JK Flip Flop

SR FLIP FLOP TO JK FLIP FLOP
 J and K will be given as external inputs to S and R.As
shown in the logic diagram, S and R will be the outputs
of the combinational circuit.
 The truth tables for the flip flop conversion are given
below.The present state is represented by Qp and Qp+1
is the next state to be obtained when the J and K inputs
are applied.
 For two inputs J and K, there will be eight possible
combinations. For each combination of J, K and Qp, the
corresponding Qp+1 states are found. Qp+1 simply
suggests the future values to be obtained by the JK flip
flop after the value of Qp.
 The table is then completed by writing the values of S
and R required to get each Qp+1 from the
corresponding Qp.
 That is, the values of S and R that are required to change
the state of the flip flop from Qp to Qp+1 are written.

JK FLIP FLOPTO SR FLIP FLOP
 This will be the reverse process of the above explained
conversion.
 S and R will be the external inputs to J and K.As shown
in the logic diagram, J and K will be the outputs of the
combinational circuit.Thus, the values of J and K have to
be obtained in terms of S, R and Qp.
 A conversion table is to be written using S, R, Qp,
Qp+1, J and K.
 For two inputs, S and R, eight combinations are made.
For each combination, the corresponding Qp+1 outputs
are found ut.The outputs for the combinations of S=1
and R=1 are not permitted for an SR flip flop.
 Thus the outputs are considered invalid and the J and K
values are taken as “don’t cares”.

SR FLIP FLOP TO D FLIP FLOP
 As shown in the figure, S and R are the actual inputs of the flip flop and D is the external input of the flip flop.
 The four combinations, the logic diagram, conversion table, and the K-map for S and R in terms of D and Qp are
shown below.

D FLIP FLOP TO SR FLIP FLOP
 D is the actual input of the flip flop and S and R are the external inputs. Eight possible combinations are achieved
from the external inputs S, R and Qp. But, since the combination of S=1 and R=1 are invalid, the values of Qp+1
and D are considered as “don’t cares”.The logic diagram showing the conversion from D to SR, and the K-map
for D in terms of S, R and Qp are shown below.

JK FLIP FLOPTO T FLIP FLOP
 J and K are the actual inputs of the flip flop andT is taken as the external input for conversion. Four combinations
are produced with T and Qp. J and K are expressed in terms ofT and Qp.The conversion table, K-maps, and the
logic diagram are given below.

JK FLIP FLOPTO D FLIP FLOP
 D is the external input and J and K are the actual inputs of the flip flop. D and Qp make four combinations. J and
K are expressed in terms of D and Qp.The four combination conversion table, the K-maps for J and K in terms of
D and Qp, and the logic diagram showing the conversion from JK to D are given below.

D FLIP FLOP TO JK FLIP FLOP
 In this conversion, D is the actual input to the flip flop and J and K are the external inputs. J, K and Qp make eight
possible combinations, as shown in the conversion table below. D is expressed in terms of J, K and Qp.
 The conversion table, the K-map for D in terms of J, K and Qp and the logic diagram showing the conversion from D to
JK are given in the figure below.

APPLICATION OF FLIP-FLOPS
 Application of the flip flop circuit mainly involves in bounce elimination switch, data storage, data transfer, latch,
registers, counters, frequency division, memory, etc.
 A register: is a collection of a set of flip flops used to store a set of bits. For instance, if you want to store an
N – bit of words you need N number of FFS.AFF can store only one bit of data (0 or 1).A number of FFs are
used when the number of data bits to be stored.
 RAM: is used in computers, information processing systems, digital control systems it is necessary to store
digital data and recover the data as preferred. FFS can be used to make memories in which information can be
stored for any required length of time and then deliver whenever required.
 DataTransfer: FFs can be used to transfer data using shift registers.A shift register is the register which is
able to shift or transfer its content within itself without changing the order of the bits.
 Counter: It is used to count pulses or events and it can be made by connecting a series of FFs.
 Frequency Division: used to divide the frequency of periodic signals.

FYBSC IT Digital Electronics Unit IV Chapter II Sequential Circuits- Flip-Flops

More Related Content

What's hot (20)

Similar to FYBSC IT Digital Electronics Unit IV Chapter II Sequential Circuits- Flip-Flops (20)

More from Arti Parab Academics (20)

Recently uploaded (20)

FYBSC IT Digital Electronics Unit IV Chapter II Sequential Circuits- Flip-Flops