High performance parallel prefix adders with fast carry chain logic

INTERNATIONAL JOURNAL OF ADVANCED RESEARCH IN
International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976
– 6480(Print), ISSN 0976 – 6499(Online)AND TECHNOLOGY (IJARET) IAEME
ENGINEERING Volume 3, Number 2, July-December (2012), ©
ISSN 0976 - 6480 (Print)
ISSN 0976 - 6499 (Online) IJARET
Volume 3, Issue 2, July-December (2012), pp. 01-10
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HIGH PERFORMANCE PARALLEL PREFIX ADDERS WITH
FAST CARRY CHAIN LOGIC
Anitha R1, V Bagyaveereswaran2
AP(Sr), SENSE, AP(Sr), SELECT

VIT University, Vellore – 632014, TamilNadu, India.
1 2
eranitharavi@gmail.com, bagyaveereswaran@gmail.com,

ABSTRACT

Binary adders are the basic and vital element in the circuit designs. Prefix adders are the
most efficient binary adders for ASIC implementation. But these advantages are not
suitable for FPGA implementation because of CLBs and routing constraints on FPGA.
This paper presents different types of parallel prefix adders and compares them with the
Simple Adder. The adders are designed using Verilog HDL code and simulated and
synthesized using Xilinx ISE13.2 software tool and Cadence RTL compiler. Among all
the adders, Kogge-Stone adder provides better performance in ASIC implementation but
it is not suitable for FPGA implementation. In order to make it suitable for FPGA
implementation, Kogge-Stone adder is modified using fast carry logic technique. The
modified adder provides better performance over the Simple adder for the higher order
bit widths.
Keywords- FPGA, Binary addition, Carry tree adders, Prefix computation, Prefix
addition.

I. INTRODUCTION
Adders are the most important element in all the digital circuit design. Among the
various types of adders, Carry Tree Adder which is also known as Parallel Prefix Adders
provide high performance in terms of speed in ASIC implementation. The Carry Tree
adder performs three stage operations such as Pre-computation stage, Prefix-
computation stage and Post-computation stage. The Pre-computation stage generates and
propagates the carry signal, the Prefix computation stage generates the carry signal using
prefix cells and the Post-computation stage generates the sum. This is shown in Fig.1
and the equation for these three stage addition operation is given in equation 1, 2 &3.
Field Programmable Gate Array [10] offers low cost and less development time over
ASIC implementation. In this paper, the most efficient adder i.e., the carry tree adder
like Kogge-Stone, Brent-Kung, Ladner-Fischer and Han-Carlson adders are designed
and implemented on FPGA.

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– 6480(Print), ISSN 0976 – 6499(Online) Volume 3, Number 2, July-December (2012), © IAEME

The problems involved in FPGA implementation are investigated and the possible
FPGA architecture which can make the Carry Tree Adder to provide high performance
over the Simple adder is explored. The possible trade-offs like area, power, delay,
interconnect count and fan-out involved in the adders are examined.

Fig.1. Block Diagram of Prefix addition

The three stages addition consists of the following computations:

• Pre-computation: Gm:n=An and Bn, G0=cin; Pm:n=An xor Bn, P0=0;
……...(1)
• Prefix-computation: (Gm, Pm) ο (Gn, Pn)= (Gn:k + Pn:k· Gk-1:n, Pn:k·Pk-1:j)
(or) Gm:n=Gn:k + Pn:k· Gk-1:nPm:n=Pn:k·Pk-1:j ……...(2)

• Post-computation: Sn=Pn xor Gn-1:0 ……...(3)

II. CARRY TREE ADDERS
The various types of carry tree adders are shown in Fig.2. Each carry tree adder
consists of three parts. They are: Upper part, Middle part, Lower part. Using these parts
the carry tree adders computes N outputs from N inputs as shown in Fig.1. The Upper
part generates and propagates the carry signal from the input to the prefix stage using the
formula given in equation (1). The propagated and generated carry signals are combined
using the associate operator “ο”. This operation is performed in the middle part using the
formula given in equation (2). The Middle part consists of prefix cells such as black
cells, grey cells and white buffers [1]. The arrangement of these prefix cells in different
order results in various types of Carry Tree adders. where the carry signals need not to
be propagated. Such operations are performed by grey cells. The grey cells generate the
carry signal only.Black cell generates and propagates the carry signal. There are some
places The white buffers are used to reduce the loading effect for the further stages. The
Lower part generates the overall sum using the formula given in equation (3).
Depends on the arrangement of prefix cells, the carry tree adders involves in trade-
offs like area, power, delay, interconnect count, fan-out and logic depth [3 & 4]. Fig.2
(a) shows the Brent-Kung The dark black line in the figure indicates the critical path of
the adder. The critical path for Han-Carlson and Kogge-Stone are less. So these two

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– 6480(Print), ISSN 0976 – 6499(Online) Volume 3, Number 2, July-December (2012), © IAEME

adders are expected to be the fastest adder. The power utilized by all the Carry Tree
Adder is more than the Simple Adder.

(a)Brent Kung

(b) Kogge Stone
minimum area and maximum logic depth. Due to the maximum logic depth, the delay of this
adder is expected to be high. Fig.2 (b) shows the Kogge-Stone adder. adder. It is designed in
such a way that it provides It provides maximum interconnect count and area but minimum
logic depth and fan-out. Ladner-Fischer adder as shown in Fig.2 (c) provides minimum logic
depth with improved area. Han-Carlson adder as shown in Fig. 2(d) provides minimum logic
depth and minimum interconnect count.

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International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –
6480(Print), ISSN 0976 – 6499(Online) Volume 3, Number 2, July-December (2012), © IAEME

(c) Ladner Fischer

(d)Han Carlson

Fig.2. (a-f) Carry Tree adders

Simple adder is designed using Verilog HDL ‘+’ operator. The carry chain structure on
FPGA makes Simple Adder to provide high performance. But this is not an efficient adder for
VLSI implementation. In this paper, Carry Tree Adder is compared with Simple Adder for
both ASIC and FPGA implementation.

III. RELATED RESEARCH AND PROPOSED WORK
The different types of carry tree adders are discussed in [4]. In [5], the authors
implemented different types of adders like Simple Adder, Carry Look Ahead Adder, Carry
Skip Adder, and Carry Select Adder on the Virtex2 FPGAs and found that the Simple Adder
provides better performance. In [3], the authors discussed various parallel prefix networks
design and implementation on a Xilinx Virtex5 FPGA. It is observed that the Simple Adder
provides better performance over the prefix networks for the bit widths up to 256 bits. This is
due to the advantage of the carry chain structure on the FPGA. All these works by different
authors shows that the simple adder provides better performance on FPGA. The area, delay
results for these works depend upon synthesis reports. In [2], the authors described several
Carry Tree Adders implemented on a Xilinx Spartan3E FPGA. It is found that the Kogge
Stone Carry Tree Adder provide better delay performance for the higher order bits. The
results obtained for this paper is similar to those presented in [2].

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Carry Tree Adders are designed, coded, simulated and synthesized and then it is
compared with the Simple Adder. The obtained area, power, delay results of various Carry
Tree Adders are compared with each other and also with the Simple Adder. Among all the
Carry Tree Adders, Kogge-Stone Adder and Han-Carlson Adder is expected to be the fastest
adder in ASIC implementation but not in FPGA implementation.

In this paper, Kogge-Stone Adder is taken, since it is having minimum fan-out and logic
depth than Han-Carlson Adder, and modified using Fast Carry Logic technique in order to
make it suitable for FPGA implementation [6, 7, 8 & 9]. The addition operation performed by
Simple Adder, which is generated by synthesis tool, is shown in Fig.3 (a). From Fig.3 (a), it
is clear that the Prefix-computation stage of the Simple Adder uses multiplexers. Similarly,
the Prefix-computation stage of Carry Tree Adder is replaced with the Fast Carry logic
technique which uses muxes as shown in Fig.3 (b). The Fast Carry Logic architecture for 4-
bit addition is shown in Fig.3(c). Instead of using Black cells, Grey cells and White buffers to
propagate and generate the carry signals, simple muxes are used. The blocks present in Fast
Carry Logic technique also uses muxes. The input to the Fast Carry Logic is the propagated
and generated carry signal of the Pre-computation stage. The Pre-computation and Post-
computation of the modified adder is similar to that of the normal carry tree adders.

IV. RESULTS

The delay, power and cell area results obtained by synthesizing the designed adders
for 128bits using Cadence RTL compiler (90nm technology) is shown in Table 1, 2 & 3. The
abbreviations used in the table are: KS for the Kogge Stone Adder, BK for the Brent Kung
Adder, LF for the Ladner Fischer Adder and HC for Han Carlson Adder.

Fig.3(a)SimpleAdder

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Fig.3(b)Carry Tree Adder

Fig.3(c) Fast Carry Logic for 4-bit Carry tree addition

The delay is measured in terms of nanoseconds, power in terms of nanowatt. From the
results it is found that the Carry Tree Adders provide best delay performance than the
Simple adder. Among the Carry Tree Adders, Kogge-Stone Adder and Han-Carlson
Adder provide best delay as it is expected but the area and power utilized by those
adders are more. Comparatively, Brent-Kung Adder and Ladner-Fischer Adder
utilizes less area and power.

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Table 1: Delay Results of Carry Tree Adders compared with Simple Adder

Table2: Power Results of Carry Tree Adders compared with Simple Adder

Table3: Cell Area Results of Carry Tree Adders compared with Simple Adder

Fig.4 shows the simulated delay results of the adders for the bit widths up to 128bits
using Xilinx ISE13.2 software tool. From the Fig.4, it is found that the Simple Adder provide
best delay performance over the Carry Tree Adder. The obtained delay result is entirely
different from the result shown in Table 1. This is because of the presence of Fast Carry chain
structure on Xilinx FPGA. Among the Carry Tree adders, Kogge-Stone Adder provides best
delay as it is expected.

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Fig.5(a-d) shows the delay results of Kogge-Stone Adder, Kogge-Stone Modified Adder and
Simple Adder for the FPGA families like Spartan-3E, Virtex-4, Virtex-5 and Virtex-6 Lower
power. Some of the 64-bit adder structure cannot be fitted in to all the devices under this
family.

Fig. 4 Simulated Delay Results of Carry Tree Adders compared with Simple Adder

Depends on the adder structure, the device and package has been selected. From the
Fig it is found that, for Spartan-3E FPGA, Kogge-Stone adder provide best
performance after it reaches 256 bits whereas Modified adder provides best
performance after it reaches 128bits, for Virtex-4 FPGA, Kogge-Stone adder provides
best performance after itreaches 128bits whereas Modified adder provides best
performance from 128bits, for Virtex-5 FPGA, Kogge-Stone adder provides best
performance after it reaches 256bits whereas Modified adder provides best
performance from 128bits, for Virtex-6 FPGA, it is able to reduce the delay of Carry
Tree Adder but Simple Adder provide better delay performance.

(fig. 5.a)
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V. CONCLUSION

This paper presents different types of Carry Tree Adders. Kogge Stone adder is
the fastest carry tree adder in VLSI implementation but it provides different result for
the FPGA implementation.

(Fig.5.b)

In order to make it suitable for FPGA implementation, the prefix computation stage is
modified using “Fast Carry Logic”.

(Fig.5.c)

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(Fig.5.d)

Fig. 5(a-d) Simulated Delay results

The obtained delay results are compared with the Simple Adder for the various FPGA devices
like Spartan3E, Virtex4, Virtex5, Lower power Virtex6. The Lower power Virtex6 FPGA
provides best delay compared to that of all the FPGA devices. By using carry logic technique
the Carry Tree Adders are able to provide better delay performance on FPGA over the Simple
Adder for the higher order bit widths.

REFERENCES

1. N. H. E. Weste and D. Harris, CMOS VLSI Design, 4th edition, Pearson–Addison-
Wesley, 2011.
2. FPGAs David H. K. Hoe, Chris Martinez and Sri Jyothsna Vundavalli, “Design and
Characterization of Parallel Prefix Adders”, IEEE 43rd Southeastern Symposium
on system theory, March 2011.
3. K. Vitoroulis and A. J. Al-Khalili, “Performance of Parallel Prefix Adders Implemented
with FPGA technology,” IEEE Northeast Workshop on Circuits and Systems, pp. 498-
501, Aug. 2007.
4. D. Harris, “A Taxonomy of Parallel Prefix Networks,” in Proc. 37th Asilomar Conf.
Signals Systems and Computers, pp. 2213–7, 2003.
5. M. Becvar and P. Stukjunger, “Fixed-Point Arithmetic in FPGA,” Acta Polytechnica,
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http://www.xilinx.com/support/documentation/user_guides/ug331.pdf
7. Virtex-4 FPGA User Guide, Xilinx Inc., Dec 2008, UG070
(V2.6):http://www.xilinx.com/support/documentation/user_guides/ug070.pdf.
8. Virtex-5 FPGA User Guide, Xilinx Inc., May 2010, UG190 (V5.3):
http://www.xilinx.com/support/documentation/userguides/ug190.pdf.
9. Virtex-6 FPGA User Guide, Xilinx Inc., Sep. 2009, UG364 (v1.1):
http://www.xilinx.com/support/documentation/user guides/ug364.pdf.
10. www.xilinx.com
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