Implementation of switching controller for the internet router

INTERNATIONAL JOURNAL OF ELECTRONICS AND
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN
0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME
COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)
ISSN 0976 – 6464(Print)
ISSN 0976 – 6472(Online)
Volume 4, Issue 2, March – April, 2013, pp. 229-238
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IMPLEMENTATION OF SWITCHING CONTROLLER FOR THE
INTERNET ROUTER

J. Paul Richardson Gnanaraj1, G. Ramesh2, G. Thanigaivel3, M. Velvizhi4
1, 2, 3, 4
(ECE, Anna University, Chennai, India)

ABSTRACT

The greedy scheduling (GS) algorithm is a scalable maximal matching algorithm.
This algorithm was conceptually proposed and well received since it provides non-blocking
in an Internet router with input buffers and a cross-bar, unlike other existing implementations.
In this paper, I implent a new design of the GS algorithm, and determine its exact behaviour,
performance and QoS that it provides. I design and measure the performance of their
implementations in terms of their scalability and speed. It will be shown that multiple
scheduler modules of a terabit Internet router can be implemented on a low-cost field-
programmable gate-array (FPGA) device, and that the processing can be performed within
the desired time slot duration. The scheduler modules designed on one low-cost Altera FPGA
may control router with hundreds of ports. The output selection time remains below 60 ns in
high-capacity Internet routers.

Keywords: Field-programmable gate-array (FPGA) implementation, high-capacity, non-
blocking, packet switching.

I. INTRODUCTION

The fast growth of bandwidth demand on the Internet has led to a need for high-
capacity packet routers, with large number of ports and high port speeds. Routers with input
buffers are the most scalable single-stage routers. In this architecture, packets are split into
cells of fixed length and stored at the input ports. Based on the information about the
outstanding packets, the scheduler determines the cross-bar configuration in each time slot,
i.e., the input-output pairs that should be connected. When the number of ports increases, the
allocation of outputs to inputs in these routers becomes computationally intensive [1]–[4].
The router with input buffers is non-blocking if appropriate scheduling algorithms are
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implemented. But, the algorithm must not limit the router scalability either. It has been
recognized that maximal matching algorithms provide non-blocking while requiring
significantly lower computing complexity compared to maximum matching algorithms
[1], [5]-[8]. The maximal matching between inputs and outputs do not leave input-output
pairs unmatched if there is traffic between them [3],[5],[9]. The sequential greedy
scheduling (GS) algorithm [1], [5] is a maximal matching algorithm that provides non-
blocking through a cross-bar with the speedup of two, when the traffic is policed, and
consequently provides delay guarantees to the sensitive applications, as well as flexible
admission control.
The GS algorithm can be implemented using pipeline technique[13], and involves
a scheduler with a simple structure. For a router with N ports, the scheduler has N
modules and each of the modules communicates only with adjacent scheduler modules.
The GS algorithm is performed in N steps. In each step, one of the inputs chooses the first
output for which it has packets to send, and which was not assigned in previous steps.
Then, this input updates the set of available outputs and forwards it to the next input in
the chain. Using pipeline technique, the schedule is calculated during multiple time slots.
In each time slot, the scheduler calculates in parallel schedules for N future time slots.
Thus, each input port is given significantly longer time to perform the output selection.
The scheduler should perform an output selection so that the overall pipeline delay is a
negligible part of the packet delay. The packet delay (including queuing delay) depends
on the cell duration and the granularity of bandwidth reservations. It is equal to the
policing interval (frame) in unicast routers with input buffers controlled by the GS [1],
[5]. Scalability of the scheduling algorithm may be estimated, but it can be ascertained
only when the algorithm is actually implemented. Field programmable gate arrays
(FPGAs) are convenient for the implementation of the GS algorithm. They are cost-
effective, and relatively easy to program. Testing of the FPGA design is significantly
simplified compared to the application-specific integrated circuit (ASIC) design, which
speeds up the FPGA design and reduces its cost. Performance of the implementation
(its speed and scalability) depends on software tools used for synthesis, and placement
and routing on the FPGA device [10]–[12]. Since in the pipelined SGS algorithm, the cell
duration, Tc, should be greater than the output selection time, Ts, and the delay is
proportional to the cell duration, the output selection time should be as low as possible in
order to provide low packet delays. Other implementations of the schedulers for the high-
capacity packet routers have been previously suggested [2], [3]. These
implementations, however, are neither scalable since the complexity of the design
increases with the square of the number of ports, nor non-blocking for all types of traffic.
In this paper, I propose a new design of a scalable non-blocking scheduler for
the high-capacity packet routers. Particular scheduler components are first described.
Next, we present the optimizations of the scheduler sub-components, and prove their
correct functioning. Then, I propose two design options for the GS scheduler, and
examine the performance of their implementation in terms of the speed and scalability.
The number of scheduler modules that can fit one FPGA device and the output selection
time Ts are calculated for various router sizes. The implemented design is thoroughly
tested using both software and hardware checks.

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II. DESIGN OF THE SCHEDULER

Fig. 1. Internal architecture of an input port i.

The internal architecture of the input port is given in Fig. 1. The input port consists of
several components: network processor, data memory, linked list memory, queue manager, and
output selector. When a packet arrives to the router, its destination IP address is read by network
processor (NP) and the router output to which the packet should be sent is determined. The NP
also divides packets into smaller fixed length cells and stores them in the appropriate virtual
output queue (VOQ). In each input buffer, there are N VOQs that comprise cells bound for
particular outputs. Data memory stores the incoming packets/cells until they are scheduled and
sent through the switching fabric. Linked list memory stores the data memory addresses of cells
in VOQs. Queue manager performs operations on virtual queues. Output selector calculates the
schedule for the outstanding cells and stores it in output memory until the cells are read. A simple
structure of the central controller that executes the GS algorithm is shown in Fig. 2.

Fig. 2. Central controller for the GS protocol.

Each input module communicates only with adjacent input modules, and the complex
interconnection between input and output modules is avoided. Addresses of the reserved outputs
are stored into the memory. The price that GS pays for its simplicity is the additional pipeline
delay, which can be as large as time slots. This pipeline delay is not critical for assumed very
short packet transmission time. I have implemented scheduler modules comprising queue
manager, Linked list memory and output selector on Altera Cyclone II FPGA. These components
will be presented in more details in the following subsections. Multiple scheduler modules can be
placed on a single FPGA device.
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A. Linked List Memory
Cells in data memory that are bound for the same destination form a VOQ. There are N
VOQs, corresponding to N outputs. Linked list memory stores addresses of cells in different
VOQs and addresses of empty locations. Each location in one virtual queue linked list (VQL)
contains the address of the next location in that VQL, or zero (NULL) if no more locations
belong to the VQL. Similarly, each location in the empty queue linked list (EQL) contains the
address of the next location in EQL. The size of the linked list memory is defined by the number
of cells that ought to be stored in the data memory of the router. The data memory should be
able to store the number of cells equal to the frame length F. Thus, the linked list memory has F
locations. We designed the linked list memory so that it uses M4K memory blocks of the Altera
Cyclone II FPGA.

B. Queue Manager
Queue manager performs operations when a cell arrives to the queue manager, when it is
scheduled by the output selector, or when it departs the router. The queue manager stores pointers
to VQLs. There are three pointers to each VQL: to the beginning of the VQL, the first un-
scheduled packet in the VQL, and the end of the VQL. Similarly, the EQL is managed with two
pointers: to the beginning and the end of the EQL. The pointers are updated each time one of the
operations is performed. Multiple operations are carried out in the same time slot, and in general
on different VQLs. At the beginning, all memory locations belong to EQL, and each location
contains the address of the next location in the memory (except the last that points to NULL). The
memory location is removed from the beginning of the EQL to the end of the VQL of some
output, when a cell bound for that output arrives to the router. The cell is stored to the address
from this memory location. When input sends a cell to some output, the cell address in the data
memory is read from the heading location of the corresponding VQL, and this memory location is
added to the end of EQL. When a cell is scheduled, the corresponding VQL is updated. If the
pointer to the first unscheduled cell from the same VQL points to the last cell in that VQL, the
pointer is set to NULL. Else, the pointer to the first unscheduled cell is set to point to the next
element in that VQL. The queue manager was designed in VHDL, and it can be scaled easily for
different router sizes.

C. Output Selector

Fig. 3. Output selector structure. (a) 2x2 output selector. (b) 2k+1 x 2k+1 output selector.

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The output selector of the associated input schedules a cell by choosing the first
available output from the set of outputs for which the given input has cells to send. The result
of the scheduling process is a vector in which only one bit, which corresponds to the
scheduled queue, is set to logical one. The structure of the optimized output selector is shown
in Fig. 3, [13]. Bits denoted by R contain information about cells of a particular input, which
participate in the contention process. Bit Rj is set to “1” only if there are unscheduled cells for
the jth output port, and the jth output port was not selected by previous input ports. As a
result of the scheduling process, Qj is set to “1” when the jth output port is chosen by the
given input.
The information about the remaining output ports is forwarded to the next input port
in the chain. The output selector is implemented recursively. The two-port output selector is
shown in Fig. 2(a). The output selector for a router with 2k+1 output ports can be built
recursively by using two output selectors for 2k ports and one two-port output selector, as
shown in Fig. 2(b).
Theorem 1: For the 2k x 2k output selector the following equations hold:

(1)

(2)
that is, the output selector chooses the first available output for which an associated input
control module has cells to send.
Proof: The Theorem 1 was proven in [13].
The Q vector is forwarded to the optimized coder shown in Fig. 4, which determines
the position of a logical one in that vector and thus the output that has been scheduled for the
observed time slot. The coder allows the output selector to propagate the information about
the scheduled queue with less bits.
The output selector and the coder are connected in the following manner: the jth
output of the output selector drives the jth input of the coder. When Qj = “1”, then Aj = “ 1”,
and the coder returns j coded binary. The coder is also implemented recursively, as shown in
Fig. 4.

Fig.4. Coder structure. (a) 4-to-3 coder. (b) 2k+1 -to- (k + 2) coder.

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Theorem 2: For the 2k-to-(k + 1) coder, when Ax =”1”(1 ≤ X ≤ 2k), the outputs of the coder Xi(0
≤ I ≤ k) comprise the binary representation of x and when all the inputs are equal to zero, the
coder’s output is zero, as well.

(3)

Proof: We have proven the Theorem 2 in [13].
The number of the scheduled output is sent to the queue manager, and also stored in the output
memory until the time the cell should be read, according to the pipeline technique. The output
selector for the input i in time slot k calculates the schedule and reserves the output for the time
slot
(4)

Therefore, the numbers of the scheduled VOQs need to be stored in the output memory until
the time slot when they need to be read by the queue manager. The output memory was designed
to use M4K memory blocks functioning as an embedded shift register. The additional delay of
three time slots needs to be introduced (since the minimum tap distance of the embedded shift
register is three). The delay incurred in this way is still a negligible part of the total packet delay.

III. PERFORMANCE ANALYSIS

I have implemented the scheduler that runs the GS algorithm. In this section, i will
discuss their performance and measure it in terms of the design scalability, i.e., the number of
scheduler modules that can fit one FPGA device. I will also examine the speed of the design, i.e.,
the minimum achievable output selection time Ts. The Altera Cyclone II EP2C35F672C6 device
[15] that we used for the implementation consists of 33216 logic elements (LEs) grouped into
logic array blocks (LABs), 100 M4K memory blocks containing 4608 memory bits each, and 475
user IOs on the periphery.
We have shown in [13] that the maximum number of scheduler modules, which can fit a
single FPGA device, does not change if the optimized structures are used in place of the simpler
VHDL design. However, it was proven that the minimum output selection time does significantly
decrease when the optimized structures are implemented. The gain of the optimization was shown
to increase with router size. The state machine for the queue manager operation comprises four
states: swait, write, schedule, and read, and the state transitions are unconditional, i.e., in each
clock cycle the state machine switches to the next state. The swait state is needed to ensure the
correct functioning of the controller, since the synchronous operations of the M4K memory
require one additional cycle between an address setup cycle, and a cycle in which the data is read.
The pointers to VQLs are implemented using LEs of the Altera Cyclone II. The number of
used pins can be calculated as in [13],

. Pins(N.Np.F)=(2[log2 F]+log2 N+1).Np+2N+3 (5)

The number of M4K blocks required for the linked list memory and the output memory can be
calculated as in [13],

mem(N.Np.F) = (F[log2 F]/4096]+4).N (6)

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TABLE I RESOURCE UTILIZATION AND TIMING CHARACTERISTICS F = 8N
M4K FMAX TS
N NP LE pins lim
[Kbits] [MHz] [ns]
16 16 17331 32 339 / 121.1 33
32 17 32096 34 441 LE 84.1 47.4
64 8 29507 16 331 LE 82.6 48.4
128 3 24599 12 215 LE 68.4 58.4

pins(N,Np,F) ≤ 475
mem(N,Np,F) ≤ 100 (7)

It can be observed from Tables I that the maximum clock frequency of the design
somewhat decreases with the increase of the number of ports because it causes the increase of
the number of required LEs.

IV. SIMULATION AND TESTING

Design was tested in software, in order to prove their correct functioning. First, the
built-in Quartus II and Model sim XE II 5.8c simulation tool was used, and the designs were
tested for different sets of input stimuli. Simulation of Scheduler (packet size = 128bits,
frame size = 8bits and cell size = 1bit) shown in figure (a),(b)and (c), and multiple scheduler
module (input module i = 4) for packet size = 16 bits, frame size = 4bits and cell size = 1bit
shown in (d) and (e). The designs were downloaded into the Cyclone II chip on the Altera
DE2 development board. Then, the hardware testing was performed. In all the cases, the
correct functioning of the switching controller was confirmed.

Fig. a Simulation of Single Scheduler for packet size of 128 bits

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Fig. b Simulation of Single Scheduler for packet size of 128 bits

Fig. c Simulation of Single Scheduler for packet size of 128 bits

Fig. d Simulation of Multiple Scheduler for packet size of 16 bits

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Fig. e Simulation of Multiple Scheduler for packet size of 16 bits

V. CONCLUSION

In this paper, I proposed the design of the scheduler for the Internet router based on
the GS algorithm, and presented its implementation. I optimized the scheduler
subcomponents, so as to provide lower packet delays, decreasing the complexity and proved
their correct functioning. The preferred design option is highly scalable: up to 14 scheduler
modules of an 128x128 router can be placed on a single low-cost FPGA device. The
scheduler modules designed on one low-cost Altera FPGA may control router with hundreds
of ports, i.e., with terabit capacity.. The output selection time remains below 60 ns in
discussed high-capacity Internet routers. The proper functioning of the scheduler was
confirmed through thorough software and hardware testing. The implemented scheduler can
be used in high-capacity routers that provide delay guarantees for sensitive applications, and
the fine granularity of reservations.

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Implementation of switching controller for the internet router

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