Input Output

382 CHAPTER 10 MEMORY INTERFACE

49. When DRAM is refreshed, can it be done while other sections of the memory operate?
CHAPTER 11
50. If a 1M x 1 DRAM requires 4 ms for a refresh and has 256 rows to be refreshed, no more
than ____ of time must pass before another row is refreshed.
51. Where is the memory address applied to the 82C08 DRAM controller?
Basic I/O Interface
52. What is the purpose of the BS pin on the 82C08?
53. What is normally connected to the WR pin of the 82C08?

INTRODUCTION

A microprocessor is great at solving problems, but if it can't communicate with the outside
world, it is of little worth. This chapter outlines some of the basic methods of communications,
both serial and parallel, between humans or machines and the microprocessor.
In this chapter, we first introduce the basic I/O interface and discuss decoding for I/O de-
vices. Then, we provide detail on parallel and serial interfacing, both of which have a variety of
applications. As applications, we connect analog-to-digital and digital-to-analog converters, as
well as both DC and stepper motors to the microprocessor.

CHAPTER OBJECTIVES

Upon completion of this chapter, you will be able to:
1. Explain the operation of the basic input and output interfaces.
2. Decode an 8-, 16, and 32-bit I/O device so that they can be used at any I/O port address.
3. Define handshaking and explain how to use it with I/O devices.
4. Interface and program the 82C55 programmable parallel interface.
5. Interface LCD displays, LED displays, keyboards, ADC, DAC, and various other devices
tothe82C55.
6. Interface and program the 8279 programmable keyboard/display controller.
7. Interface and program the 16550 serial communications interface adapter.
8. Interface and program the 8254 programmable interval timer.
9. Interface an analog-to-digital converter and a digital-to-analog converter to the microprocessor.
10. Interface both DC and stepper motors to the microprocessor.

INTRODUCTION TO I/O INTERFACE

In this section of the text, we explain the operation of the I/O instructions (IN, INS, OUT, and
OUTS). We also explain the concept of isolated (sometimes called direct or I/O mapped I/O) and
memory-mapped I/O, the basic input and output interfaces, and handshaking. A working knowledge

383

384 CHAPTER 11 BASIC I/O INTERFACE 11-1 INTRODUCTION TO I/O INTERFACE 385
of these topics will make it easier to understand the connection and operation of the programmable The address connections above A15 are undefined for an I/O instruction. The 16-bit variable
interface components and I/O techniques presented in the remainder of this chapter and text. port number (DX) appears on address connection A15-AO. This means that the first 256 I/O
port addresses (OOH-FFH) are accessed by both the fixed and variable I/O instructions, but any
I/O Instructions I/O address from 0100H-FFFFH is only accessed by the variable I/O address. In many dedi-
The instruction set contains one type of instruction that transfers information to an I/O device cated task systems, only the rightmost eight bits of the address are decoded, thus reducing the
(OUT) and another to read information from an I/O device (IN). Instructions (INS and OUTS, amount of circuitry required for decoding. In a PC computer, all 16 address bus bits are de-
found on all versions except the 8086/8088) are also provided to transfer strings of data between coded with locations OOOOH-03XXH, which are the I/O addresses used for I/O inside the PC
the memory and an I/O device. Table 11-1 lists all versions of each instruction found in the mi- for the ISA (industry standard architecture) bus.
croprocessor's instruction set. The INS and OUTS instructions address an I/O device by using the DX register, but do not
Both the IN and OUT instructions transfer data between an I/O device and the micro- transfer data between the accumulator and the I/O device as IN and OUT. Instead, these instruc-
processor's accumulator (AL, AX, or EAX). The I/O address is stored in register DX as a 16-bit tions transfer data between memory and the I/O device. The memory address is located by ES:DI
I/O address or in the byte (p8) immediately following the opcode as an 8-bit I/O address. Intel for the INS instruction and by DS:SI for the OUTS instruction. As with other string instructions,
calls the 8-bit form (p8) a fixed address because it is stored with the instruction, usually in a the contents of the pointers are incremented or decremented, as dictated by the state of the direc-
ROM. The 16-bit I/O address in DX is called a variable address because it is stored in a DX, tion flag (DF). Both INS and OUTS can be prefixed with the REP prefix, allowing more than one
and then used to address the I/O device. Other instructions that use DX to address I/O are the INS byte, word, or doubleword to be transferred between I/O and memory.
and OUTS instructions.
Whenever data are transferred by using the IN or OUT instruction, the I/O address, often Isolated And Memory-Mapped I/O
called a port number (or simply port), appears on the address bus. The external I/O interface de-
codes the port number in the same manner that it decodes a memory address. The 8-bit fixed port There are two different methods of interfacing I/O to the microprocessor: isolated I/O and
number (p8) appears on address bus connections A7-AO with bits A15-A8 equal to 000000002. memory-mapped I/O. In the isolated I/O scheme, the IN, INS, OUT, and OUTS instructions
transfer data between the microprocessor's accumulator or memory and the I/O device. In the
memory-mapped I/O scheme, any instruction that references memory can accomplish the
TABLE 11-1 Input/output instructions. transfer. Both isolated and memory-mapped I/O are in use, so both are discussed in this text.
Isolated I/O. The most common I/O transfer technique used in the Intel microprocessor-based
Instruction Data Width Function
system is isolated I/O. The term isolated describes how the I/O locations are isolated from the
IN AL, p8 8 A byte is input from port p8 into AL memory system in a separate I/O address space. (Figure 11-1 illustrates both the isolated and
IN AX, p8 16 A word is input from port p8 into AX memory-mapped address spaces for any Intel 80X86 or Pentium-Pentium II microprocessor.)
The addresses for isolated I/O devices, called ports, are separate from the memory. Because the
IN EAX, p8 32 A doubleword is input from port p8 into EAX
ports are separate, the user can expand the memory to its full size without using any of memory
IN AL,DX 8 A byte is input from the port addressed by DX into AL space for I/O devices. A disadvantage of isolated I/O is that the data transferred between I/O and
IN AX,DX 16 A word is input from the port addressed by DX into AX the microprocessor must be accessed by the IN, INS, OUT, and OUTS instructions. Separate
IN EAX.DX 32 A word is input from the port addressed by DX into EAX control signals for the I/O space are developed (using M/IO and W/R), which indicate an I/O
INSB 8 A byte is input from the port addressed by DX into the extra segment read (IORC) or an I/O write (IOWC) operation. These signals indicate that an I/O port address,
memory location addressed by Dl, then Dl = Dl ± 1 which appears on the address bus, is used to select the I/O device. In the personal computer, iso-
I NSW 16 A word is input from the port addressed by DX into the extra segment lated I/O ports are used for controlling peripheral devices. An 8-bit port address is used to access
memory location addressed by Dl, then Dl = Dl ± 2 devices located on the system board, such as the timer and keyboard interface, while a 16-bit port
INSD 32 A doubleword is input from the port addressed by DX into the extra segment is used to access serial and parallel ports as well as video and disk drive systems.
memory location addressed by Dl, then Dl ± 4
Memory-Mapped I/O. Unlike isolated I/O, memory-mapped I/O does not use the IN, INS,
OUT p8,AL 8 A byte is output from AL to port p8 OUT, or OUTS instructions. Instead, it uses any instruction that transfers data between the mi-
OUT p8,AX 16 A word is output from AX to port p8 croprocessor and memory. A memory-mapped I/O device is treated as a memory location in the
OUT p8,EAX 32 A doubleword is output from EAX to port p8 memory map. The main advantage of memory-mapped I/O is that any memory transfer instruc-
OUT DX,AL 8 A byte is output from AL to the port addressed by DX tion can be used to access the I/O device. The main disadvantage is that a portion of the memory
OUT DX,AX 16 A word is output from AX to the port addressed by DX system is used as the I/O map. This reduces the amount of memory available to applications. An-
OUT DX,EAX 32 A doubleword is output from EAX to the port addressed by DX other advantage is that the IORC and IOWC signals have no function in a memory-mapped I/O
system and may reduce the amount of circuitry required for decoding.
OUTSB 8 A byte is output from the data segment memory location addressed by SI to
the port addressed by DX, then SI = SI ± 1
OUTSW 16 A word is output from the data segment memory locations addressed by SI to
Personal Computer I/O Map
the port addressed by DX, then SI = SI ± 2 The personal computer uses part of the I/O map for dedicated functions. Figure 11-2 shows the
OUTSD 32 A doubleword is output from the data segment memory locations addressed I/O map for the PC. Note that I/O space between ports OOOOH and 03FFH are normally reserved
by SI to the port addressed by DX, then SI = SI ± 4 for the computer system and the ISA bus. The I/O ports located at 0400H-FFFFH are generally
available for user applications, main-board functions, and the PCI bus. Note that the 80287 arith-

11-1 INTRODUCTION TO I/O INTERFACE 387
386 CHAPTER 11 BASIC I/O INTERFACE

FIGURE 11-2 The I/O map FFFF
FIGURE 11-1 The memory Memory of a personal computer illus-
FFFFF
and I/O maps for the 8086/ I trating many of the fixed I/O I/O Expansion area
8088 microprocessors, areas.
(a) Isolated I/O (b) Memory-
mapped I/O.
I/O
IM x 8 FFFF

64K x 0400
03FF
03F8 COM 1
0357
03FO Floppy disk
0000 03EF
00000 03EO
(a) 03DF
03DO CGA adapter
03CF
0380
Memory + I/O 037F
FFFFF 0378 LPT1
0377
0330
032F
0320 Hard disk
031 F
0300
I/O 02FF
02 F8 COM2
02 F7
0064
0063
0060
8255 (PPI)
005F
0044
0043
0040 Timer
003F
0024
00000 0023
(b) 0020 Interrupt controller
001 F
0010
OOOF
metic coprocessor uses I/O address OOF8H-OOFFH for communications. For this reason, Intel re- 0000 DMA controller
serves I/O ports OOFOH-OOFFH. The 80386-Pentium II use I/O ports 800000F8-800000FFH for
communications to their coprocessors. The I/O ports located between OOOOH and OOFFH are ac-
cessed via the fixed port I/O instructions; the ports located above OOFFH are accessed via the When the microprocessor executes an IN instruction, the I/O port address is decoded
variable I/O port instructions. to generate the logic 0 on SEL. A 0 placed on the output control inputs (1G and 2G) of the
74ALS244 buffer causes the data input connections (A) to be connected to the data output (Y) con-
Basic Input and Output Interfaces nections. If a logic 1 is placed on the output control inputs of the 74ALS244 buffer, the device enters
The basic input device is a set of three-state buffers. The basic output device is a set of data the three-state high-impedance mode that effectively disconnects the switches from the data bus.
latches. The term IN refers to moving data from the I/O device into the microprocessor and the This basic input circuit is not optional and must appear any time that input data are inter-
term OUT refers to moving data out of the microprocessor to the I/O device. faced to the microprocessor. Sometimes it appears as a discrete part of the circuit, as shown in
.| Figure 11-3; sometimes it is built into a programmable I/O device.
The Basic Input Interface. Three-state buffers are used to construct the 8-bit input port 16- or 32-bit data can also be interfaced to various versions of the microprocessor, but this
in Figure 11-3. The external TTL data (simple toggle switches in this example) are is not nearly as common as using 8-bit data. To interface 16 bits of data, the circuit in Figure
the inputs of the buffers. The outputs of the buffers connect to the data bus. The exact data 11-3 is doubled to include two 74ALS244 buffers that connect 16 bits of input data to the 16-bit
connections depend on the version of the microprocessor. For example, the 8088 has data data bus. To interface 32 bits of data, the circuit is expanded by a factor of 4.
connections D7-DO, the 80486 has D31-DO, and the Pentium-Pentium II have D63-DO.
cuit of Figure 11-3 allows the microprocessor to read the contents of the 8 switches that The Basic Output Interface. The basic output interface receives data from the microprocessor
to any 8-bit section of the data bus when the select signal SEL becomes a logic 0. Thus, and must usually hold it for some external device. Its latches or flip-flops, like the buffers found
the IN instruction executes, the contents of the switches are copied into the AL register. in the input device, are often built into the I/O device.

388 CHAPTER 11 BASIC I/O INTERFACE 11-1 INTRODUCTION TO I/O INTERFACE 389

FIGURE 11-3 The basic vc)C are only present on the data bus for less than 1.0 }is. Without a latch, the viewer would never see
input interface illustrating the c) the LEDs illuminate.
connection of eight switches. When the OUT instruction executes, the data from AL, AX, or EAX are transferred to the
Note that the 74ALS244 is a 1111111 latch via the data bus. Here, the D inputs of a 74ALS374 octal latch are connected to the data bus
three-state that controls the 6£ 4 3 2 1 0 9 to capture the output data, and the Q outputs of the latch are attached to the LEDs. When a Q
application of the switch data output becomes a logic 0, the LED lights. Each time that the OUT instruction executes, the SEL
to the data bus. >>>>>>>> 10K
signal to the latch activates, capturing the data output to the latch from any 8-bit section of the
data bus. The data are held until the next OUT instruction executes. Thus, whenever the output
1 J> 3 4 5 6 7 8
U1 instruction is executed in this circuit, the data from the AL register appear on the LEDs.
1 2 1Y1 18

|
2

4
i! ———— 4
6
———— 8
1A1
1A2
1A3
1A4
1Y2
1Y3
1Y4
Handshaking
' 6
2A1 2Y1 Many I/O devices accept or release information at a much slower rate than the microprocessor.
2A2 2Y2
7 10 ————ft 2A3 2Y3 5 Another method of I/O control, called handshaking or polling, synchronizes the I/O device with
8 9 17
2A4 2Y4 the microprocessor. An example device that requires handshaking is a parallel printer that prints
1G 100 characters per second (CPS). It is obvious that the microprocessor can send more than 100
2G CPS to the printer, so a way to slow the microprocessor down to match speeds with the printer
74ALS244
must be developed.
Figure 11-5 illustrates the typical input and output connections found on a printer. Here,
data are transferred through a series of data connections (D7-DO), BUSY indicates that the
SEL
printer is busy and STB is a clock pulse used to send data into the printer for printing.
The ASCII data to be printed by the printer are placed on D7-DO, and a pulse is then ap-
plied to the STB connection. The strobe signal sends or clocks the data into the printer so that it
Figure 11-4 shows how eight simple light-emitting diodes (LEDs) connect to the micro- can be printed. As soon as the printer receives the data, it places a logic 1 on the BUSY pin, in-
processor through a set of eight data latches. The latch stores the number output by the micro- dicating that the printer is busy printing data. The microprocessor software polls or tests the
processor from the data bus so that the LEDs can be lit with any 8-bit binary number. Latches are BUSY pin to decide whether the printer is busy. If the printer is busy, the microprocessor waits;
needed to hold the data because when the microprocessor executes an OUT instruction, the data if it is not busy, the microprocessor sends the next ASCII character to the printer. This process of
interrogating the printer is called handshaking or polling. Example 11-1 illustrates a simple
procedure that tests the printer BUSY flag and then sends data to the printer if it is not busy. The
FIGURE 11-4 The basic vcc PRINT procedure prints the ASCII-coded contents of BL only if the BUSY flag is a logic 0, in-
o
output interface connected to dicating that the printer is not busy. This procedure is called each time a character is to be
a set of LED displays. printed.

EXAMPLE 11-1
;A procedure that prints the ASCII contents of BL.

0000 PRINT PROC NEAR
. "* ^ ^ ^ ^ •^
•^ ^ "* "•* ^ ^ 0000 E4 4B IN AL,BUSY get BUSY flag
U1 0002 A8 04 TEST AL,BUSY_BIT test BUSY bit
3 DO
4 D1
7 D2
QO
Q1-1—
Q2 6
0004 75 FA
0006 8A C3
JNE
MOV
PRINT
AL,BL
if printer busy
get data from BL
8 D3 Q3 9 0008 E6 4A OUT PRINTER,AL send data to printer
13 D4 Q4 12 OOOA CB RET return from procedure
14 D5 Q5 15
17 16
18 D7 Q7 19 OOOB PRINT ENDP

-rio OC
Notes About Interfacing Circuitry
A certain part of interfacing requires some knowledge about electronics. This portion of the in-
troduction to interfacing examines some facts about electronic interfacing. Before a circuit or de-
vice can be interfaced to the microprocessor, the terminal characteristics of the microprocessor
and its associated interfacing components must be known, (This was introduced at the start of
SEL Chapter 10.)

11-1 INTRODUCTION TO I/O INTERFACE 391
CHAPTER 11 BASIC I/O INTERFACE
390
FIGURE 11-6 A single-
pole, single-throw switch in-
terfaced as a TTL device.

bounces, one of the two circuits depicted in Figure 11-7 can be constructed. The first circuit (a)
is a classical textbook bounce eliminator; the second (b) is a more practical version of the same
.32_
!2_ circuit. Because the first version costs more money to construct, in practice, the second would be
J4_ used because it requires no pull-up resistors and only two inverters instead of two NAND gates.
You may notice that both circuits in Figure 11-7 are asynchronous flip-flops. The circuit
Ji-o
of (b) functions in the following manner: Suppose that the switch is currently at position Q . If it
Connector CENT36 is moved toward Q but does not yet touch Q, the Q output of the circuit is a logic 0. The logic 0
state is remembered by the inverters. The output of inverter B connects to the input of inverter A.
Because the output of inverter B is a logic 0, the output of inverter A is a logic 1. The logic 1
output of inverter A maintains the logic 0 output of inverter B. The flip-flop remains in this state
until the moving switch-contact first touches the Q connection. As soon as the Q input from the
Connector DB25 switch becomes a logic 0, it changes the state of the flip-flop. If the contact bounces back away
from the Q input, the flip-flop remembers and no change occurs, thus eliminating any bounce.
DB25 CENT36
DB25 CENT36 Pin number Pin number Function Output Devices. Output devices are far more diverse than input devices, but many are interfaced in
Pin number Pin number Function
12 Paper empty a uniform manner. Before any output device can be interfaced, we must understand what the volt-
Data Strobe 12
1 1 ages and currents are from the microprocessor or a TTL interface component. The voltages are TTL-
13 13 Select
2 2 Data 0 (DO) compatible from the microprocessor of the interfacing element. (Logic 0 = 0.0 V to 0.4 V; logic 1 =
14 14 Afd
3 Data 1 (Dl) 2.4 V to 5.0 V.) The currents for a microprocessor and many microprocessor-interfacing compo-
3 Error
15 32 nents are less than for standard TTL components. (Logic 0 = 0.0 to 2.0 mA; logic 1 = 0.0 to 400 uA.)
4 4 Data 2 (D2)
16 RESET Once the output currents are known, we can now interface a device to one of the outputs.
5 5 Data 3 (D3)
31 Select in Figure 11-8 shows how to interface a simple LED to a microprocessor peripheral pin. Notice that
Data 4 (D4) 17
6 6 a transistor driver is used in Figure 1 l-8(a) and a TTL inverter is used in Figure 1 l-8(b). The TTL
18—25 19—30 Ground
7 7 Data 5 (D5) inverter (standard version) provides up to 16 mA of current at a logic 0 level, which is more than
17 Frame ground
8 Data 6 (D6) enough to drive a standard LED. A standard LED requires 10 mA of forward bias current to light. In
8 Ground
16 both circuits, we assume that the voltage drop across the LED is about 2.0 V. The data sheet for an
9 9 Data 7 (D7)
33 Ground LED states that the nominal drop is 1.65 V, but we know from experience that the drop is anywhere
10 Ack
10 between 1.5 V and 2.0 V. This means that the value of the current-limiting resistor is 3-° v/io mA or
11
Busy 300 Q. Since 300 Q is not a standard resistor value, we choose to use a 330 Q resistor.
FIGURE 11-5 The DB25 connector found on computers and the Centronics 36-pin connector In the circuit of Figure 1 l-8(a), we elected to use a switching transistor in place of the TTL
found on printers for the Centronics parallel printer interface. buffer. The 2N2222 is a good general-purpose switching transistor that has a minimum gain of
100. In this circuit, the collector current is 10 mA, so the base current will be 1/100 of the col-
lector current of 0.1 mA. To determine the value of the base current-limiting resistor, we use the

FIGURE 11-7 Debouncing VCC
switch contacts: (a) conven-
tional debouncing and
(b) practical debouncing.

vcc
(a) (b)

392 CHAPTER 11 BASIC I/O INTERFACE 11-2 I/O PORT ADDRESS DECODING 393

FIGURE 11-8 Interfacing and A15-AO for isolated I/O. Sometimes, if the I/O devices use only fixed I/O addressing, we
an LED: (a) using a transistor decode only A7-AO. In the personal computer system, we always decode all 16 I/O port address
and (b) using an inverter. bits. Another difference is that we use the IORC and IOWC to activate I/O devices for a read or
330 write operation. On earlier versions of the microprocessor, IO/M = 1 and RD or WR are used to
activate I/O devices. On the newest versions of the microprocessor, the M/IO = 0 and W/R are
Input- Input used to activate I/O devices.
18K 7404
Decoding 8-Bit I/O Addresses
(a) (b) As mentioned, the fixed I/O instruction uses an 8-bit I/O port address that appears on A15-AO
as OOOOH-OOFFH. If a system will never contain more than 256 I/O devices, we often decode
only address connections A7-AO for an 8-bit I/O port address. Thus, we ignore address connec-
FIGURE 11-9 A DC motor 12V tion A15-A8. Embedded systems often use 8-bit port addresses. Please note that the DX register
interfaced to a system by can also address I/O ports OOH-FFH. If the address is decoded as an 8-bit address, we can never
using a Darlington-pair. include I/O devices that use a 16-bit I/O address.
Figure 11-10 illustrates a 74ALS138 decoder that decodes 8-bit I/O ports FOH through
F7H. (We assume that this system will only use I/O ports OOH-FFH for this decoder example.)
Input
This decoder is identical to a memory address decoder except we only connect address bits
A7-AO to the inputs of the decoder. Figure 11-11 shows the PLD version, using a PAL for this
decoder. The PAL is a better decoder circuit because the number of integrated circuits has been
reduced to one device. The program for the PAL appears in Example 11-2.
0.1 mA current and a voltage drop of 1.7 V. The TTL input signal has a minimum value of 2.4 V
and the drop across the emitter-base junction is 0.7 V. The difference is 1.7 V, which is the EXAMPLE 11-2
voltage drop across the resistor. The value of the resistor is L7 v/o.i mA or 17K £1 Because 17K £1 AUTHOR Barry B. Brey
COMPANY BreyCo
is not a standard value, we used an 18K £1 resistor. DATE 7/1/99
Suppose that we need to interface a 12 V DC motor to the microprocessor and the motor CHIP DECODERS PAL16L8
current is 1A. Obviously, we cannot use a TTL inverter for two reasons: the 12V signal would
burn out the inverter and the amount of current far exceeds the 16 mA maximum current from ;pins 1 2 3 4 5 6 7 8 9 1 0
AO Al A2 A3 A4 A5 A6 A7 NC GND
the inverter. We cannot use a 2N2222 transistor either, because the maximum amount of current
is 250 mA to 500 mA, depending on the package style. The solution is to use a Darlington-pair. ;pins 11 12 13 14 15 16 17 18 19 20
Figure 11-9 illustrates the motor connected to the Darlington-pair. The Darlington-pair NC F7 F6 F5 F4 F3 F2 Fl FO VCC
has a minimum current gain of 7000 and a maximum current of 4A. The value of the bias resistor EQUATIONS
is calculated like the one used in the LED driver. The current through the resistor is 1 A/7000, or
about 0.143 mA. The voltage drop across the resistor is 0.9 V because we have two diode drops /FO = A7 * A6 A5 * A4 * A3 /A2 * /Al * /AO
/Fl = A7 * A6 A5 * A4 * A3
instead of one. The value of the bias resistor is °-9 v/o.i43 mA or 6.29KQ. The standard value of /F2 = A7 * A6 A5 * A4 * A3
/A2 * /Al * AO
/A2 * Al * /AO
6.2 KQ is used in the circuit. The Darlington-pair must be heat-sinked because of the amount /F3 = A7 * A6 A5 * A4 * A3 /A2 * Al * AO
of current going through it and the diode must also be present to prevent the Darlington-pair /F4 = A7 * A6 * A5 * A4 * A3 * A2 * /Al * /AO
/F5 = A7 * A6 * A5 * A4 * A3 * A2 * /Al * AO
from being destroyed by the inductive kick-back from the motor. This circuit is also used to in- /F6 = A7 A6 A5 A4 A3 A2 * Al /AO
terface mechanical relays or just about any device that requires a large amount of current or a /F7 = A7 * A6 * A5 * A4 * A3 A2 Al AO
change in voltage.

FIGURE 11-10 A port de- Ul
coder that decodes 8-bit I/O
A YU
ports. This decoder generates Al 2 3 14 F1H
B Yl
11-2 I/O PORT ADDRESS DECODING active low outputs for ports
A2 3 C Y2
Y3 ^12 F3H
FOH-F7H. Y4
I/O port address decoding is very similar to memory address decoding, especially for memory- A4 6 Gl p3 FTH
A3 4^ G2A Y5 Q p^r TT
mapped I/O devices. In fact, we do not discuss memory-mapped I/O decoding because it is Y6
g7 FTH
treated the same as memory (except that the IORC and IOWC are not used because there is no IN r* G2B Y7

or OUT instruction). The decision to use memory-mapped I/O is often determined by the size of U2A 74ALS138
A5
the memory system and the placement of the I/O devices in the system. A6
The main difference between memory decoding and isolated I/O decoding is the number of A7
address pins connected to the decoder. We decode A31-AO, A23-AO, or A19-AO for memory; 74LS10

394 CHAPTER 11 BASIC I/O INTERFACE 11-2 I/O PORT ADDRESS DECODING 395

FIGURE 11-11 APAL16L8 Ul 8-And 16-Bit I/O Ports
decoder that generates I/O AO 11 01 -19 FOH
12 02 -18 F1H Now that we understand that decoding the I/O port address is probably simpler than decoding a
port signals for port FOH-F7H. ^ X17 F2H
A3
A^
13 03 :i6 F3H memory address (because of the number of bits), we explain how data are transferred between
14 O4
A4 15 O5 3H F4H the microprocessor and 8- or 16-bit I/O devices. Data transferred to an 8-bit I/O device exist in
A5 16 O6 X2~ F5H
A6 Oil F6H one of the I/O banks in a 16-bit microprocessor such as the 80386SX. The I/O system contains
17 O7 ^12 F7H
A7 18 08 two 8-bit memory banks, just as memory does. This is illustrated in Figure 11-13, which shows
19 the separate I/O banks for a 16-bit system such as the 80386SX.
110
Because two I/O banks exist, any 8-bit I/O write requires a separate write strobe to func-
16L8 tion correctly. I/O reads do not require separate read strobes. As with memory, the micro-
processor reads only the byte it expects and ignores the other byte. The only time that a read can
cause problems is when the I/O device responds incorrectly to a read operation. In the case of an
I/O device that responds to a read from the wrong bank, we may need to include separate read
Decoding 16-Bit I/O Addresses signals. This is discussed if the case arises later in this chapter.
We also decode 16-bit I/O addresses, especially in a personal computer system. The main differ- Figure 11-14 illustrates a system that contains two different 8-bit output devices, located at
ence between decoding an 8-bit I/O address and a 16-bit I/O address is that eight additional ad- 8-bit I/O address 40H and 41H. Because these are 8-bit devices and because they appear in dif-
dress lines (A15-A8) must be decoded. Figure 11-12 illustrates a circuit that contains a ferent I/O banks, we generate separate I/O write signals. Note that all I/O ports use 8-bit addresses.
PAL16L8 and an 8-input NAND gate used to decode I/O ports EFF8H-EFFFH. Thus, ports 40H and 41H can each be addressed as separate 8-bit ports, or together as one 16-bit
The NAND gate decodes the first eight bits of the I/O port address (A15-A8). The output port. The program for the PAL16L8 decoder used in Figure 11-14 is illustrated in Example 11—4.
of the NAND gate generates a signal to enable the PAL16L8 for any I/O address between EFOOH
EXAMPLE 11-4
and EFFFH. The PAL16L8 further decodes the I/O address to produce eight active low output
strobes EFF8H-EFFFH The program for the PAL16L8 decoder appears in Example 11-3. AUTHOR Barry B. Brey
COMPANY BreyCo
DATE ' 7/3/99
EXAMPLE 11-3 CHIP DECODERA PAL16L8
AUTHOR Barry B. Brey
;pins 1 2 3 4 5 6 7 8 9 10
COMPANY BreyCo
BHE IOWC AO Al A2 A3 A4 A5 A6 GND
DATE 7/2/99
CHIP DECODER9 PAL16L8
;pins 11 12 13 14 15 16 17 18 19 20
A7 NC NC NC NC NC NC 40 41 VCC
;pins 1 2 3 4 5 6 7 8 9 10
AO Al A2 A3 A4 A5 A6 A7 NAND GND EQUATIONS
;pins 11 12 13 14 15 16 17 18 19 20
NC EFFFH EFFEH EFFDH EFFCH EFFBH EFFAH EFF9H EFF8H VCC 740 = /BLE * /IOWC * /A7 * A6 * /A5 * /A4 * /A3 * /A2 * /Al
741 = /BHE * /IOWC * 7A7 * A6 * /A5 * /A4 * /A3 * /A2 * /Al
EQUATIONS

/A2 * /Al * /AO * /NAND
When selecting 16-bit wide I/O devices, the BLE (AO) and BHE pins have no function be-
/EFF8H = A7 A6 * A5 * A4 * A3 *
/EFF9H = A7 A6 * A5 * A4 * A3 * /A2 * /Al * AO * /NAND cause both I/O banks are selected together. Although 16-bit I/O devices are relatively rare, a few
/EFFAH = A7 A6 * A5 * A4 * A3 * /A2 * Al * /AO * /NAND
/EFFBH = A7 A6 * A5 * A4 * A3 * /A2 * Al * AO * /NAND
/EFFCH = A7 A6 * A5 * A4 * A3 * A2 * /Al * /AO * /NAND FIGURE 11-13 The I/O
A6 * A5 * A4 * A3 * A2 * /Al * AO * /NAND banks found in the 8086,
(BLE)
/EFFDH = A7
A6 * A5 * A4 * A3 * A2 * Al * /AO * /NAND BHE AO
/EFFEH = A7 80186, 80286, and 80386SX.
/EFFF7 = A7 A6 * A5 * A4 * A3 * A2 * Al * AO * /NAND FFFF FFFE
FFFD FFFC

^^^
FFFB
U1A FFFA
FIGURE 11-12 APAL16L8
U3
decoder that decodes 16-bit A12_ Sx>^ AO
MU
1
K~ 11 01 :>|f-|EE|
address EFF8H-EFFFH. 12 O2
74LS04 A2 —— | 13 O3 OTS— EFFA High bank Low bank
A3 —— i 14 04 OJf-EFFB
! U2 ___ 3_
& 15 O5
A15 2 A5 —— | 16 06

y-
A6 —— 4- 17 O7
A14.
A13. ——— > o A7 —— | 18
y 19 O8 0005 0004
A11 5 110 0003
6 ^ 0002
A10 16L8 0001
A9.
A8. U -7/11 oon D15-
0000

11-2 I/O PORT ADDRESS DECODING
396 CHAPTER 11 BASIC I/O INTERFACE 397
FIGURE 11-15 A 16-bit
FIGURE 11-14 An I/O port D15-D8
D15-D8 U2 I/O port decoded at I/O U2
decoder that selects ports
V-1- DO QO _1__ addresses 64H and 65H. VI8_ 1Y1 2
40H and 41H for output data. 1A1
__4_ Dl Ql _1_ Njfi_ 1A2 4
1Y2
_z_ D2 Q2 _6__
_9 _
J4_ 1Y3 1A3 6
D3 Q3 M2_ 1Y4 1A4 8
J1_ D4 Q4
12 Port41H V_9_ 2Y1 2A1 11 Port 65H
XJLL D5 Q5 J5_ 7 13
2Y2 2A2
sai_ D6 Q6
J6_ VX. 2Y3 2A3 15
_18_ D7 Q7
19 V^_ 2Y4 2A4 17

———— lc OC 1G 3 1
11 >CLK 2G D 19
Ul
BHE __ L_ 11 -19 74ALS374 74ALS244
01
IOWC __ 2_ 12 02 ^18 Ul
AO __ 3_ ^17 IORC 1
13 O3 11 Ol -02 ——
Al __ i_ :>&-
14 04 12 02 :>1S_
A2 __ 5_ 15 05 o^- U3 13 03 ^~
A3 __ 6_
A4 __ 7_
A5 __ 8_
16
17
06
07 &:
~12
/-f DO
Dl
QO
Ql
_2_
~7 ——
A4
A5
14
5~ 15
6
O4
O5
^16
^15
18 08 16 O6
A6 _ 9_ 19 / 0~
D2 Q2 -| —— A6 7
A7 11 110
£
^K
^K
D3
D4
D5
Q3
Q4
Q5
~12"~ Port40H
J5_
17
18
19
n~ 110
O7
O8 ^12~

^ 1Y2
1Y1
U3
1A1 2
4
16L8
^L D6
D7
Q6
Q7 nn ^ 14
1Y3 1A3
1 A?
6
8
—k
ii >CLK OC 16L8
1Y4
2Y1 7A1
1/T-
11 Port64H
^ 7 13
2Y2
2Y3 ?A3 15
74ALS374 17
D7-DO 2Y4 2A4
1G
— =r

D7-DO
2G fc
74ALS244
do exist for analog-to-digital and digit-to-analog converters, as well as for some video and disk
memory interfaces.
Figure 11-15 illustrates a 16-bit input device connected to function at 8-bit I/O addresses 32-Bit Wide I/O Ports
64H and 65H. Notice that the PAL16L8 decoder does not have a connection for address bit BLE
(AO) and BHE because these signals do not apply to 16-bit wide I/O devices. The program for Although 32-bit wide I/O ports are not common, they may eventually become commonplace be-
the PAL16L8, illustrated in Example 11-5, shows how the enable signals are generated for the cause of newer buses found in computer systems. The once-promising EISA system bus supports
three-state buffers (74ALS244) used as input devices. 32-bit I/O as well as the VESA local and current PCI bus, but these are found only in some com-
puter systems.
EXAMPLE 11-5 The circuit of Figure 11-16 illustrates a 32-bit input port for the 80386DX or 80486 mi-
croprocessor. As with prior interfaces, this circuit uses a single PAL to decode the I/O ports and
AUTHOR Barry B . Brey
BreyCo
four 74LS244 buffers to connect the I/O data to the data bus. The I/O ports decoded by this in-
COMPANY
DATE 7/5/99 terface are the 8-bit ports 70H-73H, as illustrated by the PAL program in Example 11-6. Again,
CHIP DECODERS PAL16L8 we only decode an 8-bit I/O port address.

;pins 1 2 3 4 5 6 7 8 9 10 EXAMPLE 11-6
IORC Al A2 A3 A4 A5 A6 A7 NC GND
;pins 11 12 13 14 15 16 17 18 19 20 AUTHOR Barry B. Brey
NC NC NC NC NC NC NC NC 06X VCC COMPANY BreyCo
DATE 7/6/99
EQUATIONS CHIP DECODERC PAL16L8

/064 = /IORC * /A7 * A6 * A5 * /A4 * /A3 * A2 * /Al 6 7 9 10

398 CHAPTER 11 BASIC I/O INTERFACE 11-3 THE PROGRAMMABLE PERIPHERAL INTERFACE 399
FIGURE 11-16 A 32-bit
1A1 1Y1 FIGURE 11-17 The pin-out 82C55
input port decoded at bytes
Input data
~- 1A2
6
8 1A3
1Y2
1Y3 =JF of the 82C55 peripheral inter- 34
70H-73H. 1A4 1Y4 DO PAO
face adapter (PPI). PA I __.3__
2A1 2Y1 Data bus D31 - D24 33 Dl
(73H) 32
PA2 — 2 —
2A2 2Y2
D2
15
2A3
-n— 2A4
2Y3
2Y4 ± _^i_
30
D3 PA3
29
D4 PA4 -40_
r-^K 1G
1 —— ^C 2G
28
D5 PAS _22_
74LS2 44 27
D6 PA6 _^8_
U3 D7 PA7 _32_
2 1Y1 lo
1A1
1A2 1Y2
36
RD
Input data -j- 1A3 1Y3
" 2
1 ~ WR PBO _LS_
PB1 -L2_
1A4 1Y4
1J
2A1 2Y1
9 busD23-D16 AO
2A2 2Y2 (72H) Al PB2 _2£L_
U1
± 2A3
2A4
2Y3
2Y4 =E 35 RESET PB3 _2I_
PB4 _22__
1 19
PB5 J>3_
1c

± 4
11
12
13
01
02
03
gt
i
1G
2G
74LS244
PB6 LH
PB7 _J5_
14
15
O4
O5 °E U4
16 O6 ^F
m~ 1A1 1Y1 PCO 14
17
18
07
O8 >^— - - 1A2
I 1Y2
£ Vcc = pin 26
6
PCI 15
3E 19
110
Input data 1A3
- - 1A4
1

4i- 2A1
1Y3
1Y4
2Y1 3E Data bus D15-
Gnd = pin 7 PC2 16
PC3
2A2 2Y2 (71H)
16L8 PC4 _13_
dfc 2A3
2A4
2Y3
2Y4 EE PCS
PC6 11
I 1G
•-T^ 2G PC7 _j&_
74LS244
U5
ib
4
1A1
1A2
1Y1
1Y2 nn 82C55 can interface any TTL-compatible I/O device to the microprocessor. The 82C55 (CMOS
Input data =
1A3
t 1A4
1Y3
1Y4
~il~
__ 11
2A1 2Y1 9
'
Data bus D7 - DO version) requires the insertion wait states if operated with a microprocessor using higher than
-— 1 . J
2A2 2Y2 (70H)
-....- 1_5 2A3 2Y3 — § — an 8 MHz clock. It also provides at least 2.5 mA of sink (logic 0) current at each output, with a
_1Z_ 2A4 2Y4 — ^—
I{ 1c maximum of 4.0 mA. Because I/O devices are inherently slow, wait states used during I/O trans-
1G
1 ——— !2_c 2G fers do not impact significantly upon the speed of the system. The 82C55 still finds application
(compatible for programming, although it may not appear in the system as a discrete 82C55), even
in the latest Pentium II-based computer system. The 82C55 is used for interface to the keyboard
IORC A7 A6 A5 A4 A3 A2 NC NC GND and the parallel printer port in many personal computers, but it is found as a function within a in-
terfacing chipset. The chipset also controls the timer and reads data from the keyboard interface.
;pins 11 12 13 14 15 16 17 18 19 20
NC NC NC NC NC NC NC NC SEL VCC
Basic Description of the 82C55
EQUATIONS
Figure 11-17 illustrates the pin-out diagram of the 82C55. Its three I/O ports (labeled A, B, and
/SEL = /IORC A6 * A5 C) are programmed as groups. Group A connections consist of port A (PA7-PAO) and the upper
half of port C (PC7-PC4), and group B consists of port B (PB7-PBO) and the lower half of port
With the Pentium-Pentium II micorprocessors and their 64-bit data buses, I/O ports appear C (PC3-PCO). The 82C55 is selected by its CS pin for programming and for reading or writing
in various banks, as determined by the I/O port address. For example, 8-bit I/O port 0034H ap- to a port. Register selection is accomplished through the Al and AO input pins that select an in-
pears in Pentium I/O bank 5, while the 16-bit I/O port 0034H-0035H appears in Pentium banks ternal register for programming or operation. Table 11-2 shows the I/O port assignments used
5 and 6. A 32-bit I/O access in the Pentium system can appear in any four consecutive I/O banks. for programming and access to the I/O ports. In the personal computer, an 82C55 or its equiva-
For example, 32-bit I/O port 0100H-0103H appears in banks 0-3. How is a 64-bit I/O device in- lent is decoded at I/O ports 60H-63H.
terfaced? The widest I/O transfers are 32 bits, and currently there are no 64-bit I/O instructions The 82C55 is a fairly simple device to interface to the microprocessor and program. For
to support 64-bit transfers. the 82C55 to be read or written, the CS input must be a logic 0 and the correct I/O address must

TABLE 11-2 I/O port as-
signments for the 82C55. A1 A0 Function
11-3 THE PROGRAMMABLE PERIPHERAL INTERFACE
0 0 Port A
The 82C55 programmable peripheral interface (PPI) is a very popular, low-cost interfacing 0 1 PortB
component found in many applications. The PPI, which has 24 pins for I/O that are program- 1 0 PortC
mable in groups of 12 pins, has groups that operate in three distinct modes of operation. The 1 1 Command Register

11-3 THE PROGRAMMABLE PERIPHERAL INTERFACE 401
FIGURE 11-19 The com- Command byte A
mand byte of the command
D7 — DO 7 6 5 4 3 2 1 0
U2 register in the 82C55. (a) Pro-
V3i_ DO PAO - 4 grams ports A, B, and C 1
J3_ 3 (b) Sets or resets the bit indi-
Dl 2 I- 1
V12_ D2 cated in the select a bit field. Group B
V^i_ 1
D3 40 Port A
JO_ D4 r/T- Port C (PC3 - PCO)
^i_ 39 1 = input
D5 F/YJ
38
J8_ D6 PA6 0 = output
_27_ 37
D7
• 5 18 PortB
IORC RD PBO
36 PB1 19
IOWC WR 0 = output
9 20
Al AO PB2
8 21
A2 Al PB3 PortB Mode
35 PB4 22
RESET RESET 00 = mode 0
6 23 01 = mode 1
CS PB5
24
PB6
PB7 25
Ul
A7 [
A YO PCO 14
B Yl pl.4 PCI 15
A4 -3- C Y2 PC2
16 Group A
Y3 ^12 PC3
17
13 PortC
A6 -f Gl Y4 PC4 Port C (PC7 — PC4)
^10 12
A5 -*<; G2A Y5 9 PC5
AO ~Q G2B Y6 11 0 = output
7 PC6
Y7 D PC7 10
Port A
74ALS138 82C55
0 = output
FIGURE 11-18 The 82C55 interfaced to the low bank of the 80386SX microprocessor.
Mode
00 = mode 0
be applied to the Al and AO pins. The remaining port address pins are don't cares as far as the 01 = mode 1
IX = mode 2
82C55 is concerned, and are externally decoded to select the 82C55.
Figure 11-18 shows an 82C55 connected to the 80386SX so that it functions at 8-bit I/O
port addresses COH (port A), C2H (port B), C4H (port C), and C6H (command register). This in-
terface uses the low bank of the 80386SX I/O map. Noticefrom this interface that all the 82C55 Command byte B
pins are direct connections to the 80386SX, except for the CS pin. The CS pin is decoded and se-
7 6 5 4 3 2 1 0
lected by a 74ALS138 decoder.
The RESET input to the 82C55 initializes the device whenever the microprocessor is reset.
A RESET input to the 82C55 causes all ports to be set up as simple input ports using mode 0 op-
eration. Because the port pins are internally programmed as input pins after a RESET, damage is
prevented when the power is first applied to the system. After a RESET, no other commands are
needed to program the 82C55, as long as it is used as an input device for all three ports. Note that
an 82C55 is interfaced to the personal computer at port addresses 60H-63H for keyboard con-
trol; and also for controlling the speaker, timer, and other internal devices such as memory ex-
pansion. This is true for any AT or earlier style personal computer system. Selects a bit

(b)
Programming the 82C55
The 82C55 is programmed through the two internal command registers that are illustrated in
Figure 11-19. Notice that bit position 7 selects either command byte A or command byte B. tions. Mode 1 operation is the strobed operation for group B connections, where data are trans-
Command byte A programs the function of group A and B, while command byte B sets (1) or referred through port B and handshaking signals are provided by port C.
sets (0) bits of port C only if the 82C55 is programmed in mode 1 or 2. Group A pins (port A and the upper part of port C) are programmed as either input or
Group B pins (port B and the lower part of port C) are programmed as either input or
output pins. The difference is that group A can operate in modes 0, 1, and 2. Mode 2 operation is
output pins. Group B operates in either mode 0 or mode 1. Mode 0 is the basic input/output mode a bi-directional mode of operation for port A.
that allows the pins of group B to be programmed as simple input and latched output connec-


If a 0 is placed in bit position 7 of the command byte, command byte B is selected. This
command allows any bit of port C to be set (1) or reset (0), if the 82C55 is operated in either
mode 1 or 2. Otherwise, this command byte is not used for programming. We often use the bit
set/reset function in a control system to set or clear a control bit at port C. The bit set/reset func-
tion is glitch-free, which means that the other port C pins will not change during the bit set/reset
command.

Mode 0 Operation
Mode 0 operation causes the 82C55 to function either as a buffered input device or as a latched
output device. These are the same as the basic input and output circuits discussed in the first sec-
tion of this chapter.
Figure 11-20 shows the 82C55 connected to a set of eight 7-segment LED displays. In this
circuit, both ports A and B are programmed as (mode 0) simple latched output ports. Port A pro-
vides the segment data inputs to the display and port B provides a means of selecting one display
position at a time for multiplexing the displays. The 82C55 is interfaced to an 8088 micro-
processor through a PAL16L8 so that it functions at I/O port numbers 0700H-0703H. The pro-
gram for the PAL16L8 is listed in Example 11-7. The PAL decodes the I/O address and
develops the write strobe for the WR pin of the 82C55.

EXAMPLE 11-7
COMPANY BreyCo
DATE 7/6/99
CHIP DECODERD PAL16L8

;pins 1 2 3 4 5 6 7 8 9 10
A2 A3 A4 A5 A6 A7 A8 A9 AlO GND

;pins 11 12 13 14 15 16 17 18 19 20
All CS IOM A12 A13 A14 A15 NC NC VCC

EQUATIONS
/CS = /A15 * /A14 * /A13 * /A12 * /All * AlO * A9 * A8 * /A6 * /A5 * /A4 * /A3 *
/A2 * /IOM

The resistor values are chosen in Figure 11-20 so that the segment current is 80 mA. This
current is required to produce an average current of 10 mA per segment as the displays are mul-
tiplexed. A 6-digit display uses a segment current of 60 mA, for an average of 10 mA per seg-
ment. In this type of display system, only one of the eight display positions is on at any given
instant. The peak anode current in an 8-digit display is 560 mA (seven segments x 80 mA), but
the average anode current is 80 mA. In a 6-digit display, the peak current would be 420 mA
(seven segments x 60 mA). Whenever displays are multiplexed, we increase the segment current Q
ID
from 10 mA (for a display that uses 10 mA per segment as the nominal current) to a value equal
to the number of display positions times 10 mA. This means that a 4-digit display uses 40 mA
per segment, a 5-digit display uses 50 mA, and so on.
In this display, the segment load resistor passes 80 mA of current and has a voltage of ap-
proximately 3.0 V across it. The LED (1.65 V nominally) and a few tenths are dropped across
the anode switch and the segment switch, hence a voltage of 3.0 V appears across the segment
load resistor. The value of the resistor is 3'° v /somA = 37.5 £1. The closest standard resistor value
UJ
of 39 Q is used in Figure 11-20 for the segment load. DC
The resistor in series with the base of the segment switch assumes that the minimum gain
O
of the transistor is 100. The base current is therefore 80 mA/ioo = 0.8 mA. The voltage across the
base resistor is approximately 3.0 V (the minimum logic 1 voltage level of the 82C55), minus
403

404 CHAPTER 11 BASIC I/O INTERFACE 11-3 THE PROGRAMMABLE PERIPHERAL INTERFACE
405
the drop across the emitter-base junction (0.7 V), or 2.3 V. The value of the base resistor is then 0022 42 INC DX ;address Port B
0023 4B DEC BX
2.3 V/0.8 mA = 2.875 KW. The closest standard resistor value is 2.7 KW, but a 2.2 KW is 0024 75 FO
;adjust count
JNZ DISP1 ;repeat 8 times
chosen for this circuit.
The anode switch has a single resistor on its base. The current through the resistor is 0026 5E POPF ;restore registers
560 mA/100 = 5.6 mA because the minimum gain of the transistor is 100. This exceeds the RET

maximum current of 4.0 mA from the 82C55, but this is small enough so that it will work without 002C DISP ENDP
problems. The maximum current assumes that you are using the port pin as a TTL input to another
circuit. If the amount of current were over 8.0-10.0 mA, then appropriate circuitry (in the form of The display procedure (DISP) addresses an area of memory where the data, in 7-segment
either a Darlington-pair or another transistor switch) would be required. Here, the voltage across code, is stored for the eight display digits called MEM. The AH register is loaded with a code
the base resistor is 5.0 V, minus the drop across the emitter-base junction (0.7 V), minus the (7FH) that initially addresses the most-significant display position. Once this position is selected,
voltage at the port pin (0.4 V), for a logic 0 level. The value of the resistor is 3.9 V/5.6 mA = 696 the contents of memory location MEM +7 is addressed and sent to the most-significant digit. The
W. The closest standard resistor value is 690 W, which is chosen for this example. selection code is then adjusted to select the next display digit, as is the address. This process repeats
Before software to operate the display is examined, we must first program the 82C55. This eight times to display the contents of location MEM through MEM +7 on the eight display digits.
is accomplished with the short sequence of instructions listed in Example 11-8. Here, port A and
B are both programmed as outputs. An LCD Display Interfaced to the 82C55. LCDs (liquid crystal displays) are quickly replacing
LED displays in many applications. The only disadvantage of the LCD display is that it is diffi-
EXAMPLE 11-8 cult to see in low-light situations in which the LED is still in limited use.
;programming the 82C55 PIA
Figure 11-21 illustrates the connection of the Optrex DMC-20481 LCD display to an
82C55. The DMC-20481 is a 4-line by 20-characters-per-line display that accepts ASCII code as
0000 BO 80 MOV AL,10000000B input data. It also accepts commands that initialize it and control its application. As you can see in
0002 BA 0703 MOV DX,703H ;address command
0005 EE OUT DX,AL ;program 82C55 Figure 11-21, the LCD display has few connections. The data connections, which are attached to
the 82C55 Port A, are used to input display data and to read information from the display.
The procedure to multiplex the displays is listed in Example 11-9. For the display system There are four control pins on the display. The VEE connection is used to adjust the con-
to function correctly, we must call this procedure often. Notice that the procedure calls another trast of the LED display and is normally connected to a 10 KQ potentiometer, as illustrated. The
procedure (DELAY) that causes a 1 ms time delay. The time delay is not illustrated in this ex- RS (register select) input selects data (RS = 1) or instructions (RS = 0). The E (enable) input
ample, but it is used to allow time for each display position to turn on. It is recommended by the must be a logic 1 for the DMC-20481 to read or write information. Finally, the R/W pin selects
manufacturers of LED displays that the display flash be between 100 Hz and 1500 Hz. Using a 1 a read or a write operation. Normally, the RS pin is placed at a 1 or 0, the R/W pin is set or
ms time delay, we light each digit for 1 ms for a total display flash rate of 1000 Hz/8 display, or cleared, data are placed on the data input pins, and then the E pin is pulsed to access the
a flash rate of 125 Hz. DMC-20481. This display also has two inputs for back-lighting LED diodes, which are not
shown in the illustration.
EXAMPLE 11-9 In order to program the DMC-20481 we must first initialize it. This applies to any display
;Procedure that multiplexes the 8-digit LED display. that uses the HD44780 (Hitachi) display driver integrated circuit. The entire line of small display
;This procedure must be called from a program at panels from Optrex is programmed in the same manner. Initialization is accomplished via the fol-
;whenever possible to display 7-segment lowing steps:
;coded data from memory.
1. Wait at least 15 ms after Vcc rises to 5.0 V.
0006 DISP PROC NEAR USES AX BX DX SI
2. Output the function set command (30H), and wait at least 4.1 ms.
O O O A 9C PUSHF ;save flag register 3. Output the function set command (30H) a second time, and wait at least 100 fis.
4. Output the function set command (30H) a third time, and wait at least 40 ju,s.
;setup registers for display
5. Output the function set command (38H) a fourth time, and wait at least 40 jus.
OOOB BB 0008 MOV BX,8 ;load count 6. Output a 08H to disable the display, and wait at least 40 jus.
OOOE B4 7F MOV AH,7FH ;load selection pattern
0010 BE OOFF R MOV SI,OFFSET MEM-1 ;address data
7. Output a 01H to home the cursor and clear the display, and wait at least 1.64 ms.
0013 BA 0701 MOV DX,701H ;address Port 8. Output the enable display cursor off (OCH), and wait at least 40 jis.
9. Output a 06H to select auto-increment, shift the cursor, and wait at least 40 jus.
;display 8 digits
The software to accomplish the initialization of the LCD display is listed in Example 11-10.
0016 DISP1:
0016 8A C4 MOV AL,AH ;select a digit It is long, but the display controller requires the long initialization dialog. Note that the software
0018 EE OUT DX,AL for the three time delays is not included in the listing. If you are interfacing to a PC, you can use
0019 4A DEC DX ;address Port A the clock tick discussed in Chapter 7 for the time delay. One clock tick can be used for all timing
001A 8A 00 MOV AL,[BX+SI] ;get 7-segment data
001C EE OUT DX,AL in this software, even though the LCD display will function faster than your eye at 1/18 seconds.
001D E8 029A R CALL DELAY ;wait one millisecond If you are developing the interface for another application, then you must write three separate time
0020 DO CC ROR AH,1 ;address next digit delays, which must provide the delay times indicated in the initialization dialog.

FIGURE 11-21 TheDMC- 005B BO 04 MOV AL, 4 ;put 1 on E, 0 on R/W# and 0 on S
20481 LCD display interfaced PA2
005D EE OUT DX,AL
PAS 005E 90 NOP ; extra. time so E = 1 longer
to the 82C55. PA4
005F 90 NOP
PAS
PA6 0060 BO 00 MOV AL, 0
PA7 4 line x 20 0062 EE OUT DX,AL ; clear E
PBO
PB1
LCD display 0063 E8 0029 CALL DELAY1 0 0 ;wait 100 us
PB2
PB3
0066 C3 ivjjj.
RET
PB4 vcc VCC 0067 OUTCMD ENDP

The NOP instructions are added in the OUTCMD procedure to ensure that the E bit re-
PGO 10K
PC1
PC2
mains a logic 1 long enough to activate the LCD display. This process should work in most sys-
PCS
PC4
tems at most clock frequencies, but additional NOP instructions may be needed to lengthen this
PCS time in some cases.
Before programming data to the display, the commands used in the initialization dialog
82C55 DMC-20481 must be explained. See Table 11-3 for a complete listing of the commands or instructions for the
LCD display. Compare the commands sent to the LCD display in the initialization program to
Table 11-3.
*Current max is 480 mA, nominal 260 mA
Once the LCD display is initialized, a few procedures are needed to display information
and control the display. After initialization, time delays are no longer needed when sending data
EXAMPLE 11-10 or many commands to the display. The clear display command still needs a time delay because
the busy flag is not used with that command. Instead of a time delay, the busy flag is tested to
; procedure to xnitiaiiz e tne LIUJJ axspj.ay
see whether the display has completed an operation. A procedure to test the busy flag appears in
0010 INIT PROC NEAR Example 11-11. The BUSY procedure tests the LCD display and only returns when the display
has completed a prior instruction.
0010 BA 0303 MOV DX,CMD8255 ; address 8255 command register
0013 BO 80 MOV AL,80H ;all ports are output ports
0015 EE OUT DX, AL
MOV AL,0 ; clear Port B TABLE 11-3 Instructions for most Optrex LCD displays.
0016 BO 00
0018 BA 0301 MOV DX,PORTB
001B EE OUT DX,AL Instruction Code Description Execution Time
001C E8 004A CALL DELAY 15 ;wait 15 ms
001F BO 30 MOV AL,30H ; first function set command Clear display 0000 0001
002A CALL OUTCMD ; s end i t Clears display and homes the 1 .64 ms
0021 E8
0024 E8 0056 CALL DELAY41 ;wait 4.1 ms cursor
0027 BO 30 MOV AL , 3 OH Cursor home 00000010 Homes the cursor 1 .64 ms
0029 E8 0022 CALL OUTCMD ; second function set command
AL,30H ; third function set command Entry mode set 0000 OAS Sets cursor movement 40 (is
002C BO
30 MOV
002E E8
001D CALL OUTCMD direction (A=1 increment)
0031 BO 38 MOV AL,38H ; fourth function set command and shift (S=1 shift)
0033 E8 0018 CALL OUTCMD Display on/off
0036 E8 0058 CALL DELAY100 0000 1DCB Sets display on/off 40 us
0039 BO 08 MOV AL,08H ; display off (D=1 on) (C=1 cursor on)
003B E8 0010 CALL OUTCMD (B=1 cursor blink)
003E BO 01 MOV AL, 01H ; clear display
CALL OUTCMD Cursor/display shift 0001 SROO Sets cursor movement and 40 (is
0040 E8 OOOB
0043 BO OC MOV AL,OCH ; display on, cursor off display shift (S-1 shift display)
0045 E8 0006 CALL OUTCMD (S=0 move cursor) (R=1 right)
0048 BO 06 MOV AL,06H ; auto- increment, shift cursor
Function set 001LNFOO Programs chip (L=1 8-bit, 40 (is
004A E8 0001 CALL OUTCMD
004D C3 RET L=0 4-bits) (1X1=1 2 lines)
004E INIT ENDP (F=1 5x10, F=0 5x7)
Set CGRAM address 01XXXXXX Sets character generator 40 (is
; procedure to output a command
RAM address
004E OUTCMD PROC NEAR Set DRAM address 10XXXXXX Sets display RAM address
004E 50 PUSH AX ; save command 40 (is
004F BA 0303 MOV DX,CMD8255 ; select 8255 command resgiter Read busy flag BOOO 0000 Reads busy flag (B=1 busy) 0
0052 BO 80 MOV AL,80H ;all ports are outputs Write data Data Writes data to display or
0054 EE OUT DX, AL
0055 BA 0300 MOV DX,PORTA character generator RAM 40 (is
0058 58 POP AX Read data Data Reads data from display or 40 (is
0059 EE OUT DX,AL ; command to port A
; address Port B character generator RAM
005A 42 INC DX


EXAMPLE 11-11 The only other procedure that is needed for a basic display is the clear and home cursor
/procedure to test busy and return if not busy procedure called CLS, shown in Example 11-13. With CLS and the procedures presented thus
BUSY PROC NEAR far, you can display any message on the display, clear it, display another message, and basically
.REPEAT operate the display. As mentioned earlier, the clear command requires a time delay (at least 1.64
0010 BA 0303 MOV DX,CMD8255 ;•select 8255 command reg:
D ms) instead of a call to BUSY for proper operation. In this procedure, we used the 4.1 ms time
0013 BO 90 MOV AL,90H ;port A input delay.
0015 EE OUT DX,AL
0016 BA 0301 MOV DX,PORTB ; select port B
:
AL,1 ;;R/W# = 1 EXAMPLE 11-13
0019 BO 01 MOV
001B EE OUT DX,AL ;procedure to clear the display and home the cursor
001C BO 05 MOV AL,5 ;;R/W# = 1 , E = 1, RS = 0
001E EE OUT DX,AL 005A CLS PROC NEAR
001F 90 NOP ; delay to allow access 005A BA 0303 MOV DX, CMD8255
0020 90 NOP 005D BO 80 MOV AL, 80H
0021 BA 0300 MOV DX,PORTA ; select port A 005F EE OUT DX,AL
0024 EC IN AL,DX ;get status of busy flag 0060 BA 0300 MOV DX, PORTA
0025 50 PUSH AX 0063 BO 01 MOV AL, 1 ;clear instruction
0026 BA 0301 MOV DX,PORTB 0065 EE OUT DX,AL
0029 BO 00 MOV AL,0 0066 BA 0301 MOV DX, PORTB
002B EE OUT DX,AL 0069 BO 04 MOV AL, 4 ;RS = 0, R/W# = 0 , E = 1
002C BA 0303 MOV DX,CMD8255 006B EE OUT DX,AL
002F BO 80 MOV AL,80H 006C 90 NOP
0031 EE OUT DX,AL 006D 90 NOP
0032 58 POP AX 006E BO 00 MOV AL, 0 ;RS = 0, R/W# = 0 , E = 0
0033 DO EO SHL AL,1 0070 EE OUT DX,AL
.UNTIL ! CARRY? ; until not busy 0071 E8 0044 CALL DELAY41
0037 C3 RET 0074 C3 RET
0038 BUSY ENDP 0075 CLS ENDP

Once the BUSY procedure is available, data can be sent to the display by writing another Additional procedures that could be developed might select a display RAM position. The
procedure called WRITE. The WRITE procedure uses BUSY to test before trying to write new display RAM address starts at 0 and progresses across the display until the last character address
data to the display. Example 11-12 shows the WRITE procedure, which transfers the ASCII char- on the first line is location 19, location 20 is the first display position of the second line, and so
acter from the BL register to the current cursor position of the display. Note that the initialization forth. Once you can move the display address, you can change individual characters on the dis-
dialog has sent the cursor for auto-increment, so if WRITE is called more than once, the characters play and even read data from the display. These procedures are for you to develop if they are
written to the display will appear one next to the other, as they would on a video display. needed.
A word about the display RAM inside of the LCD display. The LCD contains 128 bytes of
EXAMPLE 11-12 memory, addresssed from OOH to 7FH. Not all of this memory is used. For example, the one-line
/procedure that writes the ASCII ntents of the BL x 20-character display uses only the first 20 bytes of memory (OOH-13H.) The first line of any of
/register to the display these displays always starts at address OOH. The second line of any display powered by the
NEAR
HD44780 always begins at address 40H. For example, a two-line x 40-character display uses ad-
003A WRITE PROC
003A BA 0303 MOV DX,CMD8255 dresses OOH-27H to store ASCII-coded data from the first line. The second line is stored at ad-
003D BO 80 MOV AL,80H dresses 40H-67H for this display. In the four-line displays, the first line is at OOH, the second is
003F EE OUT DX, AL
DX,PORTA ;data to port A
at 40H, the third is at 14H, and the last line is at 54H. The largest display device that uses the
0040 BA 0300 MOV
0043 8A C3 MOV AL , BL HD44780 is a two-line x 40-character display. The four-line by 40-character display uses an
0045 EE ' OUT DX,AL M50530 or a pair of HD44780s. Because information on these devices can be readily found on
0046 BA 0301 MOV DX,PORTB the Internet, they are not covered in the text.
0049 BO 02 MOV AL,2 R/W# - 0,
004B EE . OUT DX,AL A Stepper Motor Interfaced to the 82C55. Another device often interfaced to a computer system
004C 90 NOP
004D 90 NOP is the stepper motor. A stepper motor is a digital motor because it is moved in discrete steps as it
004E BO 06 MOV AL, 6 ;RS = 1, R/W# = E = 1 traverses through 360°. A common stepper motor is geared to move perhaps 15° per step in an
0050 EE OUT DX,AL inexpensive stepper motor, to 1° per step in a more costly high-precision stepper motor. In all
0051 90 NOP
0052 90 NOP cases, these steps are gained through many magnetic poles and/or gearing. Notice that two coils
0053 BO 00 MOV AL,0 are energized in Figure 11-22. If less power is required, one coil may be energized at a time,
0055 EE OUT DX,AL causing the motor to step at 45°, 135°, 225°, and 315°.
0056 E8 FFB7 CALL BUSY ;wait for LCD
0059 C3 RET Figure 11-22 shows a four-coil stepper motor that uses an armature with a single pole. No-
005A WRITE ENDP tice that the stepper motor is shown four times with the armature (permanent magnetic) rotated


FIGURE 11 -22 The stepper Motor stepper

motor showing full-step
operation, (a) 45° (b) 135°
PAD
(c) 225° (d) 315°. PA1
PA2
PAS
PA4
PAS
PA6
PA7

PBO
PB1
PB2
PB3
PB4
PB5

PCO
PC1
PC2
PCS
PC4
PCS
PC6
PC7 BE
Note: * = active low

FIGURE 11-23 A stepper motor interfaced to the 82C55. This illustration does not show the
decoder.

0012 E8 0011 CALL DELAY wait one millisecond
0015 E2 F7 LOOP STEPl repeat until CX = 0
0017 EB 09 JMP STEP 0
0019 RH:
0019 81 El 7FFF AND CX,7FFFH clear bit 15
001D RH1:
001D DO C8 ROR AL 7 1 step right
to four discrete places. This is accomplished by energizing the coils, as shown. This is an illus- 001F E6 40 OUT PORT,AL
tration of full stepping. The stepper motor is driven by using NPN Darlington amplifier pairs to 0021 E8 0006 CALL DELAY wait one millisecond
0024 E2 F7 LOOP RH1 repeat until CX = 0
provide a large current to each coil. 0026 STEP_OUT:
A circuit that can drive this stepper motor is illustrated in Figure 11-23, with the four coils 0026 A2 0000 MOV POS,AL ;save position
shown in place. This circuit uses the 82C55 to provide it with the drive signals that are used to 0029 C3 RET
rotate the armature of the motor in either the right-hand or left-hand direction. 0029 STEP ENDP
A simple procedure that drives the motor (assuming that port A is programmed in mode 0
as an output device) is listed in Example 11-14. This subroutine is called, with CX holding the The current position is stored in memory location POS, which must be initialized with
number of steps and direction of the rotation. If CX > 8000H, the motor spins in the right-hand 33H, 66H, OCCH, or 99H. This allows a simple ROR (step right) or ROL (step left) instruction
direction; if CX < 8000H, it spins in the left-hand direction. The leftmost bit of CX is removed to rotate the binary bit pattern for the next step.
and the remaining 15 bits contain the number of steps. Notice that the procedure uses a time Stepper motors can also be operated in the half-step mode, which allows eight steps per se-
delay (not illustrated) that causes a 1 ms time delay. This time delay is required to allow the quence. This is accomplished by using the full-step sequence described with a half step obtained
stepper-motor armature time to move to its next position. by energizing one coil interspersed between the full steps. Half-stepping allows the armature to be
positioned at 0°, 90°, 180°, and 270°. The half-step position codes are 11H, 22H, 44H, and 88H.
EXAMPLE 11-14
A complete sequence of eight steps would follow as: 11H, 33H, 22H, 66H, 44H, OCCH, 88H, and
= 0040 PORT EQU 40H ;assign Port A 99H. This sequence could be either output from a lookup table or generated with software.
;A procedure to control stepper motor. Key Matrix Interface. Keyboards come in a vast variety of sizes, from the standard 101-key
0000 STEP PROC NEAR QWERTY keyboards interfaced to the microprocessor to small specialized keyboards that may
contain only four to 16 keys. This section of the text concentrates on the smaller keyboards that
AO 0000 R MOV AL,POS ;get position
0000 may be purchased preassembled or may be constructed from individual key switches.
0003 81 F9 8000 CMP CX,8000H
0007 77 10 JA RH ;if right-hand direction Figure 11-24 illustrates a small key-matrix that contains 16 switches interfaced to ports A
0009 83 F9 00 CMP CX, 0 and B of an 82C55. In this example, the switches are formed into a 4 x 4 matrix, but any matrix
74 14 JE STEP_OUT ;if no steps
OOOC could be used such as a 2 x 8. Notice how the keys are organized into four rows (ROWO-ROW3)
OOOE STEPl:
OOOE DO CO ROL AL, 1 ;step left and four columns (COLO-COL3). Each row is connected to 5.0 V through a 10 K£J pull-up re-
0010 E6 40 OUT PORT,AL sistor to ensure that the row is pulled high when no push-button switch is closed.


The 82C55 is decoded (PAL program is not shown) at I/O ports 50H-53H for an 8088 mi-
croprocessor. Port A is programmed as an input port to read the rows and port B is programmed
as an output port to select a column. For example, if 1110 is output to port B pins PB3-PBO,
column 0 has a logic 1, so the four keys in column 0 are selected. Notice that with a logic 0 on
PBO, the only switches that can place a logic 0 onto port A are switches 0-3. If switches 4-F are

d" closed, the corresponding port A pins remain a logic 1. Likewise, if a 1101 is output to port B,
switches 4-7 are selected, and so forth.
A flowchart of the software required to read a key from the keyboard matrix and de-
bounce the key is illustrated in Figure 11-25. Keys must be de-bounced, which is normally ac-
complished with a short time delay of from 10-20 ms. The flowchart contains three main
sections. The first waits for the release of a key. This seems awkward, but software executes very
quickly in a microprocessor and there is a possibility that the program will return to the top of

t l this program before the key is released, so we must wait for a release first. Next, the flowchart

FIGURE 11-25 The flow-
chart of a keyboard-scanning
procedure.

Wait for release

1L

Sea

......... Wait for keystroke
Time
forde

E
•2 Sea

/Ch
If key open

412

004F
shows that we wait for a keystroke. Once the keystroke is detected, the position of the key is cal- RET

culated in the final part of the flowchart. 0051 SCAN ENDP
The software uses a procedure called SCAN to scan the keys and another called DELAY
to waste 10 ms of time for de-bouncing. The main keyboard procedure is called KEY and it ap- 0051 DELAY PROC U
NEAR USES CX
pears with the others in Example 11-15. Note that the SCAN procedure is generic, so it can 0052 B9 1388 MOV CX,500 ;10ms (8MHz clock)
handle any keyboard configuration from a 2 x 2 matrix to an 8 x 8 matrix. Changing the two 0055 DELAY1 :
equates at the start of the program (ROW and COL) will change the configuration of the soft- 0055 E2 FE LOOP DELAYl
RET
ware for any size keyboard. Also note that the steps required to initialize the 82C55 so that port
A is an input port and port B is an output port are not shown. 0059 DELAY ENDP

A note about the SCAN procedure. The time between where the keyboard column is se-
EXAMPLE 11-15
lected and where the rows are read is very short. In a very high-speed system, a small time delay
;A keyboard procedure that scans the keyboard and
;returns with the numeric code of the key in AL.
must be placed between these two points for the data at port A to settle to its final state. In most
cases, this is not needed—the SCAN procedure should not scan the display at a rate higher than
= 0004 ROWS EQU 4 ; number of rows 30 KHz. If it does, the Federal Communications Commission (FCC) will not approve its appli-
= 0004 COLS EQU 4 ; number of columns
;port A address
cation in any accepted system.
= 0050 PORTA EQU 5 OH
= 0051 PORTB EQU 51H ;port B address

KEY PROC NEAR USES CX
Mode 1 Strobed Input
0000

;test all keys
Mode 1 operation causes port A and/or port B to function as latching input devices. This allows
0001 E8 002F CALL SCAN
0004 75 FA JNZ KEY ;if key closed external data to be stored into the port until the microprocessor is ready to retrieve it. Port C is
0006 E8 0048 CALL DELAY ; wait for about 10 ms also used in mode 1 operation—not for data, but for control or handshaking signals that help op-
0009 E8 0027 CALL SCAN ;test all keys
;if key closed
erate either or both port A and port B as strobed input ports. Figure 11-26 shows how both ports
OOOC 75 F2 JNZ KEY
OOOE KEY1: are structured for mode 1 strobed input operation and the timing diagram.
OOOE E8 0022 CALL SCAN ;test all keys The strobed input port captures data from the port pins when the strobe (STB) is activated.
0011 74 FB JZ KEY1 ;if no key closed
CALL DELAY ;wait for about 10 ms
Note that the strobe captures the port data on the 0-to-1 transition. The STB signal causes data to
0013 E8 003B
0016 E8 001A CALL SCAN ; test all keys be captured in the port and it activates the IBF (input buffer full) and INTR (interrupt request)
0019 74 F3 JZ KEY! ; if no key closed signals. Once the microprocessor, through software (IBF) or hardware (INTR), notices that data
001B 50 PUSH AX ; save row codes
MOV AL,COLS ; calculate starting row key are strobed into the port, it executes an IN instruction to read the port (RD). The act of reading
001C BO 04
001E 2A Cl SUB AL,CL the port restores both IBF and INTR to their inactive states until the next datum is strobed into
0020 B5 04 MOV CH,ROWS the port.
0022 F6 E5 MUL CH
0024 8A C8 MOV CL,AL
0026 FE C9 DEC CL Signal Definitions for Mode 1 Strobed Input
0028 58 POP AX
0029 KEY2: STB The strobe input loads data into the port latch, which holds the information
0029 DO C8 ROR AL,1 ; f ind row position
until it is input to the microprocessor via the IN instruction.
002B FE Cl INC CL
002D 72 FA JC KEY2 IBF Input buffer full is an output indicating that the input latch contains
002F 8A Cl MOV AL,CL ;mode code to AL information.
RET
INTR Interrupt request is an output that requests an interrupt. The INTR pin
0033 KEY ENDP becomes a logic 1 when the STB input returns to a logic 1, and is cleared when
0033 SCAN PROC NEAR USES BX
0034 Bl 04 MOV CL , ROWS ; form row mask the data are input from the port by the microprocessor.
0036 B7 FF MOV BH,OFFH INTE The interrupt enable signal is neither an input nor an output; it is an internal
0038 D2 E7 SHL BH,CL
003A B9 0004 MOV CX,COLS ; load column count bit programmed via the port PC4 (port A) or PC2 (port B) bit position.
003D B3 FE MOV BL, OFEH ,-get selection code
PC7, PC6 The port C pins 7 and 6 are general-purpose I/O pins that are available for any
003F SCAN1:
003F 8A C3 MOV AL,BL ; select column purpose.
0041 E6 51 OUT PORTB , AL
0043 DO C3 ROL BL, 1 Strobed Input Example. An excellent example of a strobed input device is a keyboard. The key-
0045 E4 50 IN AL , PORTA ; read rows
board encoder de-bounces the key-switches, and provides a strobe signal whenever a key is de-
0047 OA C7 OR AL , BH
0049 3C FF CMP AL,OFFH ;test for a key pressed and the data output contain the ASCII-coded key code. Figure 11-27 illustrates a
004B 75 02 JNZ SCAN2 keyboard connected to strobed input port A. Here DAY (data available) is activated for 1.0 jis
004D E2 FO LOOP SCAN1

Model Port B each time that a key is typed on the keyboard. This causes data to be strobed into port A because
Mode 1 Port A
DAV is connected to the STB input of port A. Each time a key is typed, therefore, it is stored into
Port A port A of the 82C55. The STB input also activates the IBF signal, indicating that data are in port A.
Example 11-16 shows a procedure that reads data from the keyboard each time a key is
typed. This procedure reads the key from port A and returns with the ASCII code in AL. To de-
1— —— i
illsJTE: tect a key, port C is read and the IBF bit (bit position PCS) is tested to see whether the buffer is
PC4 STB

U
!
i_ full. If the buffer is empty (IBF = 0), then the procedure keeps testing this bit, waiting for a char-
PCS IBF acter to be typed on the keyboard.

EXAMPLE 11-16

LL INTR ;A procedure that reads the keyboard encoder
PC3 INTR ;and returns the ASCII character in AL.
P( 26+1 I/O
= 0020 BIT5 EQU 20H
= 0022 PORTC EQU 22H
= 0020 PORTA EQU 20H

0000 READ PROC NEAR
STB 0000 E4 22 IN AL , PORTC ; read Port C
0002 A8 20 TEST AL,BIT5 ;test IBF
0004 74 FA JZ READ ;if IBF = 0
(Buffer full) 0006 E4 20 IN AL , PORTA ; read data
0008 C3 RET

INTR (Interrupt requested) 0009 READ ENDP

RD
Mode 1 Strobed Output
Figure 11-28 illustrates the internal configuration and timing diagram of the 82C55 when it is
Port .———-/" operated as a strobed output device under mode 1. Strobed output operation is similar to mode 0
output operation, except that control signals are included to provide handshaking. __
Data read by microprocessor Whenever data are written to a port programmed as a strobed output port, the OBF (output
Data strobed into port
buffer full) signal becomes a logic 0 to indicate that data are present in the port latch. This signal
(b) indicates that data are available to an external I/O device that removes the data by strobing the
ACK (acknowledge) input to the port. The ACK signal returns the OBF signal to a logic 1, indi-
FIGURE 11-26 Strobed input operation (mode 1) of the 82C55. (a) Internal structure, and cating that the buffer is not full.
(b) timing diagram.
Signal Definitions for Mode 1 Strobed Output
OBF Output buffer full is an output that goes low whenever data are output (OUT)
FIGURE 11-27 Using the Keyboard to the port A or port B latch. This signal is set to a logic 1 whenever the ACK
82C55 for strobed input pulse returns from the external device.
operation of a keyboard. Do
PA,, ACK The acknowledge signal causes the OBF pin to return to a logic 1 level. The

t
PA 7
(
—— _ ——
ASCII
t
D7
INTR
ACK is a response from an external device, indicating that it has received the
data from the 82C55 port.
Interrupt request is a signal that often interrupts the microprocessor when the
external device receives the data via the ACK signal. This pin is qualified by
the internal INTE (interrupt enable) bit.
STB
PC4
DAV INTE Interrupt enable is neither an input nor an output; it is an internal bit
programmed to enable or disable the INTR pin. The INTE A bit is programmed
as PC6 and INTE B is programmed as PC2.
PCS, PC4 Port C pins 5 and 4 are general-purpose I/O pins. The bit set and reset
82C55
command may be used to set or reset these two pins.

Mode 1 Port A Mode 1 Port B FIGURE 11-29 The82C55
connected to a parallel printer 82C55 Printer
interface that illustrates the
strobed output mode of oper- PB« DO
ation for the 82C55.
!
PB7
ASCII
V t
D7

ACK
PC, A.V_R

INTR
PC4 DS

(a)

= 0061 PORTB EQU 61H
- 0063 CMD EQU 63H

0000 PRINT PROC NEAR

;check printer ready
0000 E4 62 IN AL,PORTC ;get OBF
0002 A8 02 TEST AL,BIT1 ;test OBF
0004 74 FA JZ PRINT ;i f OBF = 0

;send character to printer
0006 8A C4 MOV AL,AH ;get data
0008 E6 61 OUT PORTB,AL ;print data
Data sent to port Data removed from port
;send data strobe to printer
(b) OOOA BO 08 MOV AL,8 ;clear DS
OOOC E6 63 OUT CMD,AL
FIGURE 11-28 Strobed output operation (mode 1) of the 82C55. (a) Internal structure, and OOOE BO 09 MOV AL,9 ;set DS
(b) timing diagram. 0010 E6 63 OUT CMD,AL
0012 C3 RET

Strobed Output Example. The printer interface discussed in Section 11-1 is used here to 0013 PRINT ENDP
demonstrate how to achieve strobed output synchronization between the printer and the 82C55.
Figure 11-29 illustrates port Reconnected to a parallel printer, with eight data inputs for re- Mode 2 Bi-directional Operation
ceiving ASCII-coded data, a DS (data strobe) input to strobe data into the printer, and an
In mode 2, which is allowed with group A only, port A becomes bi-directional, allowing data to
ACK output to acknowledge the receipt of the ASCII character.
be transmitted and received over the same eight wires. Bi-directional bused data are useful when
In this circuit, there is no signal to generate the DS signal to the printer, so PC4 is used
interfacing two computers. It is also used for the IEEE-488 parallel high-speed GPIB (general
with software that generates the DS signal. The ACK signal that is returned from the printer ac-
purpose instrumentation bus) interface standard. Figure 11-30 shows the internal structure
knowledges the receipt of the data and is connected to the ACK input of the 82C55. and timing diagram for mode 2 bi-directional operation.
Example 11-17 lists the software that sends the ASCII-coded character in AH to the printer.
The procedure first tests OBF to decide whether the printer has removed the data from port B. If Signal Definitions for Bi-directional Mode 2
not, the procedure waits for the ACK signal to return from the printer. If OBF = 1, then the proce-
dure sends the contents of AH to the printer through port B and also sends the DS signal. INTR Interrupt request is an output used to interrupt the microprocessor
for both input and output conditions.
EXAMPLE 11-17 OBF Output buffer full is an output indicating that the output buffer
;A procedure that transfers the ASCII character contains data for the bi-directional bus.
;from AH to the printer via port B. ACK Acknowledge is an input that enables the three-state buffers so that
BIT1 EQU 2 data can appear on port A. If ACK is a logic 1, the output buffers of
PORTC EQU 62H port A are at their high-impedance state.

Bi-directional mode 2
the OUT instruction. The external circuitry also monitors the OBF signal to decide whether the
microprocessor has sent data to the bus. As soon as the output circuitry sees a logic 0 on OBF, it
sends back the ACK signal to remove it from the output buffer. The ACK signal sets the OBF bit
and enables the three-state output buffers so that data may be read. Example 11-18 lists a proce-
dure that transmits the contents of the AH register through bi-directional port A.

EXAMPLE 11-18

;A procedure that transmits AH through the bi-
directional bus of port A.
= 0080 BIT7 EQU 8OH
= 0062 PORTC EQU 62H
= 0060 PORTA EQU 6OH
0000 TRANS PROC NEAR
0000 E4 62 IN AL,PORTC ;get OBF
0002 A8 80 TEST AL,BIT7 ;test OBF
0004 74 FA JZ TRANS ;if OBF = 1
0006 8A C4 MOV AL,AH ;get data
(a) 0008 E6 60 OUT PORTA,AL ;send data
OOOA C3 RET

OOOB TRANS ENDP
WR > ——^_/

fQtt v_ / To receive data through the bi-directional port A bus, the IBF bit is tested with software to
decide whether data have been strobed into the port. If IBF = 1, then data are input using the IN
INTR X /
instruction. The external interface sends data into the port by using the STB signal. When STB is
activated, the IBF signal becomes a logic 1 and the data at port A are held inside the port in a
ACK ——— / latch. When the IN instruction executes, the IBF bit is cleared and the data in the port are moved
STB ~~ —— / ' into AL. Example 11-19 lists a procedure that reads data from the port.
IBF / EXAMPLE 11-19
/
Port A . . . . . ... --/~~
... ..
>----------< >-------- ;A procedure that reads data from the bi-
directional port A and returns it in AL.
1 / = 0020 BIT5 EQU 2 OH
RD Data read from port A~~l = 0062 PORTC EQU 62H
Data store d in port A Data input (IN) from port A = 0060 PORTA EQU 6OH
Data output (OUT) to port A
0000 READ PROC NEAR
FIGURE 11-30 Mode 2 operation of the 82C55. (a) Internal structure, and (b) timing diagram.
0000 E4 62 IN AL,PORTC ;get IBF
0002 A8 20 TEST AL,BIT5 ;test IBF
0004 74 FA JZ READ ;if IBF = 0
STB The strobe input loads the port A input latch with external data from 0006 E4 60 IN AL,PORTA ;get data
the bi-directional port A bus. 0008 C3 RET

IBF Input buffer full is an output used to signal that the input buffer 0009 READ ENDP
contains data for the external bi-directional bus.
INTE Interrupt enable are internal bits (INTE1 and INTE2) that enable The INTR (interrupt request) pin can be activated from both directions of data flow
the INTR pin. The state of the INTR pin is controlled through port C through the bus. If INTR is enabled by both INTE bits, then the output and input_b3uffers both
bits PC6 (INTE1) and PC4 (INTE2). cause interrupt requests. This occurs when data are strobed into the buffer using STB or when
data are written using OUT.
PC2, PCI, and PCO These pins are general-purpose I/O pins in mode 2 controlled by the
bit set and reset command.
82C55 Mode Summary
The Bi-directional Bus. The bi-directional bus is used by referencing port A with the IN and OUT
instructions. To transmit data through the bi-directional bus, the program first tests the OBF signal Figure 11-31 shows a graphical summary of the three modes of operation for the 82C55. Mode
to determine whether the output buffer is empty. If it is, then data are sent to the output buffer via 0 provides simple I/O, mode 1 provides strobed I/O, and mode 2 provides bi-directional I/O. As
mentioned, these modes are selected through the command register of the 82C55.

11-4 THE 8279 PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE 423
422

FIGURE 11-31 A summary ModeO Mode 1 Mode 2 Pin Definitions for the 8279
of the port connections for the AO The AO address input selects data or control for reads and writes
82C55 PIA.
between the microprocessor and the 8279. A logic 0 selects data and a
logic 1 selects control or status register.
BD Blank is an output used to blank the displays.
CLK Clock is an input that generates the internal timing for the 8279. The
PortC maximum allowable frequency on the CLK pin is 3.125 MHz for the
8279-5 and 2.0 MHz for the 8279. Other timings require wait states in
microprocessors executing at above 5 MHz.
CN/ST Control/strobe is an input normally connected to the Control key on a
keyboard.
cs Chip select is an input that enables the 8279 for programming, reading
the keyboard and status information, and writing control and display
data.
11-4 THE 8279 PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE DB7-DBO The data bus consists of bi-directional pins that connect to the data bus
on the microprocessor.
The 8279 is a programmable keyboard and display interfacing component that scans and en- IRQ Interrupt request is an output that becomes a logic 1 whenever a key
codes up to a 64-key keyboard and controls up to a 16-digit numerical display. The keyboard in- is pressed on the keyboard. This signal indicates that keyboard data are
terface has a built-in first-in, first-out (FIFO) buffer that allows it to store up to eight keystrokes available for the microprocessor.
before the microprocessor must retrieve a character. The display section controls up to 16 nu- OUTA3-OUTAO Outputs that send data to the displays (most-significant).
meric displays from an internal 16x8 RAM that stores the coded display information.
OUTB3-OUTBO Outputs that send data to the displays (least-significant).
Basic Description of the 8279 RD The read input is directly connected to the IORC or RD signal from the
system. The RD input causes, when CS is a logic 0, a read from the
As we shall see, the 8279 is designed to easily interface with any microprocessor. Figure 11-32
data registers or status register.
illustrates the pin-out of this device. The definition of each pin connection follows.
RESET The reset input connects to the system RESET signal.
RL7-RLO Return lines are inputs used to sense any key depression in the
LOGIC SYMBOL
PIN CONFIGURATION keyboard matrix.
1 ^^ 40 DVcc
SHIFT The shift input normally connects to the Shift key on a keyboard.
HL 2 C
PIN N/! ^-)
RL3C 2 39 DRM
RL
^ _______ IRQ HI-07 SL3-SLO The scan line outputs scan both the keyboard and the displays.
CLKd 3 38 D o
IROC 4
RL4£ 5

RUC
RL 6 C 7
6
37 DCNTL/STB
36 D SHIFT
35 D S L 3
34 DSL 2
CLK
NftME
'oBo;

RESET
•c?
'

'
;
I/O
' I/O ' DA
CL
' Rfc
; CH s
£
K
T
<x>
———— ^
DATA
BUS

RD
SHIFT ___
WR Write is an input that connects to either the write strobe signal that is
developed with external logic. The WR input causes data to be written
to either the data registers or control registers within the 8279.
RD HE INPUT
DSL,
RL7C 33
CNTL'STB
Vcc A power supply pin connected to the system +5.0 V bus.
RES6TII 32 ZISLo ' AO BU E ADDRESS
ER "_
WR
'IRQ IN R
RbC 10
8279
31 POUT BO
'SL03 SC
RRUPTREQUEST OUTPUT"
LINES Vss A ground pin connected to the system ground.
wfiC 11 30 DOUT B, 'RL0; ' RE RW LINES

29 D OUT B 2 'SHIFT ' SHifT INPUT [
4 ^

_
12 «
"CNTL'STB ' '_ CONTROL/STROBE INPUT
CONTP [

£!! 1 28 DOUT B 3
DOUT AO
'OUT AOS
'OUT BO 3 '
o Sf.t Y (Al OUTPUTS
DISPL V IB) OUTPUTS
Interfacing the 8279 to the Microprocessor
DB^C 1 27 *0
SB ; "['BLANK DISPLAY OUTPUT
DOUT A,
] 26
OUT AO 3
—:—^
4 y In Figure 11-33, the 8279 is connected to the 8088 microprocessor. The 8279 is decoded to func-
DB 4 C 25 DOUT A Z
DBaC 1 24 D OUT A 3
RESET
tion at 8-bit I/O address 10H and 11H, where port 10H is the data port and 11H is the control
DBeC 1 23
4 >
port. This circuit uses a PAL16L8 (see Example 11-20) to decode the I/O address for the 8279.
CLK OUTBoa
1 22 DCS
DB7EI
Address bus bit AO selects either the data or control port. Notice that the CS signal selects the
VssC 20 21 IK BD
8279 and also provides a signal called WAIT2 that is used to cause two wait states so that this
1
device can function with an 8 MHz 8088.
The only signal not connected to the microprocessor is the IRQ output. This is an interrupt
FIGURE 11-32 The pin-out and logic symbol of the 8279 programmable keyboard/display interface.
request pin and is beyond the scope of this section of the text. Chapter 12 explains interrupts and
where they operate and function in a system.
(Courtesy of Intel Corporation.)

11-4 THE 8279 PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE 425
64-key matrix
FIGURE 11-33 The 8279 nn 12 U2
DBO RLO ~39~
interfaced to the 8088 micro- D1 13 DB1 RL1 1 nn 12
DBO RLO
D2 14 DB2 RL2 D1 13
processor to function at 8-bit D3 15 DBS RL3
~2~
D2 '4
DB1
DB2
RL1
RL2 1
D4 16 DB4 RL4 D3 15
I/O ports 10H and 11H. D5 17 DBS RL5
DBS RL3
-1 ————— -
D6
D7
18
19
DB6 RL6 =| D5 17
DB4
DBS
RL4
RL5 6
DB7 RL7 D6 18 7
DB6 RL6
D7 '9 8
RD 10 RD SHFT DB7 RL7
WR CN/ST RD 10
RD SHFT
WR
WA,TP < CS BD WR CN/ST
3.0 MHz ^
RESET
1 CLK
RESET SLO
WAIT2 -< ——————————————————— • — — —— £f-
3.0 MHz ————————————————————————————— g- CLK
CS BD 1 1111 1
21 5 4321 0 9 7
An AO
IRQ
SL1
SL2 I RESET ————————————————————————————— J- RESET
AO ———————
SLO 32 O O O O O Cj o o
U3
SL3
AO
IRQ
SL1
SL2
^— YY YY Y YY Y
0 1 234567 74ALS138
27 SL3 35
U1 OAO
A1 _____ T_ 11 ^19 ____ OA1 U1 27 GG
O1 OAO -26~
12 O2 OA2 A1 _____ 1_ G22
11 O1 OA1 AB C 1 AB
IS 03 OA3
OBO
12 O2 OA2
f
14
IS
16
04
05
O6
t OB1
OB2
13
14
15
O3
O4
O5
OA3
OBO
OB1
1 2 3 TT
OB3 "hi" R1
17 O7 16 O6
IO/M 9
18
19
O8
8279 17 O7 1 OB2
OB3 I 10K
IO/M ~9~ 18 O8
~
110 19 8279
110

FIGURE 11-34 A 64-key keyboard interfaced to the 8088 microprocessor through the 8279.
EXAMPLE 11-20
TITLE Address Decoder
PATTERN Test 14 in this example) select one of the eight different control words. Table 11-4 lists all eight control
REVISION A
words and briefly describes them.
COMPANY BreyCo
DATE 7/10/99 Control Word Descriptions. Following is a list of the control words that program the 8279. Note
CHIP DECODERE PAL16L8 that the first three bits are the control register number from Table 11-4, which are followed by
other binary bits of information as they apply to each control.
;pins 1 2 3 4 5 6 7 8 9 10
Al A2 A3 A4 A5 A6 A7 NC IOM GND OOODDMMM Mode set is a command with an opcode of 000 and two fields programmed
;pins 11 12 13 14 15 16 17 18 19 20 to select the mode of operation for the 8279. The DD field selects the mode
NC NC NC NC NC NC NC NC CS VCC of operation for the displays (see Table 11-5), and the MMM field selects
the mode of operation for the keyboard (see Table 11-6).
EQUATIONS
/CS = /A7 * /A6 * /A5 /A3 /A2 * /Al
TABLE 11-4 The 8279 control word summary.

Keyboard Interface D7 D6 D5 Function Purpose
Suppose that a 64-key keyboard (with no numeric displays) is connected through the 8279 to the
8088 microprocessor. Figure 11-34 shows this connection, as well as the keyboard. With the
0 0 0 Mode set Selects the number of display positions, left
or right entry, and type of keyboard scan
8279, the keyboard matrix is any size from a 2 x 2 matrix (four keys) to an 8 x 8 matrix (64
keys). (Note that each crossover point in the matrix contains a normally open push-button switch 0 0 1 Clock Programs the internal clock and sets the
that connects one vertical column with one horizontal row when a key is pressed.) scan and de-bounce times
The I/O port number decoded is the same as that decoded for Figure 11-33. The I/O port 0 1 0 Read FIFO Selects the type of FIFO read and the ad-
number is 10H for the data port and 11H for the control port in this circuit. dress of the read
The 74ALS138 decoder generates eight active low column strobe signals for the keyboard. 0 1 1 Read display Selects the type of display read and the ad-
The selection pins SL2-SLO sequentially scan each column of the keyboard, and the internal cir- dress of the read
cuitry of the 8279 scans the RL pins, searching for a key switch closure. Pull-up resisters, nor- 1 0 0 Write display Selects the type of write and the address of
mally found on input lines of a keyboard, are not required because the 8279 contains its own the write
internal pull-ups on the RL inputs. 1 0 1 Display write inhibit Allows half-bytes to be blanked
Programming the Keyboard Interface. Before any keystroke is detected, the 8279 must be pro- 1 1 0 Clear Clears the display or FIFO
grammed—a more involved procedure than with the 82C55. The 8279 has eight control words to 1 1 1 End interrupt Clears the IRQ signal to the microprocessor
consider before it is programmed. The first three bits of the number sent to the control port (11H,

426 CHAPTER 11 BASIC I/O INTERFACE 11-4 THE 8279 PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE 427

TABLE 11-5 Binary bit as- 1010WWBB The display write inhibit control word inhibits writing to either half of
signment for DD of the mode DD Function each display RAM location. The leftmost W inhibits writing to the leftmost
set control word. four bits of the display RAM location, and the rightmost W inhibits the
00 8-digit display with left entry
01 16-digit display with left entry rightmost four bits. The BB field functions in a like manner, except that
10 8-digit display with right entry they blank (turn off) either half of the output pins.
11 16-digit display with right entry 1100CCFA The clear control word clears the display, the FIFO, or both the display and
FIFO. Bit F clears the FIFO and the display RAM status, and sets the
address pointer to 000. If the CC bits are 00 or 01, all of the display RAM
locations become 0000000; if CC = 10, all locations become 00100000; and
TABLE 11-6 Binary bit as-
MMM if CC = 11, all locations become 11111111.
signment for MMM of the
mode set control word. 111EOOO The end of interrupt control word is issued to clear the IRQ pin to zero in the
000 Encoded keyboard with 2-key lockout sensor matrix mode. If E is a 1, the special error mode is used. In the special
001 Decoded keyboard with 2-key lockout error mode, the status register indicates if multiple key closures have occurred.
010 Encoded keyboard with N-key rollover
011 Decoded keyboard with N-key rollover The large number of control words make programming the keyboard interface appear com-
100 Encoded sensor matrix plex. Before anything is programmed, the clock divider rate must be determined. In the circuit il-
101 Decoded sensor matrix lustrated in Figure 11-34, we use a 3.0 MHz clock input signal. To program the prescaler to
110 Strobed keyboard, encoded display scan generate a 100 KHz internal rate, we program PPPPP of the clock control word with a 30 or 111102.
111 Strobed keyboard, decoded display scan The next step involves programming the keyboard type. The example keyboard in Figure
11-34 is an encoded keyboard. Notice that the circuit includes an external decoder that converts
the encoded data from the SL pins into decoded column-selection signals. We are free in this ex-
The DD field selects either an 8- or 16-digit display, and determines whether new data are ample to choose either 2-key lockout or N-key rollover, but most applications use 2-key lockout.
entered to the rightmost or leftmost display position. The MMM field is quite a bit more com- Finally, we program the operation of the FIFO. Once the FIFO is programmed, it never needs
plex: it provides encoded, decoded, or strobed keyboard operation. to be reprogrammed unless we need to read prior keyboard codes. Each time a key is typed, the data
In encoded mode, the SL outputs are active-high, and follow the binary bit pattern 0 are stored in the FIFO; if they are read from the FIFO before the FIFO is full (eight characters), the
through 7 or 0 through 15, depending whether 8- or 16-digit displays are selected. In decoded data from the FIFO follows the same order as the typed data. Example 11-21 provides the software
mode, the SL outputs are active-low, and only one of the four outputs is low at any given instant. required to initialize the 8279 to control the keyboard illustrated in Figure 11-34.
The decoded outputs repeat the pattern: 1110,1101,1011, and 0111. In strobed mode, an active- EXAMPLE 11-21
high pulse on the CN/ST input pin strobes data from the RL pins into an internal FIFO, where
they are held for the microprocessor. /Initialization dialog for the keyboard interface
;of Figure. 11-34.
It is also possible to select either 2-key lockout or N-key rollover. 2-key lockout prevents
two keys from being recognized, if pressed simultaneously. N-key rollover will accept all keys 0000 BO 3E MOV AL,00111110B ;program clock
0002 E6 11 OUT 11H,AL
pressed simultaneously, from first to last.
001PPPPP The clock command word programs the internal clock divider. The code 0004 BO 00 MOV AL,0
PPPPP is a prescaler that divides the clock input pin (CLK) to achieve the 0006 E6 11 OUT 11H,AL ;program mode
desired operating frequency of approximately 100 KHz. An input clock of 0008 BO 50 MOV AL,01010000B
1 MHz thus requires a prescaler of 010102 for PPPPP. OOOA E6 11 OUT 11H,AL ;program FIFO
010ZOAAA The read FIFO control word selects the address of a keystroke from the
Once the 8279 is initialized, a procedure is required to read data from the keyboard. We
internal FIFO buffer. Bit positions AAA select the desired FIFO location determine whether a character is typed in the keyboard by looking at the FIFO status register.
from 000 to 111, and Z selects auto-increment for the address. Under Whenever the control port is addressed by the IN instruction, the contents of the FIFO status
normal operation, this control word is used only with the sensor matrix word is copied into the AL register. Figure 11-35 shows the contents of the FIFO status register
operation of the 8279. and defines the purpose of each status bit.
011ZAAAA The display read control word selects the read address of one of the display The procedure listed in Example 11-22 first tests the FIFO status register to see whether it
RAM positions for reading through the data port. AAAA is the address of contains any data. If NNN = 000, the FIFO is empty. Upon determining that the FIFO is not
the position to be read and Z selects auto-increment mode. This command is empty, the procedure inputs data to AL and returns with the keyboard code in AL.
used if the information stored in the display RAM must be read.
EXAMPLE 11-22
100ZAAAA The write display control word selects the write address of one of the
displays. AAAA addresses the position to be written to through the data ;A procedure that reads data from the FIFO and
;returns it in AL.
port, and Z selects auto-increment so subsequent writes through the data
port are to subsequent display positions. MASKS EQU

428 CHAPTER 11 BASIC I/O INTERFACE 11-5 8254 PROGRAMMABLE INTERVAL TIMER 429
FIGURE 11-35 The 8279-5 7 6 5 4 3 2 1 0
FIFO status register.
D S/E 0 u F N N N

L
- Bits that indicate the number of characters in the FIFO
- Indicates the FIFO is full
- Indicates the FIFO has been read while empty
- Indicates the FIFO is full and has been overrun
- Indicates multiple key closures
- Display unavailable because of clear command

0000 READ PROC NEAR

0000 E4 11 IN AL,11H ;read status FIGURE 11-37 A 6-digit numeric display interfaced to the 8279.
0002 A8 07 TEST AL,MASKS ;test NNN
0004 74 FA JZ READ ;if NNN = 0
0006 E4 10 IN AL,10H ;read FIFO data EXAMPLE 11-23
0008 C3 RET
/Initialization dialog for the 6-digit display of
0009 READ ENDP ;Figure 11-37.

0000 BO 3E MOV AL,00111110B ;program clock
The data found in AL upon returning from the subroutine contains raw data from the key- 0002 E6 21 OUT 21H,AL
board. Figure 11-36 shows the format of this data for both the scanned and strobed modes of op- 0004 BO 00 MOV AL, 0 ;program mode set
eration. The scanned code is returned from our keyboard interface and is converted to ASCII 0006 E6 21 OUT 21H,AL
code by using the XLAT instruction with an ASCII code lookup table. The scanned code is re-
turned with the row and column number occupying the rightmost six bits. 0008 BO Cl MOV AL,11000001B ;clear display
OOOA E6 21 OUT 21H,AL
The SH bit shows the state of the shift pin and the CT bit shows the state of the control pin.
In the strobed mode, the contents of the eight RL inputs appear as they are sampled by placing a
Example 11-24 lists a procedure for displaying information on the displays. Data are
logic 1 on the strobe input pin to the 8279.
transferred to the procedure through the AX register. AH contains the 7-segment display code
and AL contains the address of the displayed digit.
Six-Digit Display Interface
Figure 11-37 depicts the 8279 connected to the 8088 microprocessor and a 6-digit numeric dis- EXAMPLE 11-24
play. This interface uses a PAL16L8 (program not shown) to decode the 8279 at I/O ports 20H ;A procedure that displays AH on the display
(data) and 21H (control/status). The segment data are supplied to the displays through the OUTA ;position addressed by AL.
and OUTB pins of the 8279. These bits are buffered by a segment driver (ULN2003A) to drive
MASKS EQU 8OH
the segment inputs to the display.
A 74ALS138 3-to-8 line decoder enables the anode switches of each display position. The DISP PROC NEAR
SL2-SLO pins supply the decoder with the encoded display position from the 8279. Notice that 0000 50 PUSH AX ;save data
the left-hand display is at position 0101 and the right-hand display is at position 0000. These are 0001 OC 80 OR AL,MASKS ;select digit
the addresses of the display positions, as indicated in control words for the 8279. 0003 E6 21 OUT 21H,AL
It is necessary to choose resistor values that allow 60 mA of current flow per segment. In 0005 8A C4 MOV AL,AH ;display data
0007 E6 0 OUT 20H,AL
this circuit, we use 47 Q resisters. If we allow 60 mA of segment current, then the average seg- 0009 58 POP AX ;restore data
ment current is 10 mA, or one-sixth of 60 mA because current only flows for one-sixth of the OOOA C3 RET
time through a segment. The anode switches must supply the current for all seven segments plus OOOB DISP ENDP
the decimal point. Here, the total anode current is 8 x 60 mA, or 480 mA.
Example 11-23 lists the initialization dialog for programming the 8279 to function with
this 6-digit display. This software programs the display and clears the display RAM.

11-5 8254 PROGRAMMABLE INTERVAL TIMER
FIGURE 11-36 The 5 4 3 2 1 0
(a) scanned keyboard code CT SH Scan Return RL7 RL6 RL5 RL4 RL3 RL2 RL1 RLO The 8254 programmable interval timer consists of three independent 16-bit programmable coun-
and (b) strobed keyboard ! I ters (timers). Each counter is capable of counting in binary or binary-coded decimal (BCD). The
code for the 8279-5 FIFO. (a) (b) maximum allowable input frequency to any counter is 10 MHz. This device is useful wherever

11-5 8254 PROGRAMMABLE INTERVAL TIMER 431
the microprocessor must control real-time events. Some examples of usage include real-time
TABLE 11-7 Address A
clock, events counter, and motor speed and direction control.
This timer also appears in the personal computer decoded at ports 40H-43H to do the following:
selection inputs to the 8254. 1 A, Function

0 0 Counter 0
1. Generate a basic timer interrupt that occurs at approximately 18.2 Hz.
2. Cause the DRAM memory system to be refreshed.
0 1 Counter 1
1 0 Counter 2
3. Provide a timing source to the internal speaker and other devices. The timer in the personal 1 1 Control word
computer is an 8253 instead of an 8254.

8254 Functional Description
CS Chip select enables the 8254 for programming, and reading or writing a counter.
Figure 11-38 shows the pin-out of the 8254, which is a higher-speed version of the 8253, and
G The gate input controls the operation of the counter in some modes of operation.
a diagram of one of the three counters. Each timer contains a CLK input, a gate input, and an output
(OUT) connection. The CLK input provides the basic operating frequency to the timer, the gate pin GND Ground connects to the system ground bus.
controls the timer in some modes, and the OUT pin is where we obtain the output of the timer. __ OUT A counter output is where the wave-form generated by the timer is available.
_ The signals that connect to the microprocessor are the data bus pins (D7-DO), RD, WR, RD Read causes data to be read from the 8254 and often connects to the IORC signal.
CS, and address inputs Al and AO. The address inputs are present to select any of the four in-
Vcc Power connects to the +5.0 V power supply.
ternal registers used for programming, reading, or writing to a counter. The personal computer
contains an 8253 timer or its equivalent, decoded at I/O ports 40H^3H. Timer zero is pro- WR Write causes data to be written to the 8254 and often connects to the write strobe
grammed to generate an 18.2 Hz signal that interrupts the microprocessor at interrupt vector 8 (IOWC).
for a clock tick. The tick is often used to time programs and events. Timer 1 is programmed for
15 |is, which is used on the PC/XT personal computer to request a DMA action used to refresh Programming the 8254
the dynamic RAM. Timer 2 is programmed to generate tone on the personal computer speaker. Each counter is individually programmed by writing a control word, followed by the initial
count. Figure 11-39 lists the program control word structure of the 8254. The control word al-
Pin Definitions lows the programmer to select the counter, mode of operation, and type of operation (read/write).
Al, AO The address inputs select one of four internal registers within the 8254. See Table 11-7 The control word also selects either a binary or BCD count. Each counter may be programmed
for the function of the Al and AO address bits. with a count of 1 to FFFFH. A count of 0 is equal to FFFFH+1 (65,536) or 10,000 in BCD.
The minimum count of 1 applies to all modes of operation except modes 2 and 3, which have
CLK The clock input is the timing source for each of the internal counters. This input is
a minimum count of 2. Timer 0 is used in the personal computer with a divide by count of 64K
often connected to the PCLK signal from the microprocessor system bus controller.
(FFFFH) to generate the 18.2 Hz (18.196 Hz) interrupt clock tick. Timer 0 has a clock input
frequency of 4.77 MHz -*- 4 or 1.1925 MHz.
The control word uses the BCD bit to select a BCD count (BCD = 1) or a binary count
(BCD = 0), The M2, Ml, and MO bits select one of the 6 different modes of operation (000-101)
A-K
for the counter. The RW1 and RWO bits determine how the data are read from or written to the
DrC 1 ^"^ 24 DVcc
o.c 2 23 3 w«
DRO FIGURE 11-39 The control
DsC 3 22
04 C 4 21 Dei word for the 8254-2 timer.
DA,
SCI SCO RW1 RWO M2 Ml MO BCD
OsC 5 20
OaL 6 19 3*0
L_J L
" •—' L
8254
DiC 7 18 3 CLK 2

DoC a 17 3 OUT 2
CLKOC 9 18 DO ATE 2 Selects a BCD when a logic 1
OUTOC 10 15 DCLK1 Selects the mode (mode 0 - mode 5)
GATEOE 11 14 D GATE 1
Read/write control
GNDC 12 13 DOUT1
00 = counter latch command
01 = read/write least-significant
byte only
10 = read/write most-significant
byte only
11 = read/write least-significant
byte first, followed by the
most-significant byte
(a) (b) Selects counter
00 = counter 0
FIGURE 11-38 The 8254 programmable interval timer, (a) Internal structure and (b) pin-out. 01 = counter 1
(Courtesy of Intel Corporation.) 10 = counter 2
11 = read-back command

11-5 8254 PROGRAMMABLE INTERVAL TIMER 433

counter. The SCI and SCO bits select a counter or the special read back mode of operation, dis- I N I 1 I 2 I 3 I 4 I 5 I 6 I 7
cussed later in this section. ModeO
Each counter has a program control word used to select the way the counter operates. If CLK
two bytes are programmed into a counter, then the first byte (LSB) will stop the count, and the
OUT
second byte (MSB) will start the counter with the new count. The order of programming is
important for each counter, but programming of different counters may be interleaved for
better control. For example, the control word may be sent to each counter before the counts Model
for individual programming. Example 11-25 shows a few ways to program counter 1 and 2.
The first method programs both control words, then the LSB of the count for each counter,
which stops them from counting. Finally, the MSB portion of the count is programmed
starting both counters with the new count. The second example shows one counter programmed
before the other. Trigger with count of 5

I 2 > < I I > < > < > < >
EXAMPLE 11-25 Mode 2
PROGRAM CONTROL WORD 1 setup counter 1 CLK
PROGRAM CONTROL WORD 2 setup counter 2
stop counter 1 and program LSB OUT I
PROGRAM LSB 1
stop counter 2 and program LSB * Count of 5 loaded
PROGRAM LSB 2
PROGRAM MSB 1 ,program MSB of counter 1 and start it 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3
PROGRAM MSB 2 program MSB of counter 2 and start it
Mode 3
CLK

;setup counter 1
OUT !
PROGRAM CONTROL WORD 1 * Count of 6 loaded
PROGRAM LSB 1 ;stop counter 1 and program LSB
PROGRAM MSB 1 ;program MSB of counter 1 and start it 1 2 3 4 5 6 7
PROGRAM CONTROL WORD 2 ;setup counter 2
;stop counter 2 and program LSB Mode 4
PROGRAM LSB 2
PROGRAM MSB 2 ;program MSB of counter 2 and start it CLK
OUT !
Modes Of Operation. Six modes (mode 0-mode 5) of operation are available to each of the 8254 Trigger with count of 8
counters. Figure 11-40 shows how each of these modes functions with the CLK input, the gate
1 2 3 4 5
(G) control signal, and OUT signal. A description of each mode follows:
Mode5
Mode 0 Allows the 8254 counter to be used as an events counter. In this mode, the output
becomes a logic 0 when the control word is written and remains there until N plus
the number of programmed counts. For example, if a count of 5 is programmed,
the output will remain a logic 0 for 6 counts beginning with N. Note that the gate
Trigger with count of 5
(G) input must be a logic 1 to allow the counter to count. If G becomes a logic 0
in the middle of the count, the counter will stop until G again becomes a logic 1. FIGURE 11-40 The six modes of operation for the 8254-2 programmable interval timer. *The G input stops the
Mode 1 Causes the counter to function as a retriggerable monostable multivibrator (one- count when 0 in modes 2, 3, and 4.
shot). In this mode the G input triggers the counter so that it develops a pulse at
the OUT connection that becomes a logic 0 for the duration of the count. If the Mode 3 Generates a continuous square-wave at the OUT connection, provided that the G
count is 10, then the OUT connection goes low for 10 clocking periods when pin is a logic 1. If the count is even, the output is high for one-half of the count
triggered. If the G input occurs within the duration of the output pulse, the and low for one-half of the count. If the count is odd, the output is high for one
counter is again reloaded with the count and the OUT connection continues for clocking period longer than it is low. For example, if the counter is programmed
the total length of the count. for a count of 5, the output is high for three clocks and low for two clocks.
Mode 2 Allows the counter to generate a series of continuous pulses that are one clock Mode 4 Allows the counter to produce a single pulse at the output. If the count is
pulse wide. The separation between pulses is determined by the count. For programmed as a 10, the output is high for 10 clocking periods and low for one
example, for a count of 10, the output is a logic 1 for nine clock periods and low clocking period. The cycle does not begin until the counter is loaded with its
for one clock period. This cycle is repeated until the counter is programmed with complete count. This mode operates as a software triggered one-shot. As with
a new count or until the G pin is placed at a logic 0 level. The G input must be a modes 2 and 3, this mode also uses the G input to enable the counter. The G input
logic 1 for this mode to generate a continuous series of pulses. must be a logic 1 for the counter to operate for these three modes.

434 CHAPTER 11 BASIC I/O INTERFACE 11-5 8254 PROGRAMMABLE INTERVAL TIMER 435

Mode 5 A hardware triggered one-shot that functions as mode 4, except that it is started 0008 BO 74 MOV AL,01110100B /program counter 1
OOOA EE OUT DX,AL ; for mode 2
by a trigger pulse on the G pin instead of by software. This mode is also similar
to mode 1 because it is retriggerable. OOOB BA 0700 MOV DX,700H ; address counter 0
OOOE BO 50 MOV AL, 80 ; load count of 80
Generating a Wave-form with the 8254. Figure 11-41 shows an 8254 connected to function at I/O 0010 EE OUT DX,AL
ports 0700H, 0702H, 0704H, and 0706H of an 80386SX microprocessor. The addresses are de- 0011 32 CO XOR AL,AL
0013 EE OUT DX,AL
coded by using a PAL16L8 that also generates a write strobe signal for the 8254, which is connected
to the low order data bus connections. The PAL also generates a wait signal for the microprocessor 0014 BA 0702 MOV DX,702H ; address counter 1
that causes two wait states when the 8254 is accessed. The wait state generator connected to the mi- 0017 BO 28 MOV AL,40 ; load count of 40
0019 EE OUT DX,AL
croprocessor actually controls the number of wait states inserted into the timing. The program for 001A 32 CO XOR AL,AL
the PAL is not illustrated here because it is the same as many of the prior examples. 001C EE OUT DX,AL
Example 11-26 lists the program that generates a 100 KHz square-wave at OUTO and a
001D 5A POP DX ; restore registers
200 KHz continuous pulse at OUT1. We use mode 3 for counter 0 and mode 2 for counter 1. The 001E 58 POP AX
count programmed into counter 0 is 80 and the count for counter 1 is 40. These counts generate 001F C3 RET
the desired output frequencies with an 8 MHz input clock.
0020 TIME ENDP

EXAMPLE 11-26 Reading a Counter, Each counter has an internal latch that is read with the read counter port op-
;A procedure that programs the 8254 timer to function eration. These latches will normally follow the count. If the contents of the counter are needed,
;as illustrated in Figure 11-41. then the latch can remember the count by programming the counter latch control word (see
TIME PROC NEAR Figure 11-42), which causes the contents of the counter to be held in a latch until it is read.
Whenever a read from the latch or the counter is programmed, the latch tracks the contents of the
0000 50 PUSH AX counter.
0001 52 PUSH DX
When it is necessary for the contents of more than one counter to be read at the same time,
0002 BA 0706 MOV DX,706H ;address control word we use the read-back control word, illustrated in Figure 11-43. With the read-back control word,
0005 BO 36 MOV AL,00110110B ;program counter 0
;for mode 3
the CNT bit is a logic 0 to cause the countersj>elected by CNTO, CNT1, and CNT2 to be latched.
0007 EE OUT DX,AL
If the status register is to be latched, then the ST bit is placed at a logic 0. Figure 11-44 shows the
status register, which shows the state of the output pin, whether the counter is at its null state (0),
(8 MHz) vcc and how the counter is programmed.

U2 < 10K
nn 8 DO
FIGURE 11-42 The 8254-2 i o
m 7
D2
na i D1
D2 CLKO
Bfe^
counter latch control word.
sci sco o o x x x
04 ——— — D3
D4
GO
OUTO -100 KHz square wave
DR
nfi
r>7
2
1
D5
D6
D7
CLK1
G1
mJ
OUT1 -200 KHz continuous pulses
Rf) 22 RD
CLK2 Select counter
.1
A9
WR
% WR
AO
A1
G2
OUT2 * 00 = counter 0
01 = counter 1
WAIT? ^ OS 10 = counter 2
—— T ——— ^ 11 = read-back command

FIGURE 11-43 The 8254-2
read-back control word.
1 1 CNT ST CNT2CNT1CNTO 0

1 1

selected counters
FIGURE 11-41 The 8254 interfaced to an 8 MHz 8086 so that it generates a 100 KHz square
wave at OUTO and a 200 KHz continuous pulse at OUT1. selected counters


FIGURE 11-44 The 8254-2 7 6 5
status register.
OUT NULL RW1 RWO M2 Ml MO BCD

I 1 1 1

———— Logic 1 for BCD counter

KTT TT T i :f — .._» — :„ n

. . Thf- If>vp1 nf thp OUT nin

DC Motor Speed and Direction Control
One application of the 8254 timer is as a motor speed controller for a DC motor. Figure 11-45
shows the schematic diagram of the motor and its associated driver circuitry. It also illustrates
the interconnection of the 8254, a flip-flop, and the motor and its driver.
The operation of the motor driver circuitry is straightforward. If the Q output of the
74ALS112 is a logic 1, the base Q2 is pulled up to +12 V through the base pull-up resistor, and
the base of Q2 is open circuited. This means that Ql is off and Q2 is on, with ground applied to
the positive lead of the motor. The bases of both Q3 and Q4 are pulled low to ground through the
inverters. This causes Q3 to conduction or turn on and Q4 to turn off, applying ground to the
negative lead of the motor. The logic 1 at the Q output of the flip-flop therefore connects +12 V
to the positive lead of the motor and ground to the negative lead. This connection causes the
motor to spin in its forward direction. If the state of the Q output of the flip-flop becomes a logic
0, then the conditions of the transistors are reversed and +12 V is attached to the negative lead of
the motor, with ground attached to the positive lead. This causes the motor to spin in the reverse
direction.
If the output of the flip-flop is alternated between a logic 1 and 0, the motor spins in either
direction at various speeds. If the duty cycle of the Q output is 50 percent, the motor will not spin
at all and exhibits some holding torque because current flows through it. Figure 11-46 shows
some timing diagrams and their effects on the speed and direction of the motor. Notice how each
counter generates pulses at different positions to vary the duty cycle at the Q output of the flip-
flop. This output is also called pulse width modulation.
To generate these wave forms, counters 0 and 1 are both programmed to divide the input
clock (PCLK) by 30,720. We change the duty cycle of Q by changing the point at which counter
1 is started in relationship to counter 0. This changes the direction and speed of the motor. But
why divide the 8 MHz clock by 30,720? The divide rate of 30,720 is divisible by 256, so we can
develop a short program that allows 256 different speeds. This also produces a basic operating
frequency for the motor of about 260 Hz, which is low enough in frequency to power the motor.
It is important to keep this operating frequency below 1000 Hz, but above 60 Hz.
Example 11-27 lists a procedure that controls the speed and direction of the motor. The o
o
speed is controlled by the value of AH when this procedure is called. Because we have an 8-bit
number to represent speed, a 50 percent duty cycle, for a stopped motor, is a count of 128. By
changing the value in AH when the procedure is called, we can adjust the motor speed. The
speed of the motor will increase in either direction by changing the number in AH when this pro-
HI
cedure is called. As the value in AH approaches OOH, the motor begins to increase its speed in DC
D
the reverse direction. As the value of AH approached FFH, the motor increases its speed in the O
forward direction.

437

11-6 16550 PROGRAMMABLE COMMUNICATIONS INTERFACE 439
0003 8A CD MOV BL,AL /calculate count
———— 30,720———H 0005 B8 0078 MOV AX, 120
0008 F6 E3 MUL BL
OOOA 8B D8 MOV BX,AX
OOOC B8 7800 MOV AX, COUNT
CLR
OOOF 2B C3 SUB AX,BX
0011 8B D8 MOV BX, AX

PS 0013 BA 0706 MOV DX , CNTR ; program control words
0016 BO 34 MOV AL,00110100B
0018 EE OUT DX,AL
Q 0019 BO 74 MOV AL, 01110100B
001B EE OUT DX,AL
-15,360 ~H (a)
001C BA 0702 MOV DX,CNT1 ; program counter 1
001F B8 7800 MOV AX, COUNT ; to generate a clear
0022 EE OUT DX, AL
- 30,720 - 0023 8A C4 MOV AL , AH
0025 EE OUT DX,AL
0026
CLR 0026 EC IN AL,DX ;wait for counter 1
0027 86 C4 XCHG AL,AH ; to reach calculated
0029 EC IN AL,DX ,- count
002A 86 C4 XCHG AL,AH
PS 002C 3B C3 CMP AX,BX
002E 72 F6 JB SPE
Q
0030 BA 0700 MOV DX,CNTO /program counter 0
3072 0033 B8 7800 MOV AX , COUNT ; to generate a set
(b)
0036 EE OUT DX,AL
0037 8A C4 MOV AL,AH
0039 EE OUT DX,AL
-30,720-
003A 5B POP BX /restore registers
003B 5A POP DX
CLR 003C 58 POP AX
003D C3 RET

PS IT SPEED ENDP

The procedure adjusts the wave form at Q by first calculating the count that counter 0 is to
start in relationship to counter 1. This is accomplished by multiplying AH by 120 and then sub-
- 27,658 - tracting it from 30,720. This is required because the counters are down-counters that count from
(c)
the programmed count to 0 before restarting. Next, counter 1 is programmed with a count of
FIGURE 11-46 Timing for the motor speed and direction control circuit of Figure 11-45. (a) No rotation, 30,720 and started to generate the clear wave form for the flip-flop. After counter 1 is started, it
(b) high-speed rotation in the reverse direction, and (c) high-speed rotation in the forward direction. is read and compared with the calculated count. Once it reaches this count, counter 0 is started
with a count of 30,720. From this point forward, both counters continue generating the clear and
set wave forms until the procedure is again called to adjust the speed and direction of the motor.
EXAMPLE 11-27
;A procedure that controls the speed and direction
;of the motor in Figure 11-45.
11-6 16550 PROGRAMMABLE COMMUNICATIONS INTERFACE
;When this procedure is called, the contents of
;AH determine the speed and direction of the
;motor where AH is between OOH and FFH. The National Semiconductor Corporation's PC16550D is a programmable communications in-
terface designed to connect to virtually any type of serial interface. The 16550 is a universal
= 0706 CNTR EQU 706H
= 0700 CNTO EQU 7OOH asynchronous receiver/transmitter (UART) that is fully compatible with the Intel microproces-
= 0702 CNTO EQU 702H sors. The 16550 is capable of operating at 0-1.5 M Baud. Baud rate is the number of bits trans-
= 7800 COUNT EQU 30720 ferred per second, including start, stop, data, and parity. The 16550 also includes a
SPEED PROC NEAR
programmable Baud rate generator and separate FIFOs for input and output data to ease the load
0000
on the microprocessor. Each FIFO contains 16 bytes of storage. This is the most common com-
0000 50 PUSH AX munications interface found in modern microprocessor-based equipment, including the personal
0001 51 PUSH DX computer and many modems.
0002 53 PUSH BX

11-6 16550 PROGRAMMABLE COMMUNICATIONS INTERFACE 441
440
CB (citizens band) radio, where we transmit and receive, but not both at the same time. The
- Frame - full-duplex system allows transmission and reception in both directions simultaneously. An ex-
ST Do D, D2 D4 pJ ST D 0 p, D2 D3 D4 D5 p * I * I * I ample full-duplex system is the telephone.
The 16550 can control a modem (modulator/demodulator), which is a device that converts
TTL levels of serial data into audio tones that can pass through the telephone system. Five pins
* = STOP on the 16650 are devoted to modem control: DSR (data set ready), DTR (data terminal ready),
ST = START CTS (clear-to-send), RTS (request-to-send), RI (ring indicator), and DCD (data carrier detect).
FIGURE 11-47 Asynchronous serial data. The modem is referred to as the data set and the 16550 is referred to as the data terminal.

16550 Pin Functions
Asynchronous Serial Data AO, Al, A2 The address inputs are used to select an internal register for programming
Asynchronous serial data are transmitted and received without a clock or timing signal. Figure and also data transfer. See Table 11-8 for a list of each combination of
11-47 illustrates two frames of asynchronous serial data. Each frame contains a start bit, seven the address inputs and the registers selected.
data bits, parity, and one stop bit. The figure shows a frame that contains one ASCII character ADS The address strobe input is used to latch the address lines and chip select
and 10 bits. Most dial-up communications systems, such as CompuServe, Prodigy, and America lines. If not needed (as in the Intel system), connect this pin to ground.
Online, use 10 bits for asynchronous serial data with even parity. Most Internet and bulletin The ADS pin is designed for use with Motorola microprocessors.
board services also use 10 bits, but they normally do not use parity. Instead, eight data bits are BAUDOUT The Baud out pin is where the clock signal generated by the Baud rate
transferred, replacing parity with a data bit. This makes byte transfers of non-ASCII data much generator from the transmitter section is made available. It is most often
easier to accomplish. connected to the RCLK input to generate a receiver clock that is equal to
the transmitter clock.
16550 Functional Description CSO, CS1, CS2 The chip select inputs must all be active to enable the 16550 UART.
Figure 11-48 illustrates the pin-out of the 16550 UART. This device is available as a 40-pin DIP CTS The clear to send (if low) indicates that the modem or data set is ready to
(dual in-line package) or as a 44-pin PLCC (plastic lead-less chip carrier). Two completely exchange information. This pin is often used in a half-duplex system to
separate sections are responsible for data communications: the receiver and the transmitter. Be- turn the line around.
cause each of these sections is independent of each other, the 16550 is able to function in sim- D7-DO The data bus pins are connected to the microprocessor data bus.
plex, half-duplex, or full-duplex modes. One of the main features of the 16550 is its internal DCD The data carrier detect input is used by the modem to signal the 16550
receiver and transmitter FIFO (first-in, first-out) memories. Because each is 16 bytes deep, the that a carrier is present.
UART requires attention only from the microprocessor after receiving 16 bytes of data. It also
holds 16 bytes before the microprocessor must wait for the transmitter. The FIFO makes this DDIS The disable driver output becomes a logic 0 to indicate that the
microprocessor is reading data from the UART. DDIS can be used to
UART ideal when interfacing to high-speed systems because less time is required to service it.
change the direction of data flow through a buffer.
An example simplex system is one in which the transmitter or receiver is used by itself
such as in an FM (frequency modulation) radio station. An example half-duplex system is a DSR Data set ready is an input to the 16550, indicating that the modem or
data set is ready to operate.
DTR Data terminal ready is an output that indicates that the data terminal
FIGURE 11-48 The pin-out (16550) is ready to function.
27 2
of the 16550 UART. 26
A1 16550 01 3 INTR Interrupt request is an output to the microprocessor used to request an
A2 D2
4
12
CSO
D3
5 interrupt (INTR =1) whenever the 16550 has a receiver error, it has
13 D4
14
CS1
D5
6 received data, and if the transmitter is empty.
CS2 —— 1~
D6
35 —— 8~
MR D7

-^ RD
SIN
10 TABLE 1 1-8 The registers
19
RD
SOUT
11
selected by AO, A1 , and A2. •A2 A1 AO Register
WR
18
WR BAUDOUT
25 "
ADS RCLK
° 9 0 0 0 Receiver buffer (read) and transmitter holding (write)
16 0^2_ 0 0 1 Interrupt enable
XIN RTS
17 0 1 0 Interrupt identification (read) and FIFO control (write)
24
XOUT CTS £H
DTR
xn:
^ 37
0 1 1 Line control
TXRDY
29 "
RXRDY
DSR
""sir 1 0 0 Modem control
DCD
23
DDIS RI
°~39~ 1 0 1 Line status
30
INTR
34 1 1 0 Modem status
OUT1
OUT 2
Q 31 1 1 1 Scratch

442 CHAPTER 11 BASIC I/O INTERFACE 11-6 16550 PROGRAMMABLE COMMUNICATIONS INTERFACE 443

MR Master reset initializes the 16550 and should be connected to the system FIGURE 11-49 The con- Line Control Register
RESET signal. tents of the 16550 line control 6 5 4 3 2 1 0
OUT1, OUT2 User-defined output pins that can provide signals to a modem or any register.
DL 5SB ST P PE S L1 LO
other device, as needed in a system.
I , I Data Length
RCLK Receiver clock is the clock input to the receiver section of the UART. 00 = 5 bits
' ————— 01 - 6 bits
This input is always 16 x the desired receiver Baud rate. 10 = 7 bits
11=8 bits
RD, RD Read inputs (either may be used) cause data to be read from the register
Stop bits
specified by the address inputs to the UART. 0 = 1 stop bit
1 = 1 .5 or 2 stop bits
RI The ring indicator input is placed at the logic 0 level by the modem to Parity enable
indicate that the telephone is ringing. 1 = parity enabled
Parity type
RTS Request-to-send is a signal to the modem, indicating that the UART
1 = even parity
wishes to send data.
Stick bit
SIN, SOUT These are the serial data pins. SIN accepts serial data and SOUT u = sticK parity on
1 = stick parity on
transmits serial data. Send break
0 = no break sent
RXRDY Receiver ready is a signal used to transfer received data via DMA 1 = send break on SOUT
techniques (see text). 0 = divisor latch off
TXRDY Transmitter ready is a signal used to transfer transmitter data via DMA 1 = enable divisor latch

techniques (see text).
WR, WR Write (either may be used) connects to the microprocessor write signal to TABLE 11-9 The opera-
transfer commands and data to the 16550. tion of the ST and parity bits. PE Function
XIN, XOUT These are the main clock connections. A crystal is connected across 0 0 0 No parity
these pins to form a crystal oscillator, or XIN is connected to an external 0 0 1 Odd parity
timing source. 0 1 0 No parity
0 1 1 Even parity
Programming the 16550 1 0 0 Undefined
1 0 1 Send/receive 1
Programming the 16550 is simple, although may be slightly more involved when compared to 1 1 0 Undefined
some of the other programmable interfaces described in this chapter. Programming is a two-part 1 1 1 Send/receive 0
process that includes the initialization dialog and operational dialog.
Initializing the 16550. Initialization dialog, which occurs after a hardware or software reset,
consists of two parts: programming the line control register and the baud rate generator. The line definition, is at least two frames of logic 0 data. The software in the system is responsible for
control register selects the number of data bits, number of stop bits, and parity (whether it's even timing the transmission of the break. To end the break, bit position 6 or the line control register
or odd, or if parity is sent as a 1 or a 0). The Baud rate generator is programmed with a divisor is returned to a logic 0 level. The Baud rate divisor is only programmable when bit position 7 of
that determines the Baud rate of the transmitter section. the line control register is a logic 1.
Figure 11-49 illustrates the line control register. The line control register is programmed
by outputting information to I/O port Oil (A2, Al, AO). The rightmost two bits of the line con- Programming the Baud Rate. The Baud rate generator is programmed at I/O addresses 000 and
trol register select the number of transmitted data bits (5, 6, 7, or 8). The number of stop bits is 001 (A2, Al, AO). Port 000 is used to hold the least-significant part of the 16-bit divisor, and port
selected by S in the line control register. If S = 0, one stop bit is used; if S = 1, 1.5 stop bits are 001 is used to hold the most-significant part. The value used for the divisor depends on the ex-
used for five data bits, and two stop bits are used with six, seven, or eight data bits. ternal clock or crystal frequency. Table 11-10 illustrates common Baud rates obtainable if a
The next three bits are used together to send even or odd parity, to send no parity, or to 18.432 MHz crystal is used as a timing source. It also shows the divisor values programmed into
send a 1 or a 0 in the parity bit position. To send even or odd parity, the ST (stick) bit must be the Baud rate generator to obtain these Baud rates. The actual number programmed into the Baud
placed at a logic 0 level, and parity enable must be a logic 1. The value of the parity bit then de- rate generator causes it to produce a clock that is 16 times the desired Baud rate. For example, if
termines even or odd parity. To send no parity (common in Internet connections), ST = 0 as well 240 is programmed into the Baud rate divisor, the Baud rate is 18-432 MHz/i6x24o = 4800 Baud.
as the parity enable bit. This sends and receives data without parity. Finally, if a 1 or a 0 must be Sample Initialization. Suppose that an asynchronous system requires seven data bits, odd parity, a
sent and received in the parity bit position for all data, ST = 1 with a 1 in parity enable. To send Baud rate of 9600, and one stop bit. Example 11-28 lists a procedure that initializes the 16550 to
a 1 in the parity bit position, place a 0 in the parity bit; to send a 0, place a 1 in the parity bit. (See function in this manner. Figure 11-50 shows the interface to the 8088 microprocessor, using a
Table 11-9 for the operation of the parity and stick bits.) PAL16L8 to decode the 8-bit port addresses FOH and F7H. (The PAL program is not shown.) Here,
The remaining bits in the line control register are used to send a break and to select pro- port F3H accesses the line control register and FOH and F1H access the Baud rate divisor registers.
gramming for the Baud rate divisor. If bit position 6 of the line control register is a logic 1, a The last part of Example 11-28 is described with the function of the FIFO control register in the
break is transmitted. As long as this bit is a 1, the break is sent from the SOUT pin. A break, by next few paragraphs.

444 CHAPTER 11 BASIC I/O INTERFACE 11-6 16550 PROGRAMMABLE COMMUNICATIONS INTERFACE 445

The divisor OOOC BO OA MOV AL,00001010B ; program 7 -data, odd
aud rate gen- Baud rate Divisor value OOOE E6 F3 OUT LINE,AL ; parity, one stop
.432 MHz 0010 BO 07 MOV AL,00000111B ; enable transmitter and
110 10,473
ng common ^ 0012 E6 F2 OUT FIFO,AL ,- receiver
3840
Baud rates.
1200 920 0014 C3 RET
2400 480
4800 240 0015 START ENDP
9600 120
19,200 60 After the line control register and Baud rate divisor are programmed into the 16550, it is
38,400 30 still not ready to function. After programming the line control register and Baud rate, we still
57,600 20 must program the FIFO control register, which is at port F2H in the circuit of Figure 11-50.
115,200 10 Figure 11-51 illustrates the FIFO control register for the 16550. This register enables the trans-
mitter and receiver (bit 0 = 1), and clears the transmitter and receiver FIFOs. It also provides
control for the 16550 interrupts, which are discussed in Chapter 12. Notice that the last section of
FIGURE 11-50 The 16550
vcc Example 11-28 places a 7 into the FIFO control register. This enables the transmitter and re-
interfaced to the 8088 micro- ceiver, and clears both FIFOs. The 16550 is now ready to operate, but without interrupts. Inter-
processor at ports > 10K rupts are automatically disabled when the MR (master reset) input is placed at a logic 1 by the
x
OOFOH-OOF7H. Data Bus (DO-D7) system RESET signal.
IO/M Sending Serial Data. Before serial data can be sent or received through the 16550, we need to
1 U2
know the function of the line status register (see Figure 11-52). The line status register contains
A3 11 01 Q 19
A4 __ ?_ 12 02 AO — 28
AO D1 1_/ information about error conditions and the state of the transmitter and receiver. This register is
A5 __ 3_ 13 03 A1 — A1 D2
A6 __ 1 . 14 04 -) 16 A2 -isr
i>k> A2 D3 —4 /
3— / tested before a byte is transmitted or can be received.
A7 __ 5_
A8 __ 6_
15
16
05
06
0^
12
D4 5 / Suppose that a procedure (see Example 11-29) is written to transmit the contents of AH to
;• 13 ' CSO D5
13 6 /
A9 __ 7_ 17 07
~? 12 14
CS1 D6
7 y the 16550 and out through its serial data pin (SOUT). The TH bit is polled by software to deter-
A10 __ |_ IS 08 CS2 D7
19 D8 _8_/ mine whether the transmitter is ready to receive data. This procedure uses the circuit of Figure
A12 ~~T^ 110
RESET 35 MR
22 RD SIN 10 Serie 11-50.
16L8 RD _ 21
—— T9~ WR SOUT ^J —— data
A13
A14 WR J 18 15
25 ADS •^ 9 | EXAMPLE 11-29
A15 Rri K
16 VIM
ANN DTC
H| o
32 ;A Procedure that transmits AH via the 16550 UART
17 XOUT §36
CTS
r~ DTR Q-^M —— = OOF5 LSTAT EQU OF5H ;line status port
18.432 MHz TXRDY DSR
^9§ RXRDY DCD g38~ = OOFO DATA EQU OFOH ;data port
DDIS Rl — 22 —
Jiz INTR .
0000 SEND PROC NEAR
OUT1 O-^ —
i OUT 2 o ——

FIGURE 11-51 The FIFO FIFO Control Register
control register of the 16550 7 6 5 4 3 2 1
EXAMPLE 11-28 UART. XMIT REVC
RT1 RTO 0 0 DMA EN
;Initialization Dialog for Figure 11-50. RST RST
;Baud rate 9600, 7 data, odd parity, one stop I __ __ I FIFO Enable
0 = disable the FIFO
= OOF3 LINE EQU OF3H
'— 1 = enable the FIFO

= OOFO LSB EQU OFOH Receiver Reset
0 = no effect
= OOF1 MSB EQU OF1H 1 = reset receiver FIFO
= OOF2 FIFO EQU OF2H
- Transmitter Reset
START PROC NEAR 0 = no effect
0000 1 = reset transmitter FIFO

0000 BO 8A MOV AL,10001010B ; enable Baud divisor DMA mode control
OUT LINE,AL 0 = set to function as 16450 UART
0002 E6 F3 1 = FIFO mode
0004 BO 78 MOV AL,120 ; program Baud rate Receiver Trigger level
0006 E6 FO OUT LSB,AL 00 = 1 bytes in FIFO
01 = 4 bytes in FIFO
0008 BO 00 MOV AL, 0 10 = 8 bytes in FIFO
OOOA E6 Fl OUT MSB , AL 11 = 14 bytes in FIFO

11-7 AIMALOG-TO-DIGITAL (ADC) AND DIGITAL-TO-ANALOG (DAC) CONVERTERS 447

FIGURE 11-52 The con- Line Status Register OOOD BO 3F MOV AL, ' ;get question mark
tents of the line status reg- 7 6 5 4 3 2 1 0 OOOF C3 RET
ister of the 16550 UART.
ER TE TH Bl FE PE OE DR 0010 REVC ENDP
Data Ready
— 0 = no data to read UART Errors, The types of errors detected by the 16550 are parity error, framing error, and
1 = data in FIFO
Overrun Error
overrun error. A parity error indicates that the received data contain the wrong parity. A framing
0 = no overrun error
1 = overrun error
error indicates that the start and stop bits are not in their proper places. An overrun error indi-
cates that data have overrun the internal receiver FIFO buffer. These errors should not occur
_ Parity Error
0 = no parity error during normal operation. If a parity error occurs, it indicates that noise was encountered during re-
1 = parity error
ception. A framing error occurs if the receiver is receiving data at an incorrect Baud rate. An
Framing Error
0 = no framing error overrun error occurs only if the software fails to read the data from the UART before the receiver
1 = framing error
FIFO is full. This example does not test the BI (break indicator bit) for a break condition. Note that
Break Indicator
- 0 = no break a break is two consecutive frames of logic Os on the SIN pin of the UART. The remaining regis-
1 = break being received ters, which are used for interrupt control and modern control, are developed in Chapter 12.
Transmitter Holding Register
~~ 0 = wait for transmitter
1 = transmitter ready for data
_ Transmitter Empty
0 = transmitter not empty
1 = transmitter empty
11-7 ANALOG-TO-DIGITAL (ADC) AND DIGITAL-TO-ANALOG (DAC) CONVERTERS
_ Error
0 = no error
1 = at least one error in FIFO
Analog-to digital (ADC) and digital-to-analog (DAC) converters are used to interface the micro-
processor to the analog world. Many events that are monitored and controlled by the micro-
0000 50 PUSH AX save AX processor are analog events. These often include monitoring all forms of events, even speech, to
0001 E4 F5 IN AL,LSTAT get line status register controlling motors and like devices. In order to interface the microprocessor to these events, we
0003 A8 20 TEST AL,20H test TH bit must have an understanding of the interface and control of the ADC and DAC, which convert be-
0005 74 FA JZ SEND if transmitter not ready
tween analog and digital data.
0007 8A C4 MOV AL,AH get data
0009 E6 FO OUT DATA,AL transmit data The DAC0830 Digital-to-Analog Converter
OOOB 58 POP AX restore AX
OOOC C3 RET A fairly common and low-cost digital-to-analog converter is the DAC0830 (a product of National
OOOD SEND ENDP
Semiconductor Corporation). This device is an 8-bit converter that transforms an 8-bit binary
number into an analog voltage. Other converters are available that convert from 10-, 12-, or 16-bit
Receiving Serial Data. To read received information from the 16550, we test the DR bit of the binary numbers into analog voltages. The number of voltage steps generated by the converter is
line status register. Example 11-30 lists a procedure that tests the DR bit to decide whether the equal to the number of binary input combinations. Therefore, an 8-bit converter generates 256 dif-
16550 has received any data. Upon the reception of data, the procedure tests for errors. If an error ferent voltage levels, a 10-bit converter generates 1024 levels, and so forth. The DAC0830 is a
is detected, the procedure returns with AL equal to an ASCII '?'. If no error has occurred, then medium speed converter that transforms a digital input to an analog output in approximately 1.0 (is.
the procedure returns with AL equal to the received character. Figure 11-53 illustrates the pin-out of the DAC0830. This device has a set of eight data
bus connections for the application of the digital input code, and a pair of analog outputs labeled
EXAMPLE 11-30 loutl and Iout2 that are designed as inputs to an external operational amplifier. Because this is an
;A procedure that receives data from the 16550 UART
;and returns it in AL.
FIGURE 11-53 The pin-out
cs
= OOF5 LSTAT EQU OF5H line status port of the DAC0830 digital-to- WR1 VREF
= OOFO DATA EQU OFOH data port analog converter. -J&c WR2
DIG
0000 RECV PROG NEAR DI1 RFB
DI2
0000 E4 F5 IN AL, LSTAT get line status register DI3
0002 A8 01 TEST AL,1 test DR bit DI4 IOUT2
0004 74 FA JZ RECV if no data in receiver DI5
DI6 IOUT1
DI7
0006 A8 OE TEST AL,OEH test all 3 error bits
0008 75 03 JNZ ERR for an error XFER
ILE
OOOA E4 FO AL,DATA ;read data from 16550
OOOC C3 DGND AGND
OOOD DAC0830

9-2 CLOCK GENERATOR (8284A) 313
CHAPTER 9 8086/8088 HARDWARE SPECIFICATIONS
312
Operation of the 8284A
—— ^
FIGURE 9-2 The pin-out of CSYNC C •'Te" DVCC The 8284A is a relatively easy component to understand. Figure 9-3 illustrates the internal block
the 822844A clock generator. PCLKC 17 DX1 diagram of the 8284A clock generator.
AENlC 3 16 DX2
15 D23?H5 Operation of the Clock Section, The top half of the logic diagram represents the clock and reset
RDY1C
READY C >
MA
14 DEFI synchronization section of the 8284A clock generator. As the diagram shows, the crystal oscil-
RDY2C 6 13 DF/C" lator has two inputs: XI and X2. If a crystal is attached to XI and X2, the oscillator generates a
SfNlC 7 12 Hose square-wave signal at the same frequency as the crystal. The square-wave signal is fed to an
CLKC 8 11 DRES AND gate and also to an inverting buffer that provides the OSC output signal. The OSC signal is
QNDC 9 10 D RESET sometimes used as an EFI input to other 8284A circuits in a system.
An inspection of the AND gate reveals that when F/C is a logic 0, the oscillator output is
steered through to the divide-by-3 counter. If F/C is a logic 1, then EFI is steered through to the
P//7 Functions. The 8284A is an 18-pin integrated circuit, designed specifically for use with the counter.
8086/8088 microprocessors. The following is a list of each pin and its function: The output of the divide-by-3 counter generates the timing for ready synchronization, a
AEN1 and The address enable pins are provided to qualify the bus ready signals, RDY1 signal for another counter (divide-by-2), and the CLK signal to the 8086/8088 microprocessors.
AEN2 and RDY2, respectively. Section 9-5 illustrates the use of these two pins, The CLK signal is also buffered before it leaves the clock generator. Notice that the output of the
which are used to cause wait states, along with the RDY1 and RDY2 inputs. first counter feeds the second. These two cascaded counters provide the divide-by-6 output at
Wait states are generated by the READY pin of the 8086/8088 microprocessors, PCLK, the peripheral clock output.
Figure 9-4 shows how an 8284A is connected to the 8086/8088. Notice that F/C and
which is controlled by these two inputs. CSYNC are grounded to select the crystal oscillator; and that a 15 MHz crystal provides the
The bus ready inputs are provided, in conjunction with the AEN1 and AEN2
RDY1 and normal 5 MHz clock signal to the 8086/8088, as well as a 2.5 MHz peripheral clock signal.
pins, to cause wait states in an 8086/8088-based system.
RDY2 The ready synchronization selection input selects either one or two stages of Operation Of the Reset Section. The reset section of the 8284A is very simple: It consists of a
ASYNC Schmitt trigger buffer and a single D-type flip-flop circuit. The D-type flip-flop ensures that the
synchronization for the RDY1 and RDY2 inputs.
timing requirements of the 8086/8088 RESET input are met. This circuit applies the RESET signal
Ready is an output pin that connects to the 8086/8088 READY input. This
READY to the microprocessor on the negative edge (l-to-0 transition) of each clock. The 8086/8088 micro-
signal is synchronized with the RDY1 and RDY2 inputs. processors sample RESET at the positive edge (0-to-l transition) of the clocks; therefore, this cir-
The crystal oscillator pins connect to an external crystal used as the timing cuit meets the timing requirements of the 8086/8088. __
XI and X2 source for the clock generator and all its functions. Refer to Figure 9-4. Notice that an RC circuit provides a logic 0 to the RES input pin when
The frequency/crystal select input chooses the clocking source for the power is first applied to the system. After a short time, the RES input becomes a logic 1 because
F/C 8284A. If this pin is held high, an external clock is provided to the EFI input the capacitor charges toward +5.0 V through the resistor. A push-button switch allows the mi-
pin; if it is held low, the internal crystal oscillator provides the timing signal. croprocessor to be reset by the operator. Correct reset timing requires the RESET input to be-
The external frequency input is used when the F/C pin is pulled high. EFI come a logic 1 no later than four clocks after system power is applied, and to be held high for at
EFI supplies the timing whenever the F/C pin is high. least 50 (is. The flip-flop makes certain that RESET goes high in four clocks, and the RC time
constant ensures that it stays high for at least 50 fis.
The clock output pin provides the CLK input signal to the 8086/8088
CLK microprocessors and other components in the system. The CLK pin has an
output signal that is one-third of the crystal or EFI input frequency, and has a The internal
33-percent duty cycle, which is required by the 8086/8088. diagram of the 8284A
" generator.
The peripheral clock signal is one-sixth the crystal or EFI input frequency,
PCLK and has a 50-percent duty cycle. The PCLK output provides a clock signal to
the peripheral equipment in the system.
The oscillator output is a TTL-level signal that is at the same frequency as
OSC the crystal or EFI input. The OSC output provides an EFI input to other
8284A clock generators in some multiple-processor systems.
The reset input is an active-low input to the 8284A. The RES pin is often
RES connected to an RC network that provides power-on resetting.
The reset output is connected to the 8086/8088 RESET input pin.
RESET
The clock synchronization pin is used whenever the EFI input provides
CSYNC synchronization in systems with multiple processors. If the internal crystal
oscillator is used, this pin must be grounded.
The ground pin connects to ground.
GND This power supply pin connects to +5.0 V with a tolerance of ±10 percent. ^ ASYNC

Vcc

9-3 BUS BUFFERING AND LATCHING 315
314

15MHz 8086

RESET

Address bus

T System
reset

the microprocessor.

BUS Dum-iuin'-' 11--- — -
DUo BUFFERING AND LATCHING
9-3

buses and illustrates how thebu^^ t^ns more than 10 other components.)
fan-out is 10, the system must be buttered
Control bus
Demultiplexing the Buses number of pins
The address/data bus on the 8086/8088 *£££$£$££,#. this burdens the hard- + 5V
FIGURE 9-5 The 8088 microprocessor shown with a demultiplexed address bus. This is the
model used to build many 8088-based systems.

allow the 8088 to address 1M bytes of memory space. The fact that the data bus is separate al-
lows it to be connected to any eight-bit peripheral device or memory component.
Demultiplexing the 8086. Like the 8088, the 8086 system requires separate address, data, and
control buses. It differs primarily in the number of multiplexed pins. In the 8088, only AD7-ADO
and A19/S6-A16/S3 are multiplexed. In the 8086, the multiplexed pins include AD15-ADO,
A19/S6-A16/S3, and BHE/S7. All of these signals must be demultiplexed.
Figure 9-6 illustrates a demultiplexed 8086 with all three buses: address (A19-AO and
SHE), data (D15-DO), and control (MIO, RD, and WR).
This circuit shown in Figure 9-6 is almost identical to the one pictured in Figure 9-5, ex-
cept that an additional 74LS373 latch has been added to demultiplex the address/data bus pins
AD15-AD8 and a BHE/S7 input has been added to the top 74LS373 to select the high-order
memory bank in the 16-bit memory system of the 8086. Here, the memory and I/O system see

324 CHAPTER 9 8086/8088 HARDWARE SPECIFICATIONS 9-5 READY AND THE WAIT STATE
325
8088 is operated with a 5 MHz clock. Hold time is often much less than this; it is, in fact, often
0 ns for memory devices. The width of the WR strobe is TWLWH or 340 ns at a 5 MHz clock rate. -Tw-
This rate is compatible with most memory devices that have an access time of 400 ns or less. CLK

RDY
9-5 READY AND THE WAIT STATE
As we mentioned earlier in this chapter, the READY input causes wait states for slower memory FIGURE 9-15 8284A RDY input timing.
and I/O components. A wait state (Tw) is an extra clocking period, inserted between T2 and T3,
to lengthen the bus cycle. If one wait state is inserted, then the memory access time, normally
460 ns with a 5 MHz clock, is lengthened by one clocking period (200 ns) to 660 ns. The ASYNC input selects one stage of synchronization when it is a logic 1 and two stages
In this section, we discuss the READY synchronization circuitry inside the 8284A clock when it is a logic 0. If one stage is selected, then the RDY signal is kept from reaching the
generator, show how to insert one or more wait states selectively into the bus cycle, and examine 8086/8088 READY pin until the next negative edge of the clock. If two stages are selected, the first
the READY input and the synchronization times it requires. positive edge of the clock captures RDY in the first flip-flop. The output of this flip-flop is fed to
the second flip-flop, so on the next negative edge of the clock, the second flip-flop captures RDY.
The READY Input Figure 9-17 illustrates a circuit used to introduce almost any number of wait states for the
8086/8088 microprocessors. Here, an eight-bit serial shift register (74LS164) shifts a logic 0 for
The READY input is sampled at the end of T2 and again, if applicable, in the middle of Tw. If
one or more clock periods from one of its Q outputs through to the RDY1 input of the 8284A.
READY is a logic 0 at the end of T2, T3 is delayed and Tw is inserted between T2 and T3.
With appropriate strapping, this circuit can provide various numbers of wait states. Notice also
READY is next sampled at the middle of Tw to determine whether the next state is Tw or T3. It
how the shift register is cleared back to its starting point. The output of the register is forced high
is tested for a logic 0 on the l-to-0 transition of the clock at the end of T2, and for a 1 on the 0-
when the RD, WR, and INTA pins are all logic Is. These three signals are high until state T2, so
to-1 transition of the clock in the middle of Tw. the shift register shifts for the first time when the positive edge of the T2 arrives. If one wait is
The READY input to the 8086/8088 has some stringent timing requirements. The timing
desired, output QB is connected to the OR gate. If two waits are desired, output Qc is connected,
diagram in Figure 9-14 shows READY causing one wait state (Tw), along with the required and so forth.
setup and hold times from the system clock. The timing requirement for this operation is met by
Notice in Figure 9-17 that this circuit does not always generate wait states. It is enabled from
the internal READY synchronization circuitry of the 8284A clock generator. When the 8284A is
the memory only for memory devices that require the insertion of waits. If the selection signal from
used for READY, the RDY (ready input to the 8284A) input occurs at the end of each T state.
a memory device is a logic 0, the device is selected; then this circuit will generate a wait state.
Figure 9-18 illustrates the timing diagram for this shift register wait state generator when
RDY and the 8284A it is wired to insert one wait state. The timing diagram also illustrates the internal contents of the
RDY is the synchronized ready input to the 8284A clock generator. The timing diagram for this shift register's flip-flops to present a more detailed view of its operation. In this example, one
input is provided in Figure 9-15. Although it differs from the timing for the READY input to the wait state is generated.
8086/8088, the internal 8284A circuitry guarantees the accuracy of the READY synchronization
provided to the 8086/8088 microprocessors. FIGURE 9-16 The internal
Figure 9-16 again depicts the internal structure of the 8284A. The bottom half of this dia- block diagram of the 8284A
gram is the READY synchronization circuitry. At the leftmost side, the RDY1 and AEN1 inputs £lock generator. (Courtesy of
are ANDed, as are the RDY2 and AEN2 inputs. The outputs of the AND gates are then ORed to Corporation).
generate the input to the one or two stages of synchronization. In order to obtain a logic IjiUhe
inputs to the flip-flops, RDY1 ANDed with AEN1 must be active or RDY2 ANDed with AEN2
must be active.

CLK

READY

FIGURE 9-14 8086/8088 READY input timing. ASYNC

9-6 MINIMUM MODE VERSUS MAXIMUM MODE 327
326

RDY,
AEN, ^
-<-, ——————————————————

() l w 2W 3U 4W 5 W 6W 7,
CS from memory device 9-6 MINIMUM MODE VERSUS MAXIMUM MODE

There are two available modes of operation for the 8086/8088 microprocessors: minimum mode
8284A
Clock
RDY,
ihiiin and maximum mode. Minimum mode operation is obtained by connecting the mode selection
pin MN/MX to ±5.0 V, and maximum mode is selected by grounding this pin. Both modes en-
able different control structures for the 8086/8088 microprocessors. The mode of operation pro-
generator HT ? ? ? ? ? vided by minimum mode is similar to that of the 8085A, the most recent Intel eight-bit
microprocessor. The maximum mode is unique and designed to be used whenever a coprocessor
QA QB Qc Qn QF. QF Qc, QH
CLK '164 exists in a system. Note that the maximum mode was dropped from the Intel family, beginning
CLK with the 80286 microprocessor.
C1J.
READY

1 _ shift direction
Minimum Mode Operation
Minimum mode operation is the least expensive way to operate the 8086/8088 microprocessors

READY
A (see Figure 9-19 for the minimum mode 8088 system). It costs less because all the control signals
for the memory and I/O are generated by the microprocessor. These control signals are identical
CLK
to those of the Intel 8085A, an earlier eight-bit microprocessor. The minimum mode allows the
8085A, eight-bit peripherals to be used with the 8086/8088 without any special considerations.

RD 0 , . .. ., Maximum Mode Operation
8088 WR
Maximum mode operation differs from minimum mode in that some of the control signals must
INTA
8086 be externally generated. This requires the addition of an external bus controller—the 8288 bus
controller (see Figure 9-20 for the maximum mode 8088 system). There are not enough pins on
the 8086/8088 for bus control during maximum mode because new pins and new features have

FIGURE 9-17 A circuit that will cause between 0 and 7 wait states.

CLK

RDY,

QA

QB

RD

FIGURE 9-18 Wait state generation timing of the circuit of Figure 9-17.

Input Output

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