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MICROPROCESSOR 8085
LECTURE 18
MEMORY INTERFACING-I
PROF. SANDIP DAS
WHAT IS MEMORY
• It stores binary instruction
• Broadly classified as RAM and ROM
• Made of registers and each register has a group of flip-flops.
So, we infer that a latch or a flip-flop acts as the basic
storage element that can store bits.
Basic Latch
D
Q
EN
DIN
EN
D
Q
ENEN
Dout
DIN
𝑊𝑅
𝑅𝐷
Dout
Latch with Tri-state buffer
TRI-STATE DEVICES
• Tri-state logic devices have three stages: logic 1, logic 0 and
high impedance.
Enable Enable
Active
High
Active
Low
Tri-State Inverter with
active High Enable line
Tri-State Inverter with active
Low Enable lines
Buffer
A Tri-state Buffer
Enable
Active
Low
LATCH WITH A TRI-STATE BUFFER AS A
MEMORY CELL
• We can write into latch by enabling
input buffer by providing active low
signal
• We can read from the latch by
enabling the output buffer by
providing active low signal
D
Q
ENEN
DIN
𝑊𝑅
𝑅𝐷
Dout
𝑊𝑅
𝑅𝐷
FOUR LATCHES AS FOUR BIT REGISTER
TO WRITE INTO OR READ FROM ANY ONE OF THE
REGISTERS: SPECIFIC REGISTER SHOULD BE
ENABLED
Register 3
Register 2
Register 1
Register 0
Output Buffer
Input Buffer
2-t0-4
Decoder𝑊𝑅
𝑅𝐷
A1
A0
• Thus, 2-to-4 decoder can
perform the required function
with the use of two input lines A0
and A1.
• These two input lines can have
four different bit combinations
(00,01,10,11) and each
combination can enable one of
the registers namely Register 0 to
Register 3.
• Thus, the Enable signal of the
flip-flops is replaced by two
address lines.
outputs
inputs

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15. memory interfacing i

  • 1. MICROPROCESSOR 8085 LECTURE 18 MEMORY INTERFACING-I PROF. SANDIP DAS
  • 2. WHAT IS MEMORY • It stores binary instruction • Broadly classified as RAM and ROM • Made of registers and each register has a group of flip-flops. So, we infer that a latch or a flip-flop acts as the basic storage element that can store bits. Basic Latch D Q EN DIN EN D Q ENEN Dout DIN 𝑊𝑅 𝑅𝐷 Dout Latch with Tri-state buffer
  • 3. TRI-STATE DEVICES • Tri-state logic devices have three stages: logic 1, logic 0 and high impedance. Enable Enable Active High Active Low Tri-State Inverter with active High Enable line Tri-State Inverter with active Low Enable lines Buffer A Tri-state Buffer Enable Active Low
  • 4. LATCH WITH A TRI-STATE BUFFER AS A MEMORY CELL • We can write into latch by enabling input buffer by providing active low signal • We can read from the latch by enabling the output buffer by providing active low signal D Q ENEN DIN 𝑊𝑅 𝑅𝐷 Dout 𝑊𝑅 𝑅𝐷
  • 5. FOUR LATCHES AS FOUR BIT REGISTER
  • 6. TO WRITE INTO OR READ FROM ANY ONE OF THE REGISTERS: SPECIFIC REGISTER SHOULD BE ENABLED Register 3 Register 2 Register 1 Register 0 Output Buffer Input Buffer 2-t0-4 Decoder𝑊𝑅 𝑅𝐷 A1 A0 • Thus, 2-to-4 decoder can perform the required function with the use of two input lines A0 and A1. • These two input lines can have four different bit combinations (00,01,10,11) and each combination can enable one of the registers namely Register 0 to Register 3. • Thus, the Enable signal of the flip-flops is replaced by two address lines. outputs inputs