Microprocessor 8085 Chapter 4
29 likes6,968 views
The 8085 microprocessor has 40 pins including address, data, control signals, power and clock pins. It uses multiplexed address/data bus and external latch is used to separate address and data. Memory interfacing and instruction fetch process involving program counter, memory and internal registers is explained with examples. Timing diagrams show the machine cycles and signal timings
![Timing Signals For Fetching an Instruction
4F –> [MOV C, A] stored @ 2005h
T
1
T
2
T
3
T
4 Prepared By Rishikesh Bhavsar](https://image.slidesharecdn.com/chapter4-140604025400-phpapp01/85/Microprocessor-8085-Chapter-4-13-320.jpg)
![ALU
Data Flow from Memory to the MPU [4F – MOV C, A]
INSTRUCTION
DECODER
B
D E
H L
STACK
POINTER
PROGRAM
COUNTER
INTERNAL 8-BIT REGISTER
CONTROL
LOGIC
M
E
M
O
R
Y
D
E
C
O
D
E
R
4F
2000
2005
A/D BUS
2005
4F
4F
CACC External Memory
Prepared By Rishikesh Bhavsar](https://image.slidesharecdn.com/chapter4-140604025400-phpapp01/85/Microprocessor-8085-Chapter-4-15-320.jpg)
Microprocessor 8085 Chapter 4
- 1. Chapter 4 8085 Microprocessor Architecture and Memory Interfacing
- 2. 8085 Microprocessor The Intel 8085 is an 8-bit microprocessor introduced by Intel in 1977. It is an 8-bit general purpose microprocessor capable of addressing 64K of memory. It is Single NMOS device. It contains 6200 transistors approx. The device has 40 pins Dual Inline-Package(DIP), requires a +5V single power supply, and can operate with a 3-Mhz clock. Prepared By Rishikesh Bhavsar
- 3. 8085A 8085 Microprocessor PIN Diagram 8085A Higher-Order Address Bus Multiplexed Address/Data Bus 28 21 A15 A8 AD7 AD0 19 12 ALE S0 S1 30 29 33 34 32 31 TRAP 6 7 8 9 10 RST 7.5 RST 6.5 RST 6.5 INTR READY 35 39HOLD 36 5 4 SID SOD X1 X2 + 5 V GND 1 2 40 20 HLDA 38 11 3 37 RESET OUT CLK OUT Externally Initiated Signals Externally Signals ACK Serial I/O Port Prepared By Rishikesh Bhavsar
- 4. Classify in Six Groups of 8085 Signals (1)Address Bus, (2)Data Bus, (3)Control and status signals, (4)Power supply and frequency signals, (5)Externally initiated signals, and (6)Serial I/O ports. Prepared By Rishikesh Bhavsar
- 5. The Address and Data Busses • The address bus has 8 signal lines A8 – A15 which are unidirectional. • The other 8 address bits are multiplexed (time shared) with the 8 data bits. – So, the bits AD0 – AD7 are bi-directional and serve as A0 – A7 and D0 – D7 at the same time. • During the execution of the instruction, these lines carry the address bits during the early part, then during the late parts of the execution, they carry the 8 data bits. – In order to separate the address from the data, we can use a latch to save the value before the function of the bits changes. Prepared By Rishikesh Bhavsar
- 6. The Control and Status Signals Prepared By Rishikesh Bhavsar
- 7. Frequency Control Signals • There are 3 important pins in the frequency control group. – X0 and X1 are the inputs from the crystal or clock generating circuit. • The frequency is internally divided by 2. – So, to run the microprocessor at 3 MHz, a clock running at 6 MHz should be connected to the X0 and X1 pins. – CLK (OUT): An output clock pin to drive the clock of the rest of the system. Prepared By Rishikesh Bhavsar
- 8. De-multiplexing AD7-AD0 – As we know AD7– AD0 lines are serving a dual purpose and that they need to be demultiplexed to separate out the address. – The high order bits of the address remain on the bus for three clock periods. However, the low order bits remain for only one clock period and they would be lost if they are not saved externally. Also, notice that the low order bits of the address disappear when they are needed most. – To make sure we have the entire address for the full three clock cycles, we will use an External latch to save the value of AD7– AD0 when it is carrying the address bits. We use the ALE signal to enable this latch. – Given that ALE operates as a pulse during T1, we will be able to latch the address. Then when ALE goes low, the address is saved and the AD7– AD0 lines can be used for their purpose as the bi-directional data lines. Prepared By Rishikesh Bhavsar
- 9. 8085A Microprocessor Higher-Order Address Bus 28 21 A15 A8 AD7 AD0 X1 X2 + 5 V GND 1 2 40 20 ALE LATCH 74LS373 A15 A8 A7 A0 D7 D0 AD7 AD0 Higher Order Address Bus Lower Order Address Bus Data BusBidirectional Data Bus 4F Prepared By Rishikesh Bhavsar
- 10. Microprocessor Communication and Bus Timing Cycle • Lets look at timing and the data flow of an instruction fetch operation. • To understand instruction fetch we need to understand tree important term: 1. Instruction Cycle: Defined as the time required to complete the execution of an instruction. 2. T-States: It is defined as one subdivision of the operation performed in one clock period. 3. Machine Cylce: Defined as the time required to complete one operation of accessing memory, I/O, or ACKing an External request. Machine cycle may consist of three to six T-States. Prepared By Rishikesh Bhavsar
- 11. Machine Cycle S1 S0 Control Signals Opcode Fetch 0 1 1 Memory Read 0 1 0 Memory Write 0 0 1 I/O Read 1 1 0 I/O Write 1 0 1 Interrupt ACK 1 1 1 Halt Z 0 0 Hold Z X X Reset Z X X Status 8085 Machine Cycle Status and Control Signals Prepared By Rishikesh Bhavsar
- 12. Steps For Fetching an Instruction • Lets assume that we are trying to fetch the instruction (Opcode) at memory location 2005. That means that the program counter is now set to that value i.e. PCH = 20H and PCL = 05H. – The following is the sequence of operations: • The program counter places the address value on the address bus and the controller issues a RD signal. • The memory’s address decoder gets the value and determines which memory location is being accessed. • The value in the memory location is placed on the data bus. • The value on the data bus is read into the instruction decoder inside the microprocessor. • After decoding the instruction, the control unit issues the proper control signals to perform the operation. Prepared By Rishikesh Bhavsar
- 13. Timing Signals For Fetching an Instruction 4F –> [MOV C, A] stored @ 2005h T 1 T 2 T 3 T 4 Prepared By Rishikesh Bhavsar
- 14. T1 T2 T3 T4 ALE CLOCK AD7-AD0 05H 4FH Opcode Opcode Fetch Machine Cycle A15-A08 20H Higher Order Address Bus Execution Phase Status Prepared By Rishikesh Bhavsar
- 15. ALU Data Flow from Memory to the MPU [4F – MOV C, A] INSTRUCTION DECODER B D E H L STACK POINTER PROGRAM COUNTER INTERNAL 8-BIT REGISTER CONTROL LOGIC M E M O R Y D E C O D E R 4F 2000 2005 A/D BUS 2005 4F 4F CACC External Memory Prepared By Rishikesh Bhavsar
- 16. Temp Reg. Accumulator Flags INSTRUCTION DECODER AND MACHINE CYCLE ENCODING INSTRUCTION REG INTERRUPT CONTROL SERIAL I/O CONTROL TIMING AND CONTROL UNIT ADDRESS BUFFER DATA/ADDRESS BUFFER Multiplexer INC/DEC ADDRESS LATCH Reg.Select PC SP B C D E H L W Z A L U 74373 LATCH 8-BIT INTERNAL BUS ALE RDWR 8085 MICRO-ARCHITECTURE S1 S0 IO/M CLK OUT READY HLDA HOLD RESET OUT RESET IN (16) SIDSODTRAPRST 5.5,6.5,7.5INTAINTR A15 - A8 AD7 - AD0 A7-A0 8-BIT INTERNAL BUS Prepared By Rishikesh Bhavsar
- 17. TEMP REG ACC FLAGS INSTRUCTION DECODER AND MACHINE CYCLE ENCODING INSTRUCTION REG INTERUPT CONTROL SERIAL I/O CONTROL TIMING AND CONTROL ADDRESS BUFFER DATA/ADDRESS BUFFER MUX PC SP INC/DEC ADDRESS LATCH Reg.Select 2 0 B C D E H L W Z MEMORY ALU ADDRESS BUS LATCH 0 5 DATA BUS 8-BIT INTERNAL BUS 4F 4FMOV C, A 4FH 4F 8-BIT INTERNAL BUS Prepared By Rishikesh Bhavsar
- 18. MOV B,D copy (B) (D), PC=2000H Prepared By Rishikesh Bhavsar
- 19. T1 T2 T3 T4 ALE CLOCK A7-A0 00H 42H opcode Opcode Fetch Machine Cycle A15-A08 20H Higher Order Address Bus Unspecified Status Prepared By Rishikesh Bhavsar
- 20. MVI L , A6h Prepared By Rishikesh Bhavsar
- 21. CLOCK A15-A08 09H Unspecified T1 T2 T3 T4 ALE A7-A0 25H 2EH Opcode M1(Opcode Fetch ) Status T1 T2 T3 26H A6H Data M2(Memory Read) 09H Prepared By Rishikesh Bhavsar
- 22. M1(Opcode Fetch ) M2(Memory Read) Prepared By Rishikesh Bhavsar
- 23. MVI M , 85h Prepared By Rishikesh Bhavsar
- 24. CLOCK A15-A08 0CH Unspecified T1 T2 T3 T4 ALE A7-A0 A8H 36H M1(Opcode Fetch ) Status T1 T2 T3 A9H 85H M2(Memory Read) 0CH T1 T2 T3 8DH 85H M3(Memory Write) FCH Prepared By Rishikesh Bhavsar
- 25. Prepared By Rishikesh Bhavsar
- 26. STA 2065H GIVEN PC=2010H, A=23H • Gaonkar pg.114-115 Prepared By Rishikesh Bhavsar
- 27. • IDENTIFY THE NUMBER OF BYTES OF FOLLOWING INSTRUCTION? 1. MVI B, 80H 2. LDA 2006H 3. LXI B,2078H 4. IN 08H 5. INX H • WAP of addition of 16 bit with carry. Take random memory location to store your result. • List the four operation commonly performed by the MPU. • Define following term a. Bus b. Flag c. Assembler d. Compiler • How many memory location can be addressed by an MP with 12 address lines? • How many address line are necessary to address two megabyte of memory? • The memory address of the last location of an 8K byte memory chip is EFFFH. Determine starting address.? Prepared By Rishikesh Bhavsar