Interfacing of 8051 with 8255 Programmable Peripheral Interface.pdf
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The document discusses interfacing the 8051 microcontroller with the 8255 Programmable Peripheral Interface (PPI). It explains that the 8051 has limited I/O ports, so the 8255 is used to provide additional ports (Port A, B, C). It describes the components needed, including the 8051, 8255, decoder and logic gates. It provides the address mapping for the 8255 ports and the control logic design. An algorithm and assembly code example is given to read inputs from 8255 Port A and B, add the values, and output the result to Port C.
Interfacing of 8051 with 8255 Programmable Peripheral Interface.pdf
- 1. Interfacing of 8051 with 8255 PPI T.Srikrishna, M.Sc, M.Tech, GVP. Interfacing of 8051 with 8255 Programmable Peripheral Interface Why do we need to interface 8255 PPI with 8051? Why do we need additional pins when we have enough on the 8051 already? For some applications, it is always recommended to use 8255 PPI to avoid data loss and damage to the microcontroller. The 8051 has four ports: Out of four ports Port 0, Port 2, Port 3 – all these ports also have alternate functions. But Port 1, this is the only port with no alternate functions. This is the reason why we need to interface 8255 to provide an additional three ports, namely Port A, Port B, and Port C. and the best part about the 8255 is that it is programmable. Components Required 1. 8051 Microcontroller. 2. 8255 Programmable Peripheral Interface 3. Decoder circuit – 74LS373 (for address demultiplexing) 4. NAND gate IC – 74LS00 5. NOT gate IC – 74LS04 Chip Select Logic For a microcontroller to interface with 8255, a LOW pulse is given to the Chip Select pin of 8255 as it is an active low pin Let’s allot the address to the ports of 8255 PPI Port A: 0010 0000 (20H) Port B: 0010 0001 (21H) Port C: 0010 0010 (22H) Control port: 0010 0011 (23H)
- 2. Interfacing of 8051 with 8255 PPI T.Srikrishna, M.Sc, M.Tech, GVP. Note that here only the last two bits – A0 and A1, are changed to select different ports. Hence, we can design a combinational logic circuit using a NAND gate for which the input will be A2 – A7 address lines and CS’ as the output. The output of the NAND gate is LOW only when ALL the inputs are HIGH. Therefore, from the address allocations that we have done, we have: A7 = 0, A6 = 0, A5 = 1, A4 = 0, A3 = 0, A2 = 0 Algorithm Step 1: Construct the control word register D7 = 1, this will make sure that all the ports of 8255 PPI are in the I/O mode. D6 = D5 = D2 = 0: selects mode 0 for Port A, Port B, and Port C. D4 = D1 = 1: To select Port A and Port B as input ports. D3 = D0 = 0: To select both lower and upper Port C as output port. Step 2: Input the data from Port A and Port B Step 3: Add the contents of port A and port B Step 4: Display the result in port C
- 3. Interfacing of 8051 with 8255 PPI T.Srikrishna, M.Sc, M.Tech, GVP. Circuit Diagram to interface 8255 PPI with 8051 Assembly Language Program to interface 8255 with 8051 PORTA EQU 0020H PORTB EQU 0021H PORTC EQU 0022H CNTPORT EQU 0023H; ORG 0000H MOV A, #92H MOV DPTR, #CNTPORT MOVX @DPTR, A
- 4. Interfacing of 8051 with 8255 PPI T.Srikrishna, M.Sc, M.Tech, GVP. MOV DPTR, #PORTA MOVX A, @DPTR MOV R0, A MOV DPTR, #PORTB MOVX A, @DPTR MOV R1, A MOV A, R0 ADD A, R1; MOV DPTR, #PORTC MOVX @DPTR, A END **Note: For Referece
- 5. Interfacing of 8051 with 8255 PPI T.Srikrishna, M.Sc, M.Tech, GVP.