SPICE MODEL of IRG4IBC20KD (Standard+FWDP Model) in SPICE PARK
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The document is a device modeling report for an insulated gate bipolar transistor (IGBT) part number IRG4IBC20KD, including various circuit simulation results and evaluations. It covers characteristics such as transfer, fall time, saturation, forward current, junction capacitance, and reverse recovery metrics, comparing measurement and simulation results with associated errors. All data is attributed to Bee Technologies Inc., copyright 2004.
![Fall Time Characteristics
Circuit Simulation result
Evaluation circuit
V3
0Vdc
R1
R2 53
U1 U2
50
V1 = 0 DIRG4IBC20KD
V4 IRG4IBC20KD V2
V2 = 15 480Vdc
TD = 0
TR = 10n
TF = 10n
PW = 5u
PER = 100m
0
Test condition Ic=9(A) ,Vcc=480(V)
Measurement Simulation
tf
72[Typ.]~110[Max.] ns 104.41 ns
All Rights Reserved Copyright (C) Bee Technologies Inc. 2004](https://image.slidesharecdn.com/irg4ibc20kdsfwdp-110211020406-phpapp01/85/SPICE-MODEL-of-IRG4IBC20KD-Standard-FWDP-Model-in-SPICE-PARK-5-320.jpg)
SPICE MODEL of IRG4IBC20KD (Standard+FWDP Model) in SPICE PARK
- 1. Device Modeling Report COMPONENTS: Insulated Gate Bipolar Transistor (IGBT) PART NUMBER: IRG4IBC20KD MANUFACTURER: International Rectifier *REMARK: Free-Wheeling Diode (Professional Model) Bee Technologies Inc. All Rights Reserved Copyright (C) Bee Technologies Inc. 2004
- 2. Pspice model Model description parameter TAU Ambipolar Recombination Lifetime KP MOS Transconductance AREA Area of the Device AGD Gate-Drain Overlap Area WB Metallurgical Base Width VT Threshold Voltage KF Triode Region Factor CGS Gate-Source Capacitance per Unit Area COXD Gate-Drain Oxide Capacitance per Unit Area VTD Gate-Drain Overlap Depletion Threshold All Rights Reserved Copyright (C) Bee Technologies Inc. 2004
- 3. Transfer Characteristics Circuit Simulation result Evaluation circuit V3 0Vdc V2 10Vdc U1 U2 DIRG4IBC20KD IRG4IBC20KD V1 0Vdc 0 All Rights Reserved Copyright (C) Bee Technologies Inc. 2004
- 4. Comparison Graph Circuit Simulation Result Simulation Result Test condition : Vce = 10 V Vge(V) Ic(A) Error (%) Measurement Simulation 1 6.380 6.380 -0.002 2 6.660 6.652 -0.114 5 7.190 7.199 0.127 10 7.830 7.826 -0.054 All Rights Reserved Copyright (C) Bee Technologies Inc. 2004
- 5. Fall Time Characteristics Circuit Simulation result Evaluation circuit V3 0Vdc R1 R2 53 U1 U2 50 V1 = 0 DIRG4IBC20KD V4 IRG4IBC20KD V2 V2 = 15 480Vdc TD = 0 TR = 10n TF = 10n PW = 5u PER = 100m 0 Test condition Ic=9(A) ,Vcc=480(V) Measurement Simulation tf 72[Typ.]~110[Max.] ns 104.41 ns All Rights Reserved Copyright (C) Bee Technologies Inc. 2004
- 6. Gate Charge Characteristics Circuit Simulation result Evaluation circuit V3 0Vdc D1 9Adc I2 Dbreak U1 U2 PER = 1m W1 DIRG4IBC20KD PW = 500u + IRG4IBC20KD V2 TF = 10n - TR = 10n TD = 0 W 400Vdc I2 = 2m IOFF = 100uA I1 = 0 I1 ION = 0A 0 Test condition : Vcc=400(V) ,Ic=9(A) ,Vge=15(V) Measurement Simulation Error(%) Qge 5.00 nc 5.00 nc 0.00 Qgc 14.00 nc 14.05 nc 0.38 Qg 34.00 nc 33.36 nc -1.87 All Rights Reserved Copyright (C) Bee Technologies Inc. 2004
- 7. Saturation Characteristics Circuit Simulation result Evaluation circuit V3 0Vdc 0Adc U1 U2 I1 DIRG4IBC20KD IRG4IBC20KD V1 15Vdc 0 All Rights Reserved Copyright (C) Bee Technologies Inc. 2004
- 8. Comparison Graph Circuit Simulation Result Simulation Result Vce(sat)(V) Ic(A) Error (%) Measurement Simulation 1 1.415 1.316 -6.982 2 1.595 1.595 0.000 5 1.920 1.920 0.010 10 2.400 2.400 0.004 All Rights Reserved Copyright (C) Bee Technologies Inc. 2004
- 9. Forward Current Characteristic Circuit Simulation Result Evaluation circuit R1 10m V1 U1 0Vdc DIRG4IBC20KD 0 All Rights Reserved Copyright (C) Bee Technologies Inc. 2004
- 10. Comparison graph Circuit Simulation Result Simulation Result Vfwd(V) Vfwd(V) Ifwd (A) %Error Measurement Simulation 0.1 0.700 0.701 0.168 0.2 0.775 0.778 0.401 0.5 0.900 0.905 0.537 1 1.010 1.021 1.129 2 1.135 1.155 1.797 5 1.335 1.385 3.723 All Rights Reserved Copyright (C) Bee Technologies Inc. 2004
- 11. Junction Capacitance Characteristic Circuit Simulation Result Evaluation circuit V1 = 0 V2 = 100 V2 TD = 0 DIRG4IBC20KD TR = 1u TF = 1u U1 PW = 1u PER = 10u 0 All Rights Reserved Copyright (C) Bee Technologies Inc. 2004
- 12. Comparison graph Circuit Simulation Result Simulation Result Cj(pF) Cj(pF) Vrev (V) %Error Measurement Simulation 2 210.890 209.108 -0.845 5 132.930 135.111 1.641 10 91.990 95.155 3.441 20 65.774 66.396 0.946 50 41.300 40.853 -1.082 100 29.880 28.244 -5.475 All Rights Reserved Copyright (C) Bee Technologies Inc. 2004
- 13. Reverse Recovery Characteristic Circuit Simulation Result Evaluation circuit R1 50 V1 = -9.5 V2 = 10.75 TD = 0 V2 U1 TR = 10n TF = 10n DIRG4IBC20KD PW = 10u PER = 50u 0 Compare Measurement vs. Simulation Measurement Simulation Error(%) trj 20.80 ns 20.71 ns -0.39 trb 56.80 ns 57.77 ns 1.70 All Rights Reserved Copyright (C) Bee Technologies Inc. 2004
- 14. Reverse Recovery Characteristic Reference Measurement trj=20.8(ns) trb=56.8(ns) Conditions:Ifwd=Irev=0.2(A),Rl=50 Example Relation between trj and trb All Rights Reserved Copyright (C) Bee Technologies Inc. 2004