IRJET - 5G Architecture using GAN based Digital Transmitter in VLSI Design for Low Pass Filter
This document discusses the design of a 5G architecture using a fully digital transmitter chain with a GaN-based digital power amplifier and low pass filter in VLSI design. A digital transmitter chain converts the baseband signal into a binary bit stream, which is amplified and filtered to reconstruct the analog output signal. The transition to a fully digital design approach allows for reduced size, increased reconfigurability, improved frequency flexibility and power savings compared to traditional analog transmitters. The key components discussed are the switch-mode power amplifier using GaN, a output low pass filter to reconstruct the analog signal from the amplified binary output, and a modulator implemented using digital logic for high efficiency and integrated digital predistortion capabilities. Simulation results show the design
