KAIST_Lecture_regulators_regarding linear dropout

2023 최신 반도체 집적회로 설계기술 워크샵
Low-Dropout (LDO) Voltage Regulators
– From Basics to Recent Design Trends
(presented in A-SSCC 2022)
Prof. Hyun-Sik Kim
(hyunskim@kaist.ac.kr)
November 22, 2023
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 1 of 94

Contents
 Basics of LDO Regulator
 Key Performance Metrics & LDO Configurations
 Frequency Response & Stability
 Fast Transient-Response LDO Designs
 Power Supply Rejection (PSR)
 Energy-Efficient Ultra-Low-Dropout (Triode) LDO
 Conclusion

Contents
 Conclusion

What is the Voltage Regulator?
 Ideal Regulator?: an voltage source (VOUT) used to be VDD of a load system
 Keep VOUT fixed voltage under any situations
◼ VIN varies, but VOUT is fixed → Regulator’s Line Regulation
◼ ILOAD varies, but VOUT is fixed → Regulator’s Load Regulation
 Always “VIN > VOUT” due to the LDO’s resistive voltage generation
VIN
VOUT
ILOAD
Regulator
LDO, Buck: VIN > VOUT
Boost: VIN < VOUT
VIN
VOUT
Fixed (Regulated) LDO input
LDO output
time

Key Features of LDO Regulator
 Ripple Suppression (Power-Supply Rejection, PSR) → Used as a Post-Regulator
 Impedance Isolation (Low ZOUT like as a buffer )
 Low Output Noise (No switching operation) → Useful for noise-sensitive loads
Battery Switching
DC-DC
Converter
LDO
Regulator
w/ High-PSR
LDO
Regulator
w/ Low-PSR
Image
Sensor
#2
Image
Sensor
#1
high fsw @ heavy load
low fsw @ light load
ΔVRIPPLE
L size → fsw
VDD1
VDD2
Clear
Noisy
Noise-sensitive load
L size ↓ → fsw ↑

Usages of LDO Regulator
 Discrete LDO chips
Velodyne LIDAR Puck VLP-16 Sensor
(source: Tech Insights)
 SoC-Integrated LDO IPs
AMD 7-nm Zen 2
(ISSCC’20)
◼ Clean voltage-supply (low-noise of LDO)
◼ Step-down DC-DC conversion
◼ Per-Core voltage-scaling (compactness)
LDO (TI)
LDO
(Microchip)
LDO
(Microchip)
Integrated LDOs

Conceptual Realization of LDO Regulator (1/2)
VIN RL
RIN
+
VOUT
VOUT-sense
& α-control
L
OUT IN
IN L
R
V V
R R
=
+ OUT IN
1
V V
α 1
=
+
 Unregulated ☺ Regulated
 VOUT generated using a resistive divider
◼ Fixed divider ratio → sensitive to load current (RL) changes
 Feedback loop regulates RIN (= α·RL) such that it is always a desired fraction
of load current
◼ VOUT is independent to load current (RL)
VIN RL
α·
RL
+
VOUT

Conceptual Realization of LDO Regulator (2/2)
 Feedback loop adjusts RIN such that
◼ VOUT is ideally independent to VIN
◼ Feedback resistors (RF1 + RF2) >> RL
VIN RL
RIN
+
VOUT
+
EA
VREF
RF1
RF2
CL
Pass Element (transistor)
F1 F2
OUT REF
F2
R R
V V
R
 
+
=  
 

Comparison of Power Converter Topologies (1/2)
Linear Regulator
(LDO)
Switched Inductor
DC-DC
Switched Capacitor
(e.g., Charge-Pump)
Transfer
Media
Resistive Inductive Capacitive
Efficiency Low  High ☺ Medium
Noise
Very Low ☺
(no switching)
High  Medium
Output
Current
Low to Medium Low to High Low
Step-Up X O O
Step-Down O O O
Footprint Small ☺ Large  Medium

Comparison of Power Converter Topologies (2/2)
CPU @ 24MHz CPU @ 48MHz
LDO Regulator 165 μA/MHz 158 μA/MHz
Switched Inductor
DC-DC
92 μA/MHz 96 μA/MHz
 LDO regulator: small footprint & low noise, but low efficiency

Basic Architecture of LDO Regulator
PMOS Pass
Element
VIN
+
BGR
VREF
R1
R2
CL IL
VOUT
rDS
EA VDO = VIN – VOUT
Dropout Voltage
+
–
1 2
OUT REF
2
R R
V V
R
 
+
=  
 
◼ Bandgap (BGR): fixed reference voltage VREF
◼ Error-Amplifier (EA): comparing VREF vs. VOUT, and providing feedback loop-gain (T)
◼ CL: used to “filter” ripple and noise

Contents
 Conclusion

Key Performance Metrics
 Regulation (in DC-domain)
◼ Line/load regulation
 Voltage (VOUT) accuracy
 Transient response
◼ Voltage droop & Recovery time
◼ Loop-bandwidth (GBW)
◼ Slew rate
 Dropout voltage (VDO)
◼ Power efficiency
 Input/output range
◼ Input (VIN) range
◼ Output (VOUT) range
◼ Max. output current (IL,MAX)
 Quiescent current (IQ)
◼ Current efficiency
 Power supply rejection (PSR)
 Stability
◼ Load (IL) dynamic range
◼ Output capacitor (CL)
 Output noise
◼ RMS noise voltage within BW

Performance Metrics: Line Regulation (1/2)
 Ability to maintain desired VOUT with varying VIN
◼ Line Regulation = ΔVOUT/ΔVIN
◼ Unit: [mV/V] or [%/V]
(source: TI tech. review)

Performance Metrics: Line Regulation (2/2)
 Line Regulation =
( )
( )
mp L DS 1 2
OUT
IN EA0
EA0 mp L DS 1 2
g R ||r || R R
ΔV 1
ΔV βA
1 βA g R ||r || R R
 
+
 
= 
 
+ +
 
PMOS Pass
Element
VIN
+
BGR
VREF
R1
R2
CL IL
VOUT
rDS
EA
AEA0
gmp
2
1 2
R
β
R R
=
+
( ) ( )
IN OUT EA0 mp L DS 1 2 OUT
ΔV ΔV βA g R ||r || R R ΔV
 
−  + =
 
+
–
 Changes in VIN suppressed by error-amp (EA)’s gain (AEA0)

Performance Metrics: Load Regulation
 Ability to maintain desired VOUT with varying IL
PMOS Pass
Element
VIN
+
BGR
VREF
R1
R2
CL IL
VOUT
rDS
EA
AEA0
gmp
2
1 2
R
β
R R
=
+
( )
OUT
L OUT EA0 mp
DS 1 2
ΔV
ΔI ΔV β A g
r || R R
= +   
 
+
 
 Load Regulation =
( )
( )
DS 1 2
OUT DS
L 0
EA0 mp DS 1 2
r || R R
ΔV r
ΔI 1 T
1 βA g r || R R
+
= 
+
 
+ +
 
 Dependent of feedback loop-gain (T0)

Performance Metrics: Voltage Accuracy
◼ Line/Load regulation: ΔVLR, ΔVLDR
◼ Reference voltage drift: ΔVO,REF
◼ Error-Amp offset drift: ΔVO,EA
◼ Feedback resistor tolerance: ΔVO,R
PMOS Pass
Element
VIN
+
BGR
VREF
R1
R2
CL IL
VOUT
rDS
EA
 LDO’s accuracy =  
2 2 2
LR LDR O,REF O,EA O,R
OUT
ΔV ΔV ΔV ΔV ΔV
%
V
+ + + +

Performance Metrics: Power Efficiency (η)
 Efficiency (η) =
PMOS Pass
Element
VIN
+
BGR
VREF
R1
R2
CL IL
VOUT
rDS
EA
IIN
IQ
Quiescent current
(ground current)
IL
( )
( )
( )
IN DO L
OUT L OUT L
IN IN IN L Q IN L Q
V V I
V I V I
[%]
V I V I I V I I
− 
 
= =
  +  +
VDO = VIN – VOUT = VDS of PMOS
Dropout Voltage
+
–

Performance Metrics: Min. Dropout (VDO,min)
PMOS Pass
Element
VIN
+
BGR
VREF
R1
R2
CL IL
VOUT
rDS
EA VDO = VIN – VOUT
+
–
≈ 0
VG
VDO,min
 Min. dropout voltage (VDO,min): minimum regulating point @ full-load (IL,max)
◼ At VDO,min & IL,max, the EA’s output (VG) reaches the minimum limit (≈ 0V)
◼ Conventional LDOs have VDO,min of 50mV ~ 200mV
◼ High aspect ratio (W/L) of pass element → large parasitic capacitance (CG) 

Performance Metrics: Power-Supply Rejection
PSR
(V
OUT
/V
IN
)
[dB]
fsw
0 dB
Lower is Better
Typical
LDO PSR
VIN VOUT
fLow fMid fHigh
LDO
Regulator
ΔVIN(fsw)
ΔVOUT(fsw)
More
Desirable
highly rejected
reduced
rather amplified
 Power-supply rejection = OUT
IN
ΔV (f)
PSR(f)
ΔV (f)
=
◼ Similar to line regulation, but measured ∆VOUT for small-signal ∆VIN variations
◼ PSR = ripple rejection capability

Performance Metrics: Transient Reponses
Voltage dip/spike
Line Regulation
Voltage dip/spike
Load Regulation
 Line (∆VIN) transient response  Load (∆IL) transient response
◼ ∆VOUT is dependent of load-step(∆IL), CL, loop bandwidth (GBW), and slew rate (SR)

Various Types of LDO (1/4)
VIN RL
RIN
+
VOUT
+
EA
VREF
RF1
RF2
CL VIN RL
+
VOUT
+
EA
VREF
RF1
RF2
CL
Variable CS
 Triode LDO  Saturation LDO
◼ Pass element works in triode region
◼ Small VDO (high η) ☺
◼ Low regulation due to low loop-gain
(T) 
◼ Bad PSR due to small RDS 
◼ Normally not preferred
◼ Pass element works in saturation region
◼ High VDO (lower η) 
◼ Good regulation performance due to
high loop-gain (T) ☺
◼ Good PSR owing to large RDS ☺
◼ Adopted in most LDOs

 P-type LDO  N-type LDO
◼ Pass element = PMOS
◼ Better regulation performance
(higher loop-gain) ☺
◼ Stability design issue 
◼ Pass element = NMOS
◼ Lower regulation performance 
◼ Easier stability design ☺
◼ Additional charge-pump (VDD) 
PMOS Pass
Element
VIN
+
VREF
R1
R2
CL IL
VOUT
EA NMOS Pass
Element
VIN
+
VREF
R1
R2
CL IL
VOUT
EA
CP
VDD >VIN

 Cap LDO  Capless LDO
◼ External capacitor (CL) is required
◼ Larger PCB footprint 
◼ Low voltage droop @ ∆IL ☺
◼ Good PSR @ high freq. ☺
◼ Narrow bandwidth 
◼ Stability issue over wide IL 
◼ No “external” component (CL)
◼ Compact or fully-integrated ☺
◼ High voltage droop @ ∆IL 
◼ Bad PSR @ high freq. 
◼ Wider (faster) bandwidth 
◼ Easier stability compensation ☺
VIN RL
RIN
+
VOUT
+
EA
VREF
RF1
RF2
CL VIN RL
RIN
+
VOUT
+
EA
VREF
RF1
RF2

 Analog LDO  Digital LDO
◼ Analog control & single pass-TR.
◼ Excellent PSR ☺
◼ No ripple & clean VOUT ☺
◼ Re-design @ different tech. nodes 
◼ Hard to work in low VIN 
◼ Digital control & segmented pass-TR.
◼ Scalable design @ various CMOS tech. ☺
◼ Digitally synthesizable ☺
◼ Limit cycle oscillation (LCO) ripple 
◼ Friendly to low VIN ☺

Contents
 Conclusion

Feedback Loop-Gain’s Transfer Function: T(s)
VIN
+
BGR
VREF
R1
R2
CL IL
VOUT
rDS
EA
Cgg
gmp
rEA
gmEA
VX
VY
( ) Y
EA mp OUT
X
P1 P2
V 1
T s A g R β
V s s
1 1
ω ω
= − =  
  
+ +
  
  
( )
EA mEA EA
OUT DS 1 2 L
2
1 2
A g r
R r || R R ||R
R
β
R R
=
= +
=
+
ωP2
ωP1
P2
EA gg
1
ω
r C
=

P1
OUT L
1
ω
R C
=

 Transfer function of feedback loop-gain:
, where
*Note: Cgg becomes higher for low VDO & high IL

Basics of Frequency Response
VIN
+
BGR
VREF
R1
R2
CL IL
VOUT
rDS
EA
Cgg
gmp
rEA
gmEA
VX
VY
ωP2
ωP1
ω [rad/s]
Loop
Gain
[dB]
X
0 mEA EA mp OUT
T β g r g r
=  
X
P1
ω
P2
EA gg
1
ω
r C
=

UGF
ω
P2
ω
|
P1
OUT L
1
ω
r C
=

 Unity-gain frequency (ωUGF, GBW) determines the LDO’s transient response
◼ Wide bandwidth (high ωUGF) = fast transient speed
 Closely-spaced poles compromise stability
◼ “ωUGF ≤ non-dominant pole” is desirable: just 1-pole under ωUGF
◼ Frequency (stability) compensation is necessary

Load Current (IL) Dependency of Output Pole
VIN
+
BGR
VREF
R1
R2
CL IL
VOUT
rDS
EA
Cgg
gmp
rEA
gmEA
VX
VY
 Why cap-LDO (w/ CL) is difficult to be stable?
◼ Load current (IL) variation significantly changes the pole of ωP1
ωP1
ω [rad/s]
Loop
Gain
[dB]
X X
P1
ω UGF
ω
P2
ω
|
L
P1
OUT L A L
I
1
ω
r C V C
= =
 
|
UGF
ω
X
P1
ω
0 mEA EA mp OUT
T β g r g r
=  
Heavy load (high IL)
Light load (low IL)
 Total ROUT (open-loop) = ( )
OUT DS 1 2 L
R r || R R ||R
= +
L
P1
OUT L DS L A L
I
1 1
ω
R C r C V C
=  =
  

Stability Compensation I: Zero-Insertion (1/3)
VIN
+
BGR
VREF
R1
R2 CL
IL
VOUT
rDS
EA
Cgg
gmp
rEA
gmEA
ESR
ωP2
ωP1
ω [rad/s]
Loop
Gain
[dB]
X
0 mEA EA mp OUT
T β g r g r
=  
X
P1
ω
Z
ESR L
1
ω
R C
=

UGF
ω
P2
ω
|
O
Z
ω
P2
EA gg
1
ω
r C
=

P1
OUT L
1
ω
R C
=

Z
ESR L
1
ω
R C
=

1 UGF
Z
ω
PM tan
ω
−  
  
 
 Zero (ωZ) insertion by adding ESR (equivalent series resistance) in CL

 Choose the right ESR to secure the phase margin
ω
Loop
Gain
[dB]
X X
P1
ω
UGF
ω
P2
ω
|
O
Z
ω
ω [rad/s]
Loop
Gain
[dB]
X X
P1
ω
UGF
ω
P2
ω
|
w/o ESR compensation  w/ ESR compensation (desirable) ☺
X
P3
ω
ω
Loop
Gain
[dB]
X X
P1
ω
UGF
ω
P2
ω
|
O
Z
ω
w/ too high ESR (unstable) 
X
P3
ω
ω
Loop
Gain
[dB]
X X
P1
ω UGF
ω
P2
ω
| O
Z
ω
w/ too low ESR (unstable) 
Stable region of ESR

 Tunnel-of-Death graph: desirable range of stable ESR
◼ ESR on CL may cause a large spike/dip at load transient response 
Kim & Kim, IEEE TPEL 2020 Texas Instrument, LDO

Stability Compensation II: Gate Buffering
 Shield Cgg from loading the error-amplifier output using a Buffer
VIN
+
BGR
VREF
R1
R2
CL IL
VOUT
rDS
EA
Cgg
RO,EA
VEA VG
RB
Buffer
B O,EA
Buffer R R
◼ w/o gate buffering: P2
gg O,EA
1
ω
C R
=
P2,A
B O,EA
1
ω
C R
= P2,B
gg B
1
ω
C R
=
(low-frequency one pole)
(high-frequency two poles)
◼ w/ gate buffering:
B gg
Buffer C C

SSF-based Gate Buffer Design (1/3)
 Gate buffer design with Super Source Follower (SSF)
B
mB SSF mB mS X
1 1 1 1
R
g T g g r
=  = 
ωG = gmB/Cgg
ωX = 1/(rXCX)
 Local feedback loop further reduces RB by loop-gain (TSSF)
 SSF loop-gain (TSSF) has closely-spaced two poles: ωG & ωX
◼ Local stability should be also considered in the design of SSF-based gate buffer 

 AC-peaking at SSF output
B
mB SSF
1 1
R
g T (s)
= 
ωG = gmB/Cgg
ωX = 1/(rXCX)
ω
Output
Z
(R
B
)
[Ω]
X
mB SSF,DC
1 1
g T
ω
Loop
Gain
[dB]
SSF
T (s)
UGF
ω
|
X
X
ω
X
G
ω
G SSF
EA SSF
V T (s)
(s)
V 1 T (s)
=
+
AC-peaking
(ΔPhase ≈ 180°)
AC-peaking ➔
Complex pole-pair effect at VG/VEA(s) 
Dominant-pole of TSSF loop
mB
1
g
( ) 
SSF UGF
T jω 1
Cgg
RB(s)
gg
1
jωC
SSF,DC mS X
T g r
=
◼ Impedance analysis
◼ Closed-loop analysis

 AC-peaking solution: Capacitive impedance (1/sCgg) does not cross the inductive RB
ω
Output
Z
(R
B
)
[Ω]
X
mB SSF,DC
1 1
g T
ω
Loop
Gain
[dB]
SSF
T (s)
UGF
ω
|
X
X
ω
X
G
ω
G
EA
V
(s)
V
AC-peaking
(ΔPhase ≈ 180°)
mB
1
g
( ) 
SSF UGF
T jω 1
Cgg
RB(s)
ω
Output
Z
(R
B
)
[Ω]
X
ω
Loop
Gain
[dB]
SSF
T (s)
|
X
X
ω
X
G
ω
G
EA
V
(s)
V
No AC-peaking
(ΔPhase ≈ 90°)
mB
1
g
( ) 
SSF UGF
T jω 1
gg
1
jωC
Unstable Case  Stable Case ☺
mS
X
g
C
X X
1
r C
=
mB
gg
g
C
=
gg
1
jωC

Dual-Loop Gate Buffer Design (1/4)
 Kim & Kim, IEEE TPEL 2020
VBP
Cgg
MP
M19
M21
M18
VBI
Power
PMOS
VIN
VOUT
IB2
M22
VG
VBN
M20
Cp
LM
Loop-Gain
ω
0 dB
X
X
Original LM
ωp1 ωp2
gm21·
rds20
ωt
ω
-90°
0°
-180°
Phase
Original LM
◼ Conventional SSF-based gate buffer
◼ Single-loop (LM)
◼ Two poles are closely spaced → instability issue & GBW (ωt) limit

◼ Insertion of RS and CS
◼ CS works for dominant-pole compensation (ωp2 ➔ ωp2’)
◼ RS introduces a zero (ωz1)
VBP CS
RS
Cgg
MP
M19
M21
M18
VBI
Power
PMOS
VIN
VOUT
IB2
M22
VG
VBN
M20
Cp
LM
Loop-Gain
LM
ω
0 dB
X
X
Original LM
ωp1 ωp2
ωz1
ωp2'
gm21·
rds20
gm21·
(rds20||RS) ωt
ω
-90°
0°
-180°
Phase
Original LM
ωp3
X
O

◼ An additional loop of LS forms and co-exists with LM-loop
◼ Dual-loop design (LM + LS)
VBP CS
RS
Cgg
MP
M19
M21
M18
VBI
Power
PMOS
VIN
VOUT
IB2
M22
VG
VBN
M20
Cp
LM
LS
VB
Loop-Gain
LM
ω
0 dB
LS
ωp1
ωz1
ωp2'
gm21·
rds20
gm19·
(rds20||RS)
gm21·
(rds20||RS) ωt'
ω
-90°
0°
-180°
Phase
Original LM
ωp3

◼ Low-frequency region dominated by LM
◼ LS covers high-frequency region
◼ Proposed dual-loop offers faster response (ωt’) with higher stability (PM ≈ 90º) ☺
VBP CS
RS
Cgg
MP
M19
M21
M18
VBI
Power
PMOS
VIN
VOUT
IB2
M22
VG
VBN
M20
Cp
LM
LS
VB
Loop-Gain
LM
ω
0 dB
X
X
LS
(LS+LM)
Original LM
X
X
O
ωp1 ωp2
ωz1
ωp2'
gm21·
rds20
gm19·
(rds20||RS)
gm21·
(rds20||RS) ωt ωt'
ωzc
ω
-90°
0°
-180°
Phase
(LS+LM)
Original LM
ωp3

Stability Compensation III: Miller Effect (1/2)
gm
1
+
CA
rO1
COUT
RL
gm
P
+
IB
CM
α
Atten.
ITH
M1
M2
MB
1/IB
VOUT
R1
R2
VREF
ω
0 dB
X
X
Loop-Gain
ωP1
ωP2
@ IL > 0
 Miller compensation (pole-splitting) by CM is one of viable options in LDO design
◼ Dominant pole:
◼ Non-dominant pole:
( )

 +
P1
O1 mp OUT M
1
ω
r 1 g R C
 mp
P2
L
g
ω
C
ωP1
ωP2

Stability Compensation III: Miller Effect (2/2)
gm
1
+
CA
rO1
COUT
RL
gm
P
+
IB
CM
α
Atten.
ITH
M1
M2
MB
1/IB
VOUT
R1
R2
VREF
IL
ω
0 dB
X
X
Loop-Gain
ωP1
ωP2
ω
0 dB
X
X
Loop-Gain
ωP1
ωP2
@ IL 0
@ IL > 0
X
0
 No Miller-Effect issue at deep light loads
◼ At light-load (IL ≈ 0) → gmp ≈ 0 (no gain in Pass-Element) → No Miller Effect
◼ Miller compensation is difficult to cover IL ≈ 0 
◼ Otherwise, large static current via R1 and R2 must be consumed 
No Miller Effect

Stability Compensation III: Miller w/ LLSL (1/3)
 Kim & Kim, VLSI 2019
80°
60°
40°
20°
Phase
Margin
(PM)
100°
Load Current IL (log-scale)
200mA
20mA
2mA
0.2mA
20μA
2μA
LLSL on
LLSL off
with COUT = 1μF
IL,trip ≈ 4mA
PMmin
≥ 40°
@IL 0
gm
1
+
CA
rO1
COUT
RL
gm
P
+
IB
CM
α
Atten.
ITH
M1
M2
MB
1/IB
VOUT
R1
R2
VREF
IL
ω
0 dB
Loop-Gain
ωP1
ωP2
@ IL 0
X
X
ωP1
 Light-load stabilizer loop (LLSL) w/ Miller
◼ If IL < pre-defined ITH, LLSL is activated and
then IB (= ITH – IL) is added to gm1 to reduce rO1
◼ Proposed LLSL can guarantee sufficient phase margin even at IL ≈ 0 ☺

VBP
VOUT
CM
CA
I
TH
VBP
CS
VBN
VBP
VBN
VREF
VIN
Miller Compensation Loop
Light-Load Stabilizer Loop (LLSL)
gm1
gmC
-A0
rO1
gm2
gm3 gm4
rO4
gm5
gm6
gm
7
Cgg
gmP
gm
8
CF
R1
R2
C
OUT
RL
M1
M2
IB IB VBI
Power
PMOS
IL
rO2
rO6
MB MB
VBP
RS
Load-current (IL) sensor
Compare-and-subtractor
IB-boosting circuit

200
mA/div
20 μs/div
VOUT LLSL On
LLSL Off
t = 10 ns
20
mV/div
Δ0.3 A
Heavy-load
Light-load
IL
@ IL 0
g
m2,3
+
CA
rO1
COUT
RL
g
mP
+
IB1
CM
IL-Sensor
Atten.
ITH
M23
M24
M6,7
1/IB1
~
VOUT
R1
R2
VREF
IL
IM4,5
VO1
◼ At load transition from 300mA to 0A, a ringing is well suppressed by LLSL ☺

Contents
 Conclusion

Understanding Load-Transient Response (1/6)
 Light-to-heavy load transition
Pass-Element
VIN
+
VREF
R1
R2
CL
IL
VOUT
EA
R
ESR
IL,light
VOUT
Load
Current IL,light
IL,heavy
IL,light
◼ At the steady-state, VOUT is stabilized and no current via CL
◼ PMOS’s supply current = Load current = IL,light

◼ A load transition from light to heavy current occurs
◼ Initially CL reacts to cover the current mismatch between PMOS and load
◼ Large voltage droop (∆VESR) appears at VOUT:
Pass-Element
VIN
+
VREF
R1
R2
CL
IL
VOUT
EA
R
ESR
IL,light
VOUT
Load
Current IL,light
IL,heavy
IL,heavy – IL,light
+
VESR
IL,heavy
( )
ESR ESR L,heavy L,light
ΔV R i i
 −

◼ VOUT falls until PMOS current reaches IL,heavy
◼ Voltage-droop period:
◼ Droop voltage:
Pass-Element
VIN
+
VREF
R1
R2
CL
IL
VOUT
EA
R
ESR
IL,light
VOUT
Load
Current IL,light
IL,heavy
Vdip
IL,heavy
BW
SR
Tdip
VG
G
dip SR gg
@light load SR,EA @light load
ΔV
1 1
T T C
BW I BW
− −
 + = + , where TSR = slew time
L,heavy L,light
dip dip ESR
L
i i
ΔV T ΔV
C
−
=  +
*Note: LDO’s loop-BW is dependent of IL

◼ Fine-settling time (Trecover) is dominated by LDO’s loop-BW and phase margin (PM)
◼ VOUT’s DC error after fine-settling is caused by limited load-regulation performance
(insufficient loop-gain in DC-domain)
Pass-Element
VIN
+
VREF
R1
R2
CL
IL
VOUT
EA
R
ESR
VOUT
Load
Current IL,light
IL,heavy IL,heavy
BW
Trecover
VG
Load reg. (DC)
IL,heavy

 Heavy-to-light load transition
Pass-Element
VIN
+
VREF
R1
R2
CL
IL
VOUT
EA
R
ESR
VOUT
Load
Current IL,light
IL,heavy
VG
IL,heavy
IL,light
IL,heavy – IL,light
Vspike
Tspike
IL,light
◼ Overshoot period:
◼ Overshoot voltage:
G
spike SR gg
@heavy load SR,EA @heavy load
ΔV
1 1
T T C
BW I BW
− −
 + = +
L,heavy L,light
spike spike ESR
L
i i
ΔV T ΔV
C
−
=  + Dominated by slew-rate (SR) and BW…

 Heavy-to-light load transition
◼ Typical LDO has no sinking capability (only pull-down path is R1 and R2)
◼ Return-to-base period:
Pass-Element
VIN
+
VREF
R1
R2
CL
IL
VOUT
EA
R
ESR
VOUT
Load
Current IL,light
IL,heavy
VG
IL,light Tdischarge
Load reg. (DC)
spike spike
discharge L L
REF
R2
2
ΔV ΔV
T C C
V
i
R
 =

Figure-of-Merit (FoM)
 Load-transient response
G
dip SR gg
@light load SR,EA @light load
ΔV
1 1
T T C
BW I BW
− −
 + = +
L,heavy L,light
dip dip ESR
L
i i
ΔV ΔT ΔV
C
−
=  +
 LDO’s FoM in terms of load-transient response
L dip Q
2
L,max
C ΔV I
FoM
ΔI
 
=
dip Q
L,max
T I
ΔI


2) FoM shows the efficiencies of SR and BW
against IQ consumption…
1) Pass element’s Cgg needs to be higher to
accommodate larger IL,max

Zero-IQ Ultra-High Slew-Rate Buffer (1/5)
 Koh & Kim, ISSCC’21 & JSSC’21
VI VI+
Mn2
Mp3
Mn3
Mp2
V
OUT
CL
VDZ
I
DCCA
VIN >VDZ = VTH,n2+VTH,p3
MX IX
VX
VIN = VI+ VI-
A
VIN
IDCCA
VDZ
-VDZ
VOUT
Time
VH
VL
VDZ
Type A
VI+
◼ Zero-IQ at steady-state at |∆VIN| < VDZ & Large dynamic current IDCCA ∝ ∆VIN
2 ☺
◼ Dead-zone (VDZ) is too large 

VIN
IDCCA VTH.n
-VDZ VDZ
VOUT
Time
VH
VL
Type B
VI+
VTH,n
VI VI+
Mn2
Mp3
Mn3
Mp2
V
OUT
CL
VTH,n
I
DCCA
VIN > VDZ VTH,n
B
VIN = VI+ VI-
◼ VTH of transistors can be cancelled by inserting the series voltage sources ☺
◼ Dead-zone (VDZ) still remains 

VI VI+
Mn2
Mp3
Mn3
Mp2
V
OUT
CL
VTH,n
I
DCCA
VIN > VDZ VTH,n VR
VR VOUT
Time
VH
VL
Type C
VI+
VR
VIN
IDCCA
VDZ
-VDZ
Decrease
VR
C
VIN = VI+ VI-
◼ Recursive-current-controlled voltage sources are introduced
◼ Near-zero dead-zone (VDZ ≈ 0) ☺ & Ultra-high slewing current (IDCCA) ☺

VI VI+
Mn2
Mp3
Mn3
Mp2
V
OUT
CL
VTH,n
I
DCCA
VIN > VDZ VTH,n VR
VR
C
VIN = VI+ VI-
VI+
VDD
GND
V
OUT
CL
IBD
IBD
Mn2 Mp2
Mp3
Mn3
Mn6
Mp5
Mp4
Mn4 Mn7
Mp7
Mp6
Mp23
Mn23
Mn5
VI-
R
CP
R
CN
Mp1
VRCP
Mn1
VRCN
◼ Mn5-Mn6 & Mp5-Mp6 forms recursive (positive) feedback loops
◼ Near-zero dead-zone (VDZ ≈ 0) ☺ & Ultra-high slewing current (IDCCA) ☺

VI+
VDD
GND
V
OUT
CL
IBD
IBD
Mn2 Mp2
Mp3
Mn3
Mn6
Mp5
Mp4
Mn4 Mn7
Mp7
Mp6
Mp23
Mn23
Mn5
VI-
R
CP
R
CN
Mp1
VRCP
Mn1
VRCN
◼ SR+ (rise) 10.3V/μs at 800pF, SR- (fall) 10.2V/μs at 800pF
◼ IQ consumption = 30nA & Max. slewing current = 9mA (= 300,000 x IQ) ☺
CL = 800pF
4.5V
0.3V SR+ 0.021V/μs
1V SR- 0.03V/μs
100μs
200ns
1V
SR- 10.2V/μs
INPUT
Proposed
SR+ 10.3V/μs

Low-IQ Gm-Boosted OTA Design (1/4)
VI VI+
1
1 : 1 K
:
VOUT
Mp8 Mp9
IB
1 K
:
( )
( ) ( )
IDC [(3+K)/2]·IB
Gm K·gmp
 Typical mirror-type OTA design (A)
◼ Effective Gm can only be amplified by output-stage mirror-ratio (K)
◼ To increase Gm, larger IDC is required (Gm ∝ IDC → low FoM) 

VOUT
1 K
:
1 1
:
VI VI+
Mn8
Mp8 Mn9 Mp9
IB
IB
1 : 1 :
1 K
VNX
VPX
( ) ( )
( )
)
(
IDC (3+K)·IB
Gm K·(gmn+gmp)
 Rail-to-rail mirror-type OTA design (B)
◼ N-type & P-type differential pairs synergies to improve the effective Gm
◼ But, the quiescent current (IDC) is also increased 

Ka
:
1 Kb
: :
1 K
VI VI+ VOUT
Mn8
Mp8 Mn9 Mp9
IB
IB
1 Ka
: Kb
Mn16
Mp16
:
1 K
VNX
Mn14
VPX
:
( ) ( )
( )( )
IDC [2+Kb+K·(1+Kb-Ka)/2]·IB
Gm K·(1+Ka+Kb)·(gmn+gmp)/2
 Proposed low-IQ Gm-boosted OTA design (C)
◼ Signal can be amplified by Ka, but the DC current is reduced by a ratio of Ka ☺
◼ If Ka = Kb = 1 ➔ 1.5x higher Gm compared to (B) for the same IDC

P+ N-
V
OUT
ML1 ML4
1:1
VI- VI+
P-
1:K
Mn14 Mn16
IB
2
(2-K)IB
2
P+ N-
V
OUT
ML1 ML4
1:1
VI-
VI+
IB IB
Gmp
Gmn
Gms
Conventional
(K/2)Gms
Gms
Gm_Eff
Proposed
 Proposed low-IQ Gm-boosted OTA design (C)
◼ Signal can be amplified by K, but the DC current is reduced to (2-K)/2

Contents
 Conclusion

Supply-Ripple Delivery Paths
VIN
+
BGR
R1
R2
C
OUT
VOUT
rDS
Cgg
RL
AEA
gmP
Main Path
(PSRMain)
ωRC
ro,EA
VREF
PSRBGR
TLoop(s)
PSR
[dB]
ω
0 dB
ωP1
ωBW
Main Path
(PSRMain)
Total PSRLDO
ωRC
ωP2
PSRBGR w/i ωRC
PSRBGR w/o ωRC
 Power-supply rejection: PSR(s) = ΔVOUT/ΔVIN
 Supply-ripple delivery paths from VIN to VOUT
◼ Main path: rDS & gmP of power PMOS
◼ Reference path (VREF): limited PSR of the reference (BGR) voltage circuit

Ripple Delivery via rDS: PSR Model (1/6)
VIN
+
BGR
VREF
R1
R2 CL
IL
VOUT
rDS
EA
Cgg
gmp
rEA
gmEA
ESR
( )
LOAD ESR 1 2 L
L
1
Z R || R R ||R
sC
 
= + +
 
 
LOAD DS
CL,OUT
Z || r
Z
T(s)
=
0 EA mp OUT
T A g R β
=  
LOAD CL,OUT
OUT
IN DS LOAD CL,OUT
(Z || Z )
v
PSR(s) (s)
v r (Z || Z )
= =
+
VIN
rDS
Z
LOAD
Z
CL,OUT
VOUT
◼ Open-loop load impedance:
◼ Closed-loop output impedance:
◼ PSR transfer function (via rDS):

LOAD CL,OUT
OUT
IN DS LOAD CL,OUT
(Z || Z )
v
PSR(s) (s)
v r (Z || Z )
= =
+
VIN
rDS
Z
LOAD
Z
CL,OUT
VOUT
VIN
+
BGR
VREF
R1
R2 CL
IL
VOUT
rDS
EA
Cgg
gmp
rEA
gmEA
ESR
( )
LOAD ESR 1 2 L
L
1
Z R || R R ||R
sC
 
= + +
 
 
LOAD DS
CL,OUT
Z || r
Z
T(s)
=
ω [rad/s]
PSR:
V
OUT
/V
IN
[dB]
VIN
rDS
VOUT
RCL,OUT
DC
DC
1
PSR
T
=
1 2 L DS
CL,OUT DC
DC
1 2 L DS
DS CL,OUT DC
DS
DC
(R R )||R || r
R T 1
PSR
(R R )||R || r
r R T
r
T
+
= = 
+
+
+

LOAD CL,OUT
OUT
IN DS LOAD CL,OUT
(Z || Z )
v
PSR(s) (s)
v r (Z || Z )
= =
+
VIN
rDS
Z
LOAD
Z
CL,OUT
VOUT
VIN
+
BGR
VREF
R1
R2 CL
IL
VOUT
rDS
EA
Cgg
gmp
rEA
gmEA
ESR
( )
LOAD ESR 1 2 L
L
1
Z R || R R ||R
sC
 
= + +
 
 
LOAD DS
CL,OUT
Z || r
Z
T(s)
=
ω [rad/s]
PSR:
V
OUT
/V
IN
[dB]
P
ω
DC
DC
1
PSR
T
=
O X
UGF
ω
1
PSR
T(s)

VIN
rDS
Z
CL,OUT
VOUT
VIN
rDS
VOUT
(R
1
+R
2
)||R
L
Assumed that the dominant pole (ωP) ≈ 1/(rEA·Cgg)

LOAD CL,OUT
OUT
IN DS LOAD CL,OUT
(Z || Z )
v
PSR(s) (s)
v r (Z || Z )
= =
+
VIN
rDS
Z
LOAD
Z
CL,OUT
VOUT
VIN
+
BGR
VREF
R1
R2 CL
IL
VOUT
rDS
EA
Cgg
gmp
rEA
gmEA
ESR
( )
LOAD ESR 1 2 L
L
1
Z R || R R ||R
sC
 
= + +
 
 
LOAD DS
CL,OUT
Z || r
Z
T(s)
=
ω [rad/s]
PSR:
V
OUT
/V
IN
[dB]
P
ω
DC
DC
1
PSR
T
=
O X
UGF
ω
1
PSR
T(s)

X
CL
ω
VIN
rDS
VOUT
(R
1
+R
2
)||R
L
CL
ESR
ω
O
VIN
rDS
VOUT
CL
RESR
VIN
rDS
VOUT
RESR

LOAD CL,OUT
OUT
IN DS LOAD CL,OUT
(Z || Z )
v
PSR(s) (s)
v r (Z || Z )
= =
+
VIN
rDS
Z
LOAD
Z
CL,OUT
VOUT
VIN
+
BGR
VREF
R1
R2 CL
IL
VOUT
rDS
EA
Cgg
gmp
rEA
gmEA
ESR
( )
LOAD ESR 1 2 L
L
1
Z R || R R ||R
sC
 
= + +
 
 
LOAD DS
CL,OUT
Z || r
Z
T(s)
=
ω [rad/s]
PSR:
V
OUT
/V
IN
[dB]
P
ω
VIN
rDS
VOUT
RCL,OUT
DC
DC
1
PSR
T
=
O X
UGF
ω
1
PSR
T(s)

VIN
rDSZ
CL,OUT
VOUT
VIN
rDS
VOUT
(R
1
+R
2
)||R
L
X
CL
ω
VIN
rDS
VOUT
(R
1
+R
2
)||R
L
CL
ESR
ω
O
VIN
rDS
VOUT
CL
RESR
VIN
rDS
VOUT
RESR

LOAD CL,OUT
OUT
IN DS LOAD CL,OUT
(Z || Z )
v
PSR(s) (s)
v r (Z || Z )
= =
+
VIN
rDS
Z
LOAD
Z
CL,OUT
VOUT
VIN
+
BGR
VREF
R1
R2 CL
IL
VOUT
rDS
EA
Cgg
gmp
rEA
gmEA
ESR
( )
LOAD ESR 1 2 L
L
1
Z R || R R ||R
sC
 
= + +
 
 
LOAD DS
CL,OUT
Z || r
Z
T(s)
=
ω [rad/s]
PSR:
V
OUT
/V
IN
[dB]
P
ω
DC
DC
1
PSR
T
=
O X
UGF
ω
1
PSR
T(s)

X
CL
ω ESR
ω
O
◼ If ωCL (by CL) = dominant-pole
(ωP = 2nd pole) ➔ More desirable ☺

Ripple Delivery via gmP: Ripple Feedforward (1/2)
 Kim & Kim, VLSI’19 & TPEL’20
VIN
+
BGR
VREF
R1
R2 COUT
VOUT
rDS
R
ESR
EA
ΔVRipple
RL
ωP1
AEA
gmP
Main
PSR
PSR
(V
OUT
/V
IN
)
[dB]
ω
0 dB
ωP1
ωBW
Lower is Better
Main PSR
w/o Ripple
Feedforward
ΔVRipple
+ X
Main PSR
w/ Ripple
Feedforward
Δvgs,P 0
𝑷𝑺𝑹𝑳𝒐𝒘 =
𝟏
𝑨𝑬𝑨 ∙
𝑹𝟐
𝑹𝟏 + 𝑹𝟐
𝟏
𝑻𝑳𝒐𝒐𝒑,𝑫𝑪
𝑷𝑺𝑹𝑯𝒊𝒈𝒉 = 𝒈𝒎𝑷 𝒓𝑫𝑺||𝑹𝑳
𝑹𝑳
𝒓𝑫𝑺 + 𝑹𝑳
❶
❷
❶ ❷
TLoop

☺

Ripple Delivery via gmP: Ripple Feedforward (2/2)
VBP
CS
RS
Cgg
MP
M8
M7
M6
VBI
Power
PMOS
VIN
Low-Z by
feedback
VRipple
FF-path2
(+)
VOUT Cgg
MP
M7
M6
VBI
Power
PMOS
VIN
M8
VRipple
Δvgs,M8
0 X
VOUT
 Proposed ripple-feedforward buffer
◼ VRipple is absorbed into low-Z via CS
 Conventional buffer
◼ No feedforward by Δvgs,M8 ≈ 0

Ripple Delivery via VREF: Recursive LDO (1/3)
Total PSR of LDO ≈ Worst(Main-PSR, BGR-PSR) Total PSR of LDO ≈ Main-PSR
VIN
BGR LDO
VIN
VOUT
LDO
VOUT
Conventional Architecture BGR-recursion
BGR BGR LDO
Out
Clean
Power
Recursion
BGR LDO
Out
Noisy Ref
Power w/ ripple
VREF
VREF
VIN
VREF
VOUT
VREF
Clean Ref
PSR
[dB]
ω
0 dB
ωP1
ωBW
Lower is Better
Main PSR
Total PSR
PSR
[dB]
ω
0 dB
ωP1
ωBW
Lower is Better
Main PSR
Total PSR

☺

 Design Consideration (1) in recursive LDO: stability
◼ TLoop(s) = main LDO regulation loop, TPFB(s) = BGR-recursive loop
◼ For stability, TPFB(s) < TLoop(s)
VIN
+
BGR R1
R2
VOUT
AEA gmP
Neg. TLoop(s)
VREF
CREF
Pos. TPFB(s)
CF
RP
I
PTAT
rds
Q1
C
p,BGR
VDD,BGR
VIN
+
BGR R1
R2
VOUT
AEA gmP
Neg. TLoop(s)
VREF
CREF
Pos. TPFB(s)
CF
RP
I
PTAT
rds
Q1
C
p,BGR
VDD,BGR
( ) ( )
,
,
, , ,
||
+
+
=
+ +  
+ + +
 
p BGR ds
P e Q
BGR
ds P e Q p BGR REF ds P e Q
sC r
R r
PSR
r R r s C C r R r
1
1 1
1
1
( )
( )
||
+
=
+ +
F
F
R sC R
β s
R R sC R R
2 1
1 2 1 2
1
1
( )
( ) ( ) ( ) ( )
( )
 
 + = −
 
 
1 BGR
tot Loop PFB Loop
PSR s
T s T s T s T s
β s

 Design Consideration (2) in recursive LDO: startup & deadlock
◼ As a result of VOUT fault, the recursive LDO may fall in a deadlock
◼ When fault is detected, the recursive-loop is unlocked & temporarily VIN-supplied
VIN
BGR LDO
VIN
VOUT
LDO
VOUT
VDD,BGR VIN
BGR-cascaded
EN=1
?
BGR-Replica
ON (VRP)
BGR-Output
Soft ON (VREF)
Yes
<
VRP = 0.8V VREF = 0→1.2V
CMP
VDD,BGR VOUT(LDO)
BGR-recursion
EN=0
?
No
Yes
No
Yes
Ref
Ref
BGR
VOUT
=0 ? Yes
No
Anti
dead
lock
CMP
= 0

Contents
 Conclusion

Triode LDO vs. Saturation (CS) LDO
VIN RL
RIN
+
VOUT
+
EA
VREF
RF1
RF2
CL VIN RL
+
VOUT
+
EA
VREF
RF1
RF2
CL
Variable CS
 Triode LDO  Saturation LDO
◼ Pass element works in triode region
◼ Small VDO (high η) ☺
◼ Low regulation due to low loop-gain
(T) 
◼ Bad PSR due to small RDS 
◼ Normally not preferred
◼ Pass element works in saturation region
◼ High VDO (lower η) 
◼ Good regulation performance due to
high loop-gain (T) ☺
◼ Good PSR owing to large RDS ☺
◼ Adopted in most LDOs
+ –
1% of VOUT
+ –
10% of VOUT

Low PSR of Triode LDO
-
+
VREF,P
Buffer
Av
MP
CL
IL
Av
RL
RO
T
RPASS
VDO
RPASS -
+
vIN (From SCC)
vOUT
VOUT
Condition: RPASS >> RL
RO = RPASS / T
T = AV x gm,P x RPASS
RPASS
Small
Dropout
RO + RPASS
RO
Low
PSR
= T
1
=
(15V)
(0.2V)
VH,M
VBOOST
(15.2V)
EROC
VOUT
=
+
VDO
inimized
(16V)
 Extremely excellent efficiency ☺: VDO = 0.2V [≈ 1.3% of VOUT (15V)]
 Low PSR due to small RPASS (= RDS of MP) 
◼ MP (power PMOS) working in triode region has a lower RDS

IL (load)
= IV
CL
VH,M
VDO
VOUT
VBOOST
-
+
(15.2V)
(0.2V)
(15V)
EROC
VOUT
=
+
VDO
Minimized
(16V)
-
+
VREF,P
Buffer
Av
VH,A
MV
IV
(+15V)
Aux.
Boost
Efficiency
Low
VOUT
VOUT VDO
+ + VBAT
Voltage Regulation (TV) Large Dropout
(VDO + VBAT)
x
Large Pass Current (IV)
=
High Power Loss
VBAT
-
+
(4V)
(19.2V)
VBAT
-
+
Voltage-Current-Hybrid (VIH) LDO (1/6)
◼ VIN (VH,A = 4V + VOUT) is boosted by charge-pump to ensure a sufficient VDO
◼ Significant power loss  (= large VDO x pass current IV)
 Ko & Kim, ISSCC’21 & JSSC’23

Current Mirroring
IL
= IC + IV
IC
CL
VH,M
Minimized
Dropout
β
VOUT
MC
-
+
VDO
-
+
VREF,P
Buffer
Av
VH,A
MV
IV
Voltage Regulation (TV)
Aux.
Boost
Efficiency
High
VOUT VDO
+
VOUT
(+15V)
Large Dropout
(VDO + VBAT)
x
Small Pass Current (IV)
=
Low Power Loss
Small Dropout (VDO)
x
Large Pass Current (IC)
=
Low Power Loss
VBAT
-
+
◼ Proposed VIH LDO: power current (IC) = β·
IV via power (triode) PMOS ☺
◼ TV-loop regulates the voltage VOUT, while handling smaller IV (≈ ILoad/β)

Current Regulation (TC)
ro,C
1/β
Rds,C
MC
(Main Pass TR.)
CL
VG
VH,M
IL
IC
VOUT
-
+
VREF,P
Buffer
Av
VH,A
MV
Aux.
Boost
(+15V)
IV
Rds,V
Current Loop (TC)
TC = 1/β x gm,C x ro,C
RPASS-Boosting
RPASS =
(1 + TC) x Rds,C
Av
-gm,C
RL
Rds,V
vH,M
ro,C
vOUT
RPASS
TC
1/β
+
-
vG
Rds,C
Small Sign Analysis
VBAT
-
+
◼ PMOS’s RDS is small because of working in triode region, BUT
◼ RPASS is highly boosted by current-loop gain (TC): RDS → (1+ TC)RDS

ro,C
1/β
Rds,C
MC
(Main Pass TR.)
CL
VH,M
VG
IL
VOUT
-
+
VREF,P
Buffer
Av
VH,A
MV
Aux.
Boost
(+15V)
Voltage Loop (TV)
TV = AV x gm,V x RL
Gm-Boosting
RO =
RL / (1 + β x TV)
Av
-gm,C
RL
Rds,V
vH,M
ro,C
RO
TV
TTOTAL vOUT
1/β
+
-
vG
Rds,C
Small Sign Analysis
VBAT
-
+
is
β x is
vH,M
gm-boosting
β x gm,V
IV
Rds,V
◼ RO is further reduced owing to GM-boosting effect (β): TV → β·
TV

Current Regulation (TC)
ro,C
1/β
Rds,C
MC
(Main Pass TR.)
CL
VH,M
VG
IL
VOUT
-
+
VREF,P
Buffer
Av
VH,A
MV
Rds,V
Aux.
Boost
(+15V)
Voltage Loop (TV)
TV = AV x gm,V x RL
Current Loop (TC)
TC = 1/β x gm,C x ro,C
Gm-Boosting RPASS-Boosting
PSR
High
RO =
RL / (1 + β x TV)
RPASS =
(1 + TC) x Rds,C
RO + RPASS
RO
Av
-gm,C
RL
Rds,V
vH,M
ro,C
RO
TV
TTOTAL vOUT
RPASS
TC
1/β
+
-
vG
Rds,C
Small Sign Analysis
VBAT
-
+
is
β x is
vH,M
gm-boosting
β x gm,V
◼ Small RO (by TV-loop) & Boosted RPASS (by TC-loop) ➔ high PSR even low VDO ☺

ro,C
1/β
Rds,C
MC
(Main Pass TR.)
CL
VH,M
VG
IL
VOUT -
+
VDO
-
+
VREF,P
Buffer
Av
VH,A
MV
Rds,V
Aux.
Boost
(+15V)
Load-Current-Reused (LCR)
Voltage Regulation
-
+
VBAT
VBAT
-
+
> VBAT
IBIAS
Load-Current-Reused (LCR)
Voltage Regulation
Lower Noise
@ Given Power & Size
Load-Current
Reused IBIAS
Low-Noise
5V CMOS
Using VH,A-VOUT
Supply Rail
◼ Bias current (IBIAS) consumed in TV-loop is re-used as a part of ILoad
◼ Thus, high bias current (IBIAS) can contribute on low noise of VOUT ☺

Implementation of VIH LDO
Mn2 :Mn3 MV :MVS
2:1 Mp3 :Mp4 :Mp5 10 :1:1
Mn5 :Mn6 1:10 Mn5 :Mn7 1:5 Mn9 :Mn8 :MGD
IV :IGD (=N:1)
30 :1
1:1:1
30 :1
MC :MCS
Mn5 :Mn6
300:1
IC :IGU 6000 :1
1:1
IC :In6 600:1 IC :IL,SEN 1200 :1
-
+
A2
x1
Buffer
-
+
AV MV
VH,A
VBAT
VREF
VOUT
MC-gate drive IC-sensing stage Low-voltage domain current-mirroring stage IV-sensing stage Balancing load Output
Voltage regulation stage
MVS
MC
MCS
IBV
IBB
MGU
MGD
MBAL
RBAL
CL
RZ
IL
CC1
CC2
Mp1
Mn1
Mp2
Mn2 Mn3
Mn4 Mn5
Mn6 Mn7
Mn8 Mn9
Mp3
Mp4 Mp5
Mp6 Mp7
IV
IC
IGU
IGD
In6 IL,SEN
IBAL
VM
VG
ICS IVS
5V CMOS
40V
LDMOS
IC :IGU = 6000 :1 (Nxβ:1)
IV :IGD = 30:1 (N:1)
LDO input (VIN = 15.2V)
VIN + VBAT (= 4V)
(= 15V)
β (current gain) = 200 A/A

Frequency & Stability of VIH LDO
Av
CL
RZ
ro,C
CC1
RL
iV
iC = β(s)iV
TV
TC
ro,ea
Cbuf
x1 vOUT
vG
Notation Pole/Zero Frequency [rad/s]
ωp1,V Pole 1/(RL·CL)
ωBW,C Pole gm,C/(N·β·CC1)
ωp2,V Pole 1/(ro,ea·Cbuf)
ωz,V Zero 1/(RZ·CL)
β·ωBW,C Zero gm,C/(N·CC1)
TTotal(s)
rad/s
TV(s)
ω
z,V
Heavy IL
Light IL
TC(s)
dB
β
ω
BW,C
rad/s
Pole-Zero Location
ω
p1,V
ω
BW,C
ω
p2,V
IL
( ) ( ) ( )
( ) ( )
( )( )( )
Total V
z,V BW,C
V m,V L
p1,V BW,C p2,V
T s β s T s
s ω s β ω
β A g R
s ω s ω s ω
= + 
 
 
 
+ + 
 
    
+ + +
1
1 1
1 1 1
( )
( )
( )
C
C
V C BW,C
T s
i
β s β β
i T s s ω
= =   
+ +
1
1 1
◼ Overall TTotal(s) has 3 poles and 2 zeros
◼ VIH LDO can cover a wide load range

Effects of VIH LDO
VM,N (100 mV/div)
VOUT,N (50 mV/div)
VOUT,P (50 mV/div)
VM,P (100 mV/div)
10μs
160 mV
160 mV
◼ VIH LDO effectively rejects
the switching ripple
100 1k 100k 1M
Frequency [Hz]
Noise
[V/sqrt(Hz)]
1.E-8
1.E-7
1.E-6
1.E-5
1.E-4
1.E-3
1.E-2
10k
VM,P
VOUT,P
IL = 20 mA
IL = 1 mA
fSW @ IL = 20 mA
fSW @ IL = 1 mA
PSR = -75 dB
@ 30 kHz
◼ -75dB PSR @ 30kHz & 28.7μVRMS noise
End-to-End
Efficiency
[%]
Output Power [mW]
Peak Efficiency
90.5%
95
90
85
80
75
70
600
400
200
VBAT = 4V
(w/o post-regulator)
VBAT = 4 V
VBAT = 3.5 V
VBAT = 4.5 V
◼ Efficiency loss is only 1.3%

Summary of VIH (triode) LDO
IBIAS
IV
x1/β
MC
(Main Pass TR.)
CL
VM
VG
-
+
VDO
-
+
Av
VH,A
MV
VBAT
-
+
-
+
VBAT
IL
IC
VREF
(15V)
ro,C
VOUT
IGU
IGD
Aux.
CP
VBAT
 Dedicated separate two loops
◼ TV (voltage) regulates VOUT by handling low IV
◼ TC (current) supplies IC (= β·
IV) via ultra-low VDO
 High PSR even at ultra-low VDO
◼ RPASS is boosted: RDS → (1+ TC)RDS
◼ Gm-boosting (β) effect further reduces RO
 Fabricated results
◼ Power efficiency = 98.7%
◼ PSR = -75dB @ 30kHz
◼ VOUT noise = 28.7μVRMS integrated in 0.1 – 500kHz
0.34mm2 in 0.18-μm BCD
VIN = 15.2V, VOUT = 15V

Contents
 Conclusion

Conclusion
 LDO performs DC-DC step-down conversion via a resistive power transfer media
◼ Error amplifier compares VOUT with VREF and controls the gate volt. of pass transistor
◼ Features: no ripple (clean VOUT), high PSR, small footprint (no bulky L), low efficiency
 Transient response of LDO is determined by loop bandwidth and slew-rate
◼ Dynamic range of load current that LDO can accommodate affects the loop stability
◼ Good FoM in LDO = bandwidth & slew rate vs. IQ consumption
 Supply-ripple (∆VIN) may leak to VOUT via three paths: 1) rDS, 2) gmP, 3) VREF
◼ Wide loop-BW helps to suppress ∆VIN that is transferred through rDS
◼ Ripple-feedforward to gate can restrain ∆VGS of power PMOS, improving PSR
◼ Recursive (self-biased) LDO design is introduced to be free from PSR of VREF
 Ultra-low-dropout (triode) LDO resolves a major drawback of low efficiency
◼ Voltage-current-hybrid (VIH) design is a good option for both high eff. & high PSR

Thank you!
Hyun-Sik Kim (KAIST) 91 of 94
2023 최신 집적회로설계 워크샵: LDO Regulators

References (1/2)
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version in IEEE JSSC, May 2023, pp. 1400-1413.
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References (2/2)
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 V. Gupta et al., "Analysis and design of monolithic, high PSR, linear regulators for SoC applications", IEEE Int.
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