Lear design club_presentation_collaboration-verification
- 1. Reuse and Collaboration Opportunities in AMS Design and Verification 9/30/2006 1
- 2. Overview Mixed-signal simulators for architectural design improve collaboration, reuse, and the verification schedule Standards or models can improve verification and validation collaboration and reuse 9/30/2006 2
- 3. Who Legerity is and What We Do Carrier Telephony • High voltage mixed-signal telephone drivers for central offices, local neighborhood boxes, and analog PBXs Consumer Telephony • Voice-enabled cable modems, voice- enabled DSL modems, analog terminal adapters • Phone ready PCs • Voice over wireless LAN 9/30/2006 3
- 4. Modeling and Design Tool Incompatability SYSTEM ARCHITECTURE Matlab/Simulink Software Mechanical SDK VHDL-AMS, FEA C Digital Logic Simulator Analog Spice P hysics R TL A nalog VERIFICATION Imagine verification is a fan... 9/30/2006 4
- 5. Incompatible Models Delay Verification SYSTEM SYSTEM ARCHITECTURE ARCHITECTURE MICRO MICRO ARCHITECTURE ARCHITECTURE MODELING MODELING VERIFICATION VERIFICATION 9/30/2006 5
- 6. Analog-Mixed-Signal Simulators Provide Solution SYSTEM ARCHITECTURE Analog/Mixed-signal Software Mechanical SystemC VHDL-AMS Digital Analog Logic Simulator Spice VERIFICATION 9/30/2006 6
- 7. Common Tools Move Verification Forward SYSTEM SYSTEM ARCHITECTURE ARCHITECTURE MICRO MICRO ARCHITECTURE ARCHITECTURE MODELING MODELING VERIFICATION VERIFICATION 9/30/2006 7
- 8. Very Little Test Case Sharing – As Expensive As Design SYSTEM ARCHITECTURE SYSTEM TEST CASES Software Mechanical DESIGN TEST CASES Digital Analog VERIFICATION TEST CASES VERIFICATION RANDOM TESTCASE GEN HARDWARE VALIDATION VALIDATION TEST CASES PRODUCT TEST PRODUCTION TEST CASES 9/30/2006 8
- 9. Virtual Lab Or Standard Devices/Languages May Provide Solution SD 1 2 3 4 5 6 7 8 9 10 11 12 SD P R O L IA N T 8000 ESC SD DLT Hardware vendors provide simulation models of their devices Define a standard set of devices and behavior A standard mixed-signal verification assertion language can be defined Bonus: Common environment allows common GUI between laboratory and simulation (e.g. LabView) Question: Do similar issues arise in signal processing and mechanical designs? 9/30/2006 9
- 10. Summary Problems • Collaboration between architecture and implementation • Delayed verification • Little test case, test bench, or RTG infrastructure reuse Solutions • Common design and modeling simulation tools • Virtual lab or language standards 9/30/2006 10