Lect2 up370 (100329)

Lecture 370 – Testing of ADCs and Moderate Speed Nyquist ADCs (3/29/10) Page 370-1
LECTURE 370 – TESTING OF ADCS AND MODERATE SPEED
NYQUIST ADCS
LECTURE ORGANIZATION
Outline
• Introduction
• Testing of ADCs
• Serial ADCs
• Successive approximation ADCs
• Single-bit/stage pipeline ADCs
• Iterative ADCs
• Self calibration techniques
• Summary
CMOS Analog Circuit Design, 2nd Edition Reference
Pages 665-681
CMOS Analog Circuit Design © P.E. Allen - 2010
TESTING OF ADCs
Input-Output Test for an ADC
Test Setup:
N-bit
ADC
under
test
DAC with
more resolution
than ADC
(N+2 bits)
Digital
Word
Output
(N bits)
Qn =
Vin-Vin'
Fig.10.5-17
Vin'
Vin Σ -
+
The ideal value of Qn should be within ±0.5LSB
Can measure:
• Offset error = constant shift above or below the 0 LSB line
• Gain error = contant increase or decrease of the sawtooth plot as Vin is increased
• INL and DNL (see following page)

Illustration of the Input-Output Test for a 4-Bit ADC
2.0 LSB
1.5 LSB
1.0 LSB
0.5 LSB
0.0 LSB
-0.5 LSB
-1.0 LSB
-1.5 LSB
-2.0 LSB
0
16
1
16
2
16
3
16
4
16
5
16
6
16
+2LSB
DNL
7
16
8
16
9
16
10
16
-2LSB
DNL
-2LSB
INL
11
16
12
16
+2LSB
INL
13
16
14
16
15
16
16
16
Quantization Noise (LSBs)
Analog Input Normalized to VREF
Fig.10.5-18
Measurement of Nonlinearity Using a Pure Sinusoid
This test applies a pure sinusoid to the input of the ADC. Any nonlinearity will
appear as harmonics of the sinusoid. Nonlinear errors will occur when the dynamic range
(DR) is less than 6N dB where N = number of bits.
t
VREF
N-bit
ADC
under
test
Vin
Harmonic
free
sinusoid
1000 0
1000
1
1001
1
Clock
|Vout(jω)|
DR
fsig
t
Distortion
or
Spectrum
Analyzer
Noise floor
due to non-linearities
ω
Spectral
Output
1111
1
Fig. 10.5-19A
Vout(DAC)
VREF
N-bit
DAC
with N+2
bits
resolution
Vout(DAC)
fsig
Vin
Comments:
• Input sinusoid must have less distortion that the required dynamic range
• DAC must have more accuracy than the ADC

FFT Test for an ADC
Test setup:
Analog-
Digital
Converter
Fast RAM
Buffer
FFT
Post-processor
Pure
Sinusoidal
Input, fin
Clock
fc
Frequency
Spectrum
Fig.10.5-19B
Comments:
• Stores the digital output codes of the ADC in a RAM buffer
• After the measurement, a postprocessor uses the FFT to analyze the quantization noise
and distortion components
• Need to use a window to eliminate measurement errors (Raised Cosine or 4-term
Blackmann-Harris are often used)
• Requires a spectrally pure sinusoid
Histogram Test for an ADC
The number of occurences of each digital output code is plotted as a function of the digital
output code.
Illustration:
Number of
Occurances
Sinusoidal Input
Triangular Input
0 Code
Comments:
• Emphasizes
the time spent
at a given level and can show DNL and missing codes
• DNL
DNL(i) =
0 Mid
Scale
Widthofthebinasafractionoffullscale
Ratioofthebinwidthtotheidealbinwidth -1 =
Full
Scale
Output
Fig.10.5-20
H(i)/Nt
P(i) -1
where
H(i) = number of counts in the ith bin
Nt = total number of samples
P(i) = ratio of the bin width to the ideal bin width
• INL is found from the cumulative bin widths

Comparison of the Tests for Analog-Digital Converters
Other Tests
• Sinewave curve fitting (good for ENOB)
• Beat frequency test (good for a qualitative measure of dynamic performance)
Comparison
Test
Error

Histogram
or
Code Test
FFT Test
Sinewave
Curve
Fit Test
Beat
Frequency
Test
DNL Yes (spikes) Yes (Elevated
noise floor)
Yes Yes
Missing Codes Yes (Bin counts with
zero counts)
Yes (Elevated
noise floor)
Yes Yes
INL Yes (Triangle input gives
INL directly)
Yes (Harmonics in
the baseband)
Yes Yes
Aperature
Uncertainty
No Yes (Elevated
noise floor)
Yes No
Noise No Yes (Elevated
noise floor)
Yes No
Bandwidth
Errors
No No No Yes (Measures
analog bandwidth)
Gain Errors Yes (Peaks in
distribution)
No No No
Offset Errors Yes (Offset of
distribution average)
No No No
Bibliography on ADC Testing
1.) D. H. Sheingold, Analog-Digital Conversion Handbook, Analog Devices, Inc.,
Norwood, MA 02062, 1972.
2.) S.A. Tretter, Introduction to Discrete-Time Signal Processing, John Wiley Sons
New York, 1976.
3.) J. Doernberg, H.S. Lee, and D.A. Hodges, “Full-Speed Testing of A/D Converters,”
IEEE J. of Solid-State Circuits, Vol. SC-19, No. 6, December 1984, pp. 820-827.
4.) “Dynamic performance testing of A to D converters,” Hewlett Packard Product Note
5180A-2.

INTRODUCTION TO MODERATE SPEED ADCS
Moderate Speed ADC Topics
• Serial ADCs - require 2NT for conversion where T = period of the clock
Types:
- Single-slope
- Dual-slope
• Successive approximation ADCs – require NT for conversion where T = the clock
period
• 1-bit per stage, pipeline ADCs – require T for conversion after a delay of NT
• Iterative ADCs – require NT for conversion
• Self-calibration techniques
SERIAL ANALOG-DIGITAL CONVERTERS
Single-Slope ADC
Block diagram:
vT
vin*
Ramp
Generator vT
vin*
+-
0 t
0
nT
VREF
Reset
Interval
Counter
t
t
Clock
f =1/T
T
Output
Counter
nT
nT
Output
Fig.10.6-1
n ≤ N
Attributes:
• Simplicity of operation
• Subject to error in the ramp generator
• Long conversion time 2NT

Dual-Slope ADC
Block diagram: Waveforms:
Positive
Integrator
1
2
Digital
Control
+-
Carry
Output Binary
Counter
vin*
-VREF
vint
Vth
Output
Fig.10.6-2
vin
VREF+Vth
Vth
0
0
t1 = NREFT
vin'''
vin''
vin'
vin''' vin'' vin'.
Reset t0(start)
NREFT
t2' t2''
t2'''
t2= NoutT
Fig.10.6-3
Operation:
1.) Initially vint = 0 and vin is sampled and held (vIN* 0).
2.) Reset the positive integrator by integrating a positive voltage until vint (0) = Vth.
3.) Integrate vin* for NREF clock cycles to get,
NREFT
vint(t1) = K
0
vin*dt

+ vint(0) = KNREFTvin* + Vth
4.) After NREF counts, the carry output of the counter closes switch 2 and-VREF is
applied to the positive integrator. The output of the integrator at t = t1+t2 is,
vint(t1+t2) = vint(t1)+K
NoutT
t1
(VREF)dt

t
=Vth KNREFTvin*+Vth -KNoutTVREF = Vth
5.) Solving for Nout gives, Nout = NREF (vin*/VREF)
Comments: Conversion time 2(2N)T and the operation is independent of Vth and K.
SUCCESSIVE APPROXIMATION ANALOG-DIGITAL CONVERTERS
Introduction
Successive Approximation Algorithm:
1.) Start with the MSB bit and work toward the LSB bit.
2.) Guess the MSB bit as 1.
3.) Apply the digital word 10000.... to a DAC.
4.) Compare the DAC output with the sampled analog input voltage.
5.) If the DAC output is greater, keep the guess of 1. If the DAC output is less, change
the guess to 0.
6.) Repeat for the next MSB.
vguess
VREF
0.75VREF
0.50VREF
0.25VREF
0
0 1 2 3 4 5 6 tT
Fig.10.7-2

Block Diagram of a Successive Approximation ADC†
Output
Register
Vin* +-
Comparator
Digital-Analog
Converter
Conditional
Shift
Register Clock
Output
VREF
Gates Fig.10.7-1
† R. Hnatek, A User's Handbook of D/A and A/D Converters, John Wiley and Sons, Inc., New York, NY, 1976.
5-Bit Successive Approximation ADC
LSB
Analog
Switch
5
0 1
FF5
R RD S
G5
5-bit Digital-Analog Converter
Analog
Switch
4
0 1
FF4
R RD S
G4
VREF
LSB
Analog
Switch
3
0 1
FF3
R RD S
G3
Analog
Switch
2
MSB
0 1
FF2
R RD S
G2
vIA vOA
Comp-arator
MSB
Analog
Switch
1
0 1
FF1
R RD S
G1
1 1 1
SR1 SR2 SR3 SR4
Shift Register
1
SR5
1
Analog
In
-1
Gate
Delay
+ -
Delay
Clock pulses
Start pulse
The delay allows for the circuit transients to
settle before the comparator output is sampled. Fig.10.7-3

m-Bit Voltage-Scaling, k-Bit Charge-Scaling Successive Approximation ADC
Operation:
1.) With the two SF
switches closed, all
capacitors are paralleled
and connected to Vin*
which autozeros the
comparator offset
voltage.
2.) With all capacitors
still in parallel, a suc-cessive
approximation
Ck =
2k-1C
Ck-1=
2k-2C
Sk-1,A
Bus A
SB
Sk,A
Sk,B
SF
Sk-1,B
Bus B
C2=
2C
C1=
C
C
m-MSB bits
m-bit, MSB voltage
scaling subDAC
m-to-2m Decoder A
R1 R2 R3 R2m-2 R2m-1 R2m
m-to-2m Decoder B
Vin*
S2A
S2B
S1A
S1B
VREF
m-MSB bits
k-bit, LSB charge
scaling subDAC
SF
m-MSB bits
Capacitor Switches Clock
Successive approximation
register switch control logic
search is performed to
find the resistor segment
in which the analog
signal lies.
3.) Finally, a successive
approximation search is performed on charge scaling subDAC to establish the analog
output voltage.
+-
(m+k) bit output of ADC Start
Fig.10.7-4
Voltage-Scaling, Charge-Scaling Successive Approximation ADC - Continued
Autozero Step
Removes the influence of the offset voltage of the
comparator.
The voltage across the capacitor is given as,
vC = Vin* - VOS
Successive Approximation Search on the Resistor String
The voltage at the comparator input is
vcomp = VRi - Vin*
If vcomp 0, then VRi Vin*, if vcomp 0, then VRi Vin*
Successive Approximation Search on the Capacitor SubDAC
The input to the comparator is written as,
vcomp = (VRi+1 - V*
in)
Ceq
2kC + (VRi - V*
in)
2kC-Ceq
2kC
However, VRi+1 = VRi + 2-mVREF
Combining gives,
vcomp = (VRi + 2-mVREF -V *
IN)
Ceq
2kC + (VRi-V *
IN)
2kC-Ceq
2kC
= VRi - V * IN + 2-mVREF
Ceq
2kC
+ -
Vin*
vC
+ -
+
-
2kC
VOS
VOS
Fig.10.7-5
vcomp
2kC
Busses
A and B
V*in
+ -
VRi=V'REF -
+
Fig.10.
Fig.10.7-6
-
+
VRi+1
+ + -
2-mVREF
VRi=V'REF
vcomp
Ceq.
V*in
2kC - Ceq.
Bus
A
Bus
B
+ -
V*in
-

SINGLE-BIT/STAGE, PIPELINE ANALOG-DIGITAL CONVERTERS
Single-Bit/Stage Pipeline ADC Architecture
MSB LSB
+ -
Σ z-1 2
±1
Vin*
VREF
+ -
2 Vi-1
Σ
±1
z-1
+ -
2 Vi
Σ
±1
z-1
+ -
z-1
Implementation:
Operation:
• Each stage multiplies
its input by 2 and adds or
subtracts VREF depending
upon the sign of the input.
• i-th stage,
Vi = 2Vi-1 - biVREF
where bi is given as
bi =
+1ifVi-10
-1ifVi-10
i-th stage
Stage 1 Stage 2 Stage N
Fig.10.7-9
Vi/VREF
1.0
0
-1.0 -0.5 0 0.5 1.0
-1.0
bi+1
=+1
bi+1
=-1
bi = -1 bi = +1
Vi-1/VREF
[bi,bi+1] [0,0] [0,1] [1,0] [1,1] Fig.10.7-10
Example 370-1 - Illustration of the Operation of the Pipeline ADC
Assume that the sampled analog input to a 4-bit pipeline analog-digital converter is 2.00
V. If VREF is equal to 5 V, find the digital output word and the analog equivalent voltage.
Solution
Stage No. Input to the ith stage, Vi-1 Vi-1 0? Bit i
1 2V Yes 1
2 (2V·2) - 5 = -1V No 0
3 (-1V·2) + 5 = 3V Yes 1
4 (3V·2) - 5 = 1V Yes 1
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
REF
Stage Ouputs normalized to V
Stage 4
Stage 3
Stage 2
Stage 1
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1
*/V REF
V in
Illustration:
Vanalog = 5

12
14

18
+
1
16
+
= 5(0.4375) = 2.1875
where bi = +1 if the ith-bit is 1
and bi = -1 if the ith bit is 0

Achieving the High Speed Potential of the Pipeline ADC
If shift registers are used to store the output bits and align them in time, the pipeline ADC
can output a digital word at every clock cycle with a latency of NT.
Illustration:
MSB
SR
SR
SR
SR
+ -
Σ z-1 2
±1
Vin*
VREF
MSB-1
SR
SR
SR
+ -
2 Vi-1
Σ
±1
z-1
Digital Ouput Word
i-th Bit
SR
+ -
2 Vi
Σ
±1
z-1
LSB
+ -
i-th stage
Stage 1 Stage 2 Stage N
Fig.10.7-9B
z-1
Errors in the Pipeline ADC
Types of errors:
• Gain errors – x2 amplifier or summing junctions
• Offset errors – comparators or summing junctions
Illustration of errors:
-1
2ΔAi
060927-04
2ΔAi
Vo/VREF
Vi/VREF
1
1
0
0
-1
2VOSi
Vo/VREF
1Vi/VREF
1
-1
0
0
-1
2VOSi
System offset error, VOSi.
Vo/VREF
Vi/VREF 1
1
-1
0
0
-1
2VOCi
Comparator offset error, VOCi.
Gain error, Ai.
An error will occur if the output voltage of one stage exceeds ±VREF (saturates).

Digital Error Correction
In the previous slide, we noted that if the analog output to the next stage exceeds ±VREF
that an error occurs. This error can be detected by adding one more bit to the following
stage for the purposes of detecting the error.
Illustration (2nd bit not used for error correction):
Input
Range
for next
Stage
Input/output characteristics of a 1-bit stage Input/output characteristics of a 2-bit stage
Vin(i)
060930-01
Vout(i)
0 0 1 1
VREF
1
Vin(i)
VREF
-VREF
-VREF
Vout(i)
00 01 10 11
VREF
11
10
01
00
VREF
-VREF
-VREF
[00] [01] [10] [11]
0
[0000]
[0010]
[0001]
[0011]
[0100]
[0110]
[0101]
[0111]
[1000]
[1010]
[1001]
[1011]
[1100]
[1110]
[1101]
[1111]
Input
Range
for next
Stage
Digital Error Correction – Continued
If the gain of 4 amplifier is reduced back to 2, the input/output characteristics of the 2-bit
stage become:
Vin(i)
Input
Range
for next
Stage
060930-02
Vout(i)
00 01 10 11
VREF
11
10
01
VREF
-VREF
-VREF
[0001]
[0010]
[0101]
[0110]
[1001]
[1010]
[1101]
[1110]
00
The output bits can be used to determine the error. If these bits are 00, then 0.5LSB must
be added to get the correct digital output. If the bits are 11, then 0.5LSB must be
subtracted to get the correct digital output.

Modified Digital Error Correction (1.5 bits per stage)
In the previous slide, it was necessary sometimes to perform digital subtraction which is
not easy to implement. To avoid this problem, a 0.5LSB shift has been added to the
input/output characteristic resulting in the following.
Movement of all comparator thresholds
to the right by 0.5LSB.
Vout(i)
00 01 10 11
VREF
11
10
VREF
-VREF
-VREF
Vin(i)
Input
Range
for next
Stage
Vin(i)
Input
Range
for next
Stage
060930-03
Removal of the comparator at 0.75LSB.
Vout(i)
00 01 10
VREF
10
VREF
-VREF
4
-VREF
-VREF
[0000]
[0001]
[0101]
[0010]
[0100]
VREF
4
[1000]
[1001]
[1010]
01
00
01
00
[0110]
[0000]
[0001]
[0101]
[0100]
[1000]
[1001]
[1010]
[0010]
[0110]
[1100]
[1101]
To obtain code 11 out of the stage after correction, the correction logic must increment
the output of the stage.
To obtain code 00 from this stage after correction, the correction logic need do nothing.
Therefore, only two comparators are needed to produce outputs of (00, 01, 10) as shown
on the right-hand characteristic.
How Does the 1.5 Bit Stage Correct Offset Errors?
Consider a ±0.25VREF comparator offset shift in the input-output characteristics of the
1.5 bit stage.
Input
Range
for next
Stage
061001-01
0.5
Vin(i)
VREF
Vout(i)
Input
Range
for next
Stage
VREF
2
4
3
1
-0.5
-1
0 1 1
Comparator shift
from 0.25VREF
to 0VREF
2
4
1
4
1 4 3
4
- - - -
4
0
0.5
Vin(i)
VREF
Vout(i)
VREF
2
4
3
1
-0.5
-1
0 1 1
Comparator shift
from 0.25VREF
to 0.5VREF
2
4
1
4
1 4 3
4
- - - -
4
0
When the shift is to the left, the comparator will not be in error until the shift is greater
than 0.25 VREF. This is because the comparator thresholds were shifted to the right by
0.5 VREF.
When the shift is to the right, the input to the next stage will be greater than 0.50VREF.
This will cause the output code 10 which indicates that the digital word should be
incremented by 1 bit.
The range of correction ±VREF /2B+1 where B is the number of bits per stage.

Implementation of the 1.5 Bit Stage
1 if
VREF
4 +
vin ≥ C C
1 if
vin
VREF
4 −
061001-03
−
+
vin φ1
C
φ2
VREF φ1
C
φ2
4
φ1
−
+
vin φ1
C
φ2
VREF φ1
C
φ2
4
φ1
−
Sub-ADC
φ1
− φ2
+
φ1
φ1
φ2
φ1
VREF
VREF
Multiplying
Sub-DAC
vout
The multiplying Sub-DAC must implement the following equation:
Vout =

2·vin-VREF
2·vin
2·vin+VREF
if vinVREF/4
if -VREF/4vinVREF/4
if vin-VREF/4
Example 370-2 - Accuracy requirements for a 5-bit pipeline ADC
Show that if Vin = VREF, that the pipeline ADC will have an error in the 5th bit if the gain
of the first stage is 2-(1/8) =1.875 which corresponds to when an error will occur. Show
the influence of Vin on this result for Vin of 0.65VREF and 0.22VREF.
Solution
For Vin = VREF, we get the results shown below. The input to the fifth stage is 0V
which means that the bit is uncertain. If A1 was slightly less than 1.875, the fifth bit
would be 0 which is in error. This result assumes that all stages but the first are ideal.
i Vi(ideal) Bit i (ideal) Vi(A1=1.875) Bit i (A1=1.875)
1 1 1 1.000 1
2 1 1 0.875 1
3 1 1 0.750 1
4 1 1 0.500 1
5 1 1 0.000 ?
Now let us repeat the above results for Vin = 0.65VREF. The results are shown below.
1 +0.65 1 0.6500 1
2 +0.30 1 0.2188 1
3 -0.40 0 -0.5625 0
4 +0.20 1 -0.1250 0
5 -0.60 0 0.7500 1

Example 370-2 - Continued
Next, we repeat for the results for Vin = 0.22VREF. The results are shown below. We
see that no errors occur.
1 +0.22 1 0.2200 1
2 -0.56 0 -0.5875 0
3 -0.12 0 -0.1750 0
4 +0.76 1 0.6500 1
5 +0.52 1 0.3000 1
Note the influence of Vin in the fact that an error occurs for A1= 1.875 for Vin =
0.65VREF but not for Vin = 0.22VREF. Why? Note on the plot for the output of each
stage, that for Vin = 0.65VREF, the output of the fourth stage is close to 0V so any small
error will cause problems. However, for Vin = 0.22VREF, the output of the fourth stage is
at 0.65VREF which is further away from 0V and is less sensitive to errors.
The most robust values of Vin will be near -VREF , 0 and +VREF. or
when each stage output is furthest from the comparator threshold, 0V.
ITERATIVE ANALOG-DIGITAL CONVERTERS
Iterative (Cyclic) Algorithmic Analog-Digital Converter
The pipeline ADC can be reduced to a single stage that cycles the output back to the
input.
Implementation:
+
-
Voi
+1 +1
Σ
x2
Sample
and
Hold
+VREF
-VREF
+-
x2
Va
VREF
+1
Vb
Σ Sample
and
Hold
+1
S1
Vo
Vin*
Vo =1
-VREF
Vo =0
Iterative algorithm ADC Different version of iterative algorithm ADC implementation
Fig. 10.7-13
Operation:
1.) Sample the input by connecting switch S1 to Vin*.
2.) Multiply Vin* by 2.
3.) If Va VREF, set the corresponding bit = 1 and subtract VREF from Va.
If Va VREF, set the corresponding bit = 0 and add zero to Va.
4.) Repeat until all N bits have been converted.

Example 370-3 - Conversion Process of an Iterative, Algorithmic Analog-Digital
Converter
The iterative, algorithmic analog-digital converter is to be used to convert an analog
signal of 0.8VREF. The figure below shows the waveforms for Va and Vb during the
process. T is the time for one iteration cycle.
1.) The analog input of 0.8VREF givesVa = 1.6VREF and Vb = 0.6VREF and the MSB as 1.
2.) Vb is multiplied by two to give Va = 1.2VREF. The next bit is also 1 and Vb = 0.2VREF.
3.) The third iteration givesVa = 0.4VREF, making the next bit is 0 and Vb = 0.4VREF .
4.) The fourth iteration gives Va = 0.8VREF, giving Vb = 0.8VREF and the fourth bit as 0.
5.) The fifth iteration gives Va = 1.6VREF, Vb = 0.6VREF and the fifth bit as 1.
The digital word after the fifth iteration is 11001 and is equivalent to an analog voltage of
0.78125VREF.
Va/VREF

2.0
1.6
1.2
0.8
0.4
0.0
0 1 2 3 4 5
t/T
Vb/VREF
2.0
1.6

1.2

0.8
0.4

0.0
0 1 2 3 4 5
t/T
Fig. 10.7-14.
SELF-CALIBRATION TECHNIQUES
Self-Calibrating Analog-Digital Converters
Self-calibration architecture for a m-bit charge scaling, k-bit voltage scaling successive
approximation ADC
+ -
C1
VREF
m-bit subDAC
C2 C3 Cm-1
m control lines
Successive
Approximation
Cm
S1
m+2-bit
Calibration
k-bit
subDAC
k-bits
Cm
DAC
Control
Logic
To Successive
Approximation
Register
Register
Adder
Data Register
Comments:
Register
• Self-calibration can be
m+k-bits
accomplished during a
calibration cycle or at start-up
• In the above scheme, the LSB bits are not calibrated
• Calibration can extend the resolution to 2-4 bits more that without calibration
Vε1 Vε2
Data Output
Fig.10.7-15

Self-Calibrating Analog-Digital Converters - Continued
Self-calibration procedure starting with the MSB bit:
1.) Connect C1 to VREF and the
remaining capacitors (C2+C3+···+Cm
+Cm = C1 ) to ground and close SF.
2.) Next, connect C1 to ground and
C1 to VREF.
3.) The result will be Vx1 =

C1 -C1
C1+ C1
C1
VREF C1
C1
VREF
+ -
Connection of C1 to VREF. Connection of C1 to VREF.
VREF. If C1 = C1 , then Vx1 = 0.
C1
Vx1
+ -
Fig.10.7-16
VREF
4.) If Vx1 0, then the comparator output will be either high or low. Depending on the
comparator output, the calibration circuitry makes a correction through the calibration
DAC until the comparator output changes. At this point the MSB is calibrated and the
MSB correction voltage, V1 is stored.
5.) Proceed to the next MSB with C1 out of the array and repeat for C2 and C2 . Store
the correction voltage, V2, in the data register.
6.) Repeat for C3 with C1 and C2 out of the array. Continue until all of the capacitors of
the MSB DAC have been corrected.
Note: For normal operation, the circuit adds the correct combined correction voltage.
SUMMARY
• Tests for the ADC include:
- Input-output test
- Spectral test
- FFT test
- Histogram test
• Moderate Speed ADCs:
Type of ADC Advantage Disadvantage
Serial ADC High resolution Slow
Voltage-scaling, charge-scaling
successive approximation ADC
High resolution Requires
considerable digital
control circuitry
Successive approximation
using a serial DAC
Simple Slow
Pipeline ADC Fast after initial
latency of NT
Accuracy depends
on input
Iterative algorithmic ADC Simple Requires other
digital circuitry
• Successive approximation ADCs also can be calibrated extending their resolution 2-4
bits more than without calibration.

Lect2 up370 (100329)

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