Lect2 up380 (100329)
- 1. Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-1 LECTURE 380 – HIGH SPEED NYQUIST ADCS LECTURE ORGANIZATION Outline • Parallel/flash ADCs • Interpolating and averaging • Folding • High-speed, high-resolution ADCs • Time-interleaved ADCs CMOS Analog Circuit Design, 2nd Edition Reference Pages 682-697 CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-2 PARALLEL/FLASH ADCs Parallel/Flash ADC Architecture Analog Input VREF Voltage Scaling Network creating all possible discrete analog voltages 060928-01 vin(t) V1 V2 V3 V4 V2N-1 Sample and Hold Circuit vin*(t) 2N-1 Compar ators d1 d2 d3 d4 d2N-1 2N-1 to N Decoder b1 b2 b3 bN Phase 1 Phase 2 One Clock Period, T Digital Word Output • The notation, vin*(t), means the signal is sampled and held. • The sample and hold function can be incorporated into the comparators • The digital words designated as di form a thermometer code CMOS Analog Circuit Design © P.E. Allen - 2010
- 2. Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-3 A 3-bit, parallel ADC General Comments: • Fast, in the first phase of the clock the analog input is sampled and applied to the comparators. In the second phase, the digital encoding network determines the correct output digital word. • Number of comparators required is 2N-1 which can become large if N is large • The offset of the comparators must be less than ±VREF/2N+1 • Errors occur as “bubbles” in the thermometer code and can be corrected with additional circuitry • Typical sampling frequencies can be as high as 1000MHz for 6-bits in sub-micron CMOS technology. VREF Vin*=0.7VREF R 1 + - R 1 + - R 0 + - R 0 + - R 0 + - R 0 + - R 0 + - R 2N-1 to N encoder Output Digital Word 101 0.875VREF 0.750VREF 0.625VREF 0.500VREF 0.375VREF 0.250VREF 0.125VREF Fig.10.8-1 CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-4 Example 380-1 - Comparator Bandwidth Limitations on the Flash ADC The comparators of a 6-bit, flash ADC have a dominant pole at 104 radians/sec, a dc gain of 104 a slew rate of 10V/μs, and a binary output voltage of 1V and 0V. Assume that the conversion time is the time required for the comparator to go from its initial state to halfway to its final state. What is the maximum conversion rate of this ADC if VREF = 1V? Assume the resistor ladder is ideal. Solution: The output of the i-th comparator can be found by taking the inverse Laplace transform of, L -1 Ao Vout(s)=
- 4. (s/104)+1 ·
- 6. Vin*-VRi s vout(t) = Ao(1 - e-104t)(Vin* - VRi). The worst case occurs when Vin*-VRi = 0.5VLSB = VREF/27 = 1/128 0.5V = 104(1 - e-104T)(1/128) 64x10-4 = 1- e-104T or, e-104T = 1 - 64x10-4 = 0.9936 T = 10-4 ln(1.0064) = 0.6421μs Maximum conversion rate = 1 0.6421μs = 1.557x106 samples/second Checking the slew rate shows that it does not influence the maximum conversion rate. SR = 10V/μs V T = 10V/μs V = 10V/μs(0.6421μs) = 6.421V 1V CMOS Analog Circuit Design © P.E. Allen - 2010
- 7. Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-5 Signal Delay in High Speed Converters Assume that clocked comparators are used in a 500MHz sampling frequency ADC of 8-bits. If the input frequency is 250MHz with a peak-to-peak value of VREF, the clock accuracy must be t V Vp = VREF/2N+1 2f(0.5VREF) = 1 29··f 2.5ps Since electrical signals travel at approximately 50μm/ps for metal on an IC, each metal path from the clock to each comparator must be equal to within 125μm to avoid LSB errors due to clock skew. Therefore, must use careful layout to avoid ADC inaccuracies at high frequencies. An equal-delay clock distribution system for a 4-bit parallel ADC: Clock Generator 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Comparators Fig.10.8-2B CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-6 Other Errors of the Parallel ADC • Resistor string error - if current is drawn from the taps to the resistor string this will create a “bowing” effect on the voltage. This can be corrected by applying the correct voltage to various points of the resistor string. • Input common mode range of the comparators - the comparators at the top of the string must operate with the same performance as the comparators at the bottom of the string. • Kickback or flashback - influence of rapid transition changes occurring at the input of a comparator. Can be solved by using a preamplifier or buffer in front of the comparator. • Metastability - uncertainty of the comparator output causing the transition of the thermometer code to be undetermined. CMOS Analog Circuit Design © P.E. Allen - 2010
- 8. Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-7 INTERPOLATING AND AVERAGING Illustration of a 3-bit interpolating ADC using a factor of 4 interpolation VDD A2 + - VDD +- V2 Vth R 8 +- V2a R 7 +- V2b R 6 +- V2c R 5 V1 +- R 4 +- V1a R 3 +- V1b R 2 +- V1c R 1 VREF 8 to 3 encoder Vin R A1 + - R VREF 2 3-bit digital output Fig.10.8-3 Volts VDD Vth V2 V2a V2b V2c 1 2 3 4 5 6 7 8 VREF 0 0 V1c V1b V1a V1 0.5VREF Comparator Threshold Vin Comments: Fig.10.8-4 • Capacitive loading at the input is reduced from 8 comparators to two amplifiers. • The comparators no longer need a large ICMR • V1 and V2, are interpolated through the resistor string and applied to the comparators. • Because of the amplification of the input amplifiers and a single threshold, the comparators can be simple and are often replaced by a latch. • If the dots in Fig. 10.8-4 are not equally spaced, INL and DNL will result. CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-8 A 3-Bit Interpolating ADC with Equalized Comparator Delays One of the problems in voltage (passive) interpolation is that the delay from the amplifier output to each comparator can be different due to different source resistance. Solution: CMOS Analog Circuit Design © P.E. Allen - 2010
- 9. Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-9 Active Interpolation Example of a 3 level current interpolation: +2I2 4 I1 4 I2 I2 4 +3I2 4 2I2 4 3I2 4 I2 3I2 4 2I2 4 I2 4 x4 x1 x2 x3 x4 x3 x2 x1 060928-02 I1 I1 4 2I1 4 3I1 4 I1 3I1 4 3I1 4 + I2 4 2I1 4 I1 4 x4 x1 x2 x3 x4 x3 x2 x1 2I1 4 This type of interpolation works well with current processing, i.e., current comparators. CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-10 Interpolation using Amplifiers 060928-03 Interpolating Amplifiers + - + - + - + - + - + - Vin Preamplifiers + - + - Aj+1 + - + - VR,j+1 VR,j Aj Vy Vo2 Vo3 Vx Vo1 Vo3 = K(Vy – Vx) which is between Vy and Vx. CMOS Analog Circuit Design © P.E. Allen - 2010
- 10. Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-11 Averaging† In many cases, the comparators consist of a number of pre-amplifiers followed by a latch. Averaging is the result of interconnecting the outputs of each stage of amplifiers so that the errors in one amplifier chain are balanced out by adjacent amplifier chains. Result: The offsets are reduced allowing the transistors to be made smaller and therefore reducing the parasitics increasing the speed of the ADC. VDD Termination Resistors A11 A21 AN-2,1 AN-1,1 Termination Resistors VDD Termination Resistors A12 A22 AN-2,2 AN-1,2 Termination Resistors VDD Termination Resistors A13 A23 AN-2,3 AN-1,3 Termination Resistors 060928-04 † P.C.S. Scholtens and M. Vertregt, “A 6-b 1.6-Gsample/s Flash ADC in 0.18 μm CMOS Using Averaging Termination, IEEE J. of Solid-State Circuits, vol. 37, no. 12, Dec. 2002, pp. 1599-1609. CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-12 Analog Front End of an ADC using Averaging CMOS Analog Circuit Design © P.E. Allen - 2010
- 11. Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-13 FOLDING Folding Analog-Digital Converters Allows the number of comparators to be reduced below the value of 2N-1. Architecture for a folded ADC: Preprocessor Coarse Quantizer n1 bits Vin Logic Folding Preprocessor Fine Quantizer Encoding Digital Output n2 bits n1+n2 bits Fig.10.8-7 Operation: The input is split into two or more parallel paths. • First path uses a coarse quantizer to quantize the signal into 2n1 values • The second path maps all of the 2n1 subranges onto a single subrange and applies this analog signal to a fine quantizer of 2n2 subranges. Thus, the total number of comparators is 2n1-1 + 2n2-1 compared with 2n1+n2-1 for a parallel ADC. I.e., if n1 = 2 and n2 = 4, the folding ADC requires 3 + 15 = 18 compared with 63 comparators. CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-14 Example of a Folding Preprocessor Folding characteristic for n1 = 2 and n2 = 3. 8 32 VREF After Analog Preprocessing MSBs = 00 01 10 11 No Folding Folding 0 0 Analog Input VREF n1 = 2 n2 = 3 VREF 4 Fig.10.8-9 Problems: • The sharp discontinuities of the folder are difficult to implement at high speeds. • Fine quantizer must work at voltages ranging from 0 to VREF/4 (subranging). • The actual frequency of the folding signal is F times the input frequency where F is the number of folds CMOS Analog Circuit Design © P.E. Allen - 2010
- 12. Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-15 Modified Folding Preprocessors The discontinuity problem can be removed by the following folding preprocessors: Vin VREF Vin VREF 060928-04 Folder that removes discontinuity problem. Vout VREF 8 0 -VREF 8 0 Multiple folders shifted in voltage. Vout VREF 8 0 0 -VREF 8 In the second case, the reference voltage for all comparators is identical which removes any ICMR problems. CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-16 A 5-Bit Folding ADC Using 1-Bit Quantizers (Comparators) Block diagram: Coarse MSBs (n1=2) Folder 1 +- Folder 2 +- Folder 7 +- 2 bits Decoder Vin 3 bits LSBs Comparators 5-bit digital output Fig.10.8-11 Comments: • Number of comparators is 7 for the fine quantizer and 3 for the course quantizer • The zero crossings of the folders must be equally spaced to avoid linearity errors • The number of folders can be reduced and the comparators simplified by use of interpolation CMOS Analog Circuit Design © P.E. Allen - 2010
- 13. Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-17 Folding Circuits Implementation of a times 4 folder: Folding Outputs Vou - + RL RL I I I I V1 V2 V8 VDD I Vin +VREF V8 V7 V7 R R/4 R/4 R/4 R/4 R/4 R/4 R/4 R/4 Comments: R/4 V2 • Horizontal R/4 Vout R/4 shifting is R/4 V1 achieved by R/4 R/4 modifying the R/4 R/4 V1 V2 V3 V4 V5 V6 V7 topmost and bottom resistors of the resistor 060928-06 string • Folding and interpolation ADCs offer the most resolution at high speeds (8 bits at 500MHz) Vin +IRL 0 -IRL VREF V8 CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-18 Use of a S/H in Front of the Folding ADC Benefit of a S/H: • With no S/H, the folding circuit acts as an amplitude-dependent frequency multiplier. BW of ADC BW of Folding Circuit • With S/H, all inputs to the folding circuit arrive at the same time. - The folding circuit is no longer an amplitude-dependent frequency multiplier - BW of the ADC is now limited by the BW of the S/H circuit - Settling time of the folding and interpolating preprocessor is critical Single S/H versus Distributed S/H: • Single S/H requires high dynamic range for low THD • Dynamic range requirement for distributed S/H reduced by the number of S/H stages • If the coarse quantizer uses the same distributed S/H signals as the fine preprocessor, the coarse/fine synchronization is automatic • The clock skew between the distributed S/H stages must be small. The clock jitter will have a greater effect on the distributed S/H approach. CMOS Analog Circuit Design © P.E. Allen - 2010
- 14. Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-19 Error Sources and Limitations of a Basic Folding ADC Error Sources: • Offsets in reference voltages due to resistor mismatch • Preamp offset (reduced by large W/L for low VGS-VT, with common-centroid geometry) • vin feedthrough to reference ladder via Cgs of input pairs places a maximum value on ladder resistance which is dependent on the input frequency. • Folder current-source mismatches (gives signal-dependent error distortion) • Comparator kickback (driving nodes should be low impedance) • Comparator metastability condition (uncertainty of comparator output) • Misalignment between coarse and fine quantization outputs (large code errors possible) Sampling Speed Limitations: • Folding output settling time • Comparator settling time • Clock distribution and layout • Clock jitter Input Bandwidth Limitations: • Maximum folding signal frequency (F/2)·fin, unless a S/H is used • Distortion due to limited preamplifier linear range and frequency dependent delay • Distortion due to the limited linear range and frequency dependent delay of the folder • Parasitic capacitance of routing to comparators CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-20 HIGH-SPEED, HIGH-RESOLUTION ADCs Multiple-Bit, Pipeline Analog-Digital Converters A compromise between speed and resolution is to use a pipeline ADC with multiple bits/stage. i-th stage of a k-bit per stage pipeline ADC with residue amplification: Residue Av =2k i+1-th stage Vi+1 061002-02 VREF VREF k-bit ADC k-bit DAC k-bits Clock S/H Residue Σ Av =2k + - i-th stage Vi-1 Vi VREF VREF k-bit ADC k-bit DAC k-bits Clock S/H Σ + - Residue voltage = Vi-1 - bk-1 2k VREF b0 2 + bk-2 2k-1+ b1 22+···+ Potential specifications range from 100-300 Msps and 10 to 14 bits. CMOS Analog Circuit Design © P.E. Allen - 2010
- 15. Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-21 A 3-Stage, 3-Bit Per Stage Pipeline ADC Illustration of the operation: Stage 1 111 110 101 100 011 010 001 000 Stage 2 111 110 101 100 011 010 001 000 Stage 3 111 110 101 100 011 010 001 000 0 Time Clock 1 Clock 2 Clock 3 VREF VREF 2 Voltage Digital output = 011 111 001 MSB LSB Fig.10.8-14 Converted word is 011 111 001 Comments: • Only 21 comparators are required for this 9-bit ADC • Conversion occurs in three clock cycles • The residue amplifier will cause a bandwidth limitation, GB = 50MHz f-3dB = 50MHz 23 6MHz CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-22 Multiple-Bit, Pipeline Analog-Digital Converters - Subranging The amplification of Av = 2k for each stage places a bandwidth limitation on the converter. The subranging technique shown below eliminates this problem. Residue Vi+1 061002-03 Residue VREF(i)=VREF(i-1)/2k Σ + VREF(i)=VREF(i-1)/2k VREF(i+1)=VREF(i)/2k k-bit ADC k-bit DAC k-bits Clock S/H - i-th stage Vi-1 Vi Clock S/H Σ + VREF(i+1)=VREF(i)/2k k-bit ADC k-bit DAC k-bits - i+1-th stage Note: the reference voltage of the previous stage (i-1) is divided by 2k to get the reference voltage for the present stage (i), VREF(i), and so forth. CMOS Analog Circuit Design © P.E. Allen - 2010
- 16. Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-23 Subranging, Multiple-Bit, Pipeline ADCs Illustration of a 2-stage, 2-bits/stage pipeline ADC: Comments: • Resolution of the comparators for the following stages increases but fortunately, the tolerance of each stage decreases by 2k for every additional stage. • Removes the frequency limitation of the amplifier Stage 1 Stage 2 11 10 01 00 11 VREF 0.7500VREF 0.5000VREF 0.4375VREF 0.3750VREF 0.3125VREF 0.2500VREF 0 Time Voltage 10 01 00 Clock 1 Clock 2 Digital output word = 01 10 Fig.10.8-15 CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-24 Implementation of the DAC in the Multiple-Bit, Pipeline ADC Circuit: Comments: • A good compromise between area and speed • The ADC does not need to be a flash or parallel if speed is not crucial • Typical performance is 10 bits at 50Msamples/sec + - + - + - + - Analog Out VREF Vin* R R 1 1 0 1 R 0 R 0 0 0 0 OFF ON OFF OFF Fig.10.8-16 CMOS Analog Circuit Design © P.E. Allen - 2010
- 17. Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-25 Example 380-2 - Examination of error in subranging for a 2-stage, 2-bits/stage pipeline ADC The stages of the 2-stage, 2-bits/stage pipeline ADC shown below are ideal. However, the second stage divides VREF by 2 rather than 4. Find the ±INL and ±DNL for this ADC. Solution Examination of the first stage shows that its output, Vout(1) changes at Vin(1) VREF = 14 , 24 , Vin(1) 34 , and 2-bit ADC VREF VREF 44 . The output of the first stage will be Vin(2) 2-bit DAC Σ b0 b1 Vout(1) VREF = Vout(1) b0 2 + b1 4 . The second stage changes at Vin(2) VREF = 18 , 28 , 38 2-bit ADC VREF VREF 2 2 Fig.10.8-17 , and 48 where Vin(2) = Vin(1) - Vout(1). b2 b3 The above relationships permit the information given in the following table. 2-bit DAC Vout(2) CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-26 Example 380-2 - Continued Output digital word for Ex. 380-2: Vin(1) b0 b1 Vout(1) Vin(2) VREF VREF VREF b2 b3 Ideal Ouput b0 b1 b2 b2 0 0 0 0 0 0 0 0 0 0 0 1/16 0 0 0 1/16 0 0 0 0 0 1 2/16 0 0 0 2/16 0 1 0 0 1 0 3/16 0 0 0 3/16 0 1 0 0 1 1 4/16 0 1 4/16 0 0 0 0 1 0 0 5/16 0 1 4/16 1/16 0 0 0 1 0 1 6/16 0 1 4/16 2/16 0 1 0 1 1 0 7/16 0 1 4/16 3/16 0 1 0 1 1 1 8/16 1 0 8/16 0 0 0 1 0 0 0 9/16 1 0 8/16 1/16 0 0 1 0 0 1 10/16 1 0 8/16 2/16 0 1 1 0 1 0 11/16 1 0 8/16 3/16 0 1 1 0 1 1 12/16 1 1 12/16 0 0 0 1 1 0 0 13/16 1 1 12/16 1/16 0 0 1 1 0 1 14/16 1 1 12/16 2/16 0 1 1 1 1 0 15/16 1 1 12/16 3/16 0 1 1 1 1 1 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Ideal Finite Characteristic -DNL=0LSB -INL=2LSB INL=0LSB +DNL=2LSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Analog Input Voltage Digital Output Code Comparing the actual digital output word with the ideal output word gives the following: +INL = 0LSB, -INL = 0111-0101 = -2LSB, +DNL = (1000-0101) - 1LSB = +2LSB, and -DNL = (0101-0100) - 1LSB = 0LSB. CMOS Analog Circuit Design © P.E. Allen - 2010
- 18. Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-27 Example of a Multiple-Bit, Pipeline ADC Two-stages with 5-bits per stage resulting in a 10-bit ADC with a sampling rate of 5Msamples/second. Architecture: Vin Vin* S/H MSB ADC DAC Increment by 1 Vr1 LSB ADC DAC MSBs LSBs Vr2 Fig.10.8-21 Features: • Requires only 2n/2-1 comparators • LSBs decoded using 31 preset charge redistribution capacitor arrays • Reference voltages used in the LSBs are generated by the MSB ADC • No op amps are used CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-28 Example of a Multiple-Bit, Pipeline ADC - Continued MSB Conversion: Operation: 1.) Sample Vin* on each 32C capacitance autozeroing the comparators 2.) Connect each comparator to a node of the resistor string generating a thermometer code. + - Vin* + - Vin* VREF R32 R31 + - Vin* + - Vin* Latch Bank and Binary Encoder Vin* + - 32C Vin* + - 32C Vin* + - 32C VRi -Vin* Vin* + - 32C R30 VRi Ri R2 R1 DAC Analog MUX Vr2 Vr1 MSB Outpu Fig.10.8-22 MSBs CMOS Analog Circuit Design © P.E. Allen - 2010
- 19. Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-29 Example of a Multiple-Bit, Pipeline ADC - Continued LSB Conversion: Operation: 1.) MSB comparators are preset to each of the 31 possible digital codes. 2.) Vr1 and Vr2 are derived from the MSB conversion. 3.) Preset comparators will produce a thermometer code to the encoder. Comments: • Requires two full clock cycles • Reuses the comparators • Accuracy limited by resistor string and its dynamic loading • Accuracy also limited by the capacitor array • Comparator is a 3-stage, low-gain, wide-bandwidth, using internal autozeroing Latch Bank and Binary Encoder LSB Output Vr2 ADC set to Code 11111 Vr1 Vin* Vr2 ADC set to Code 11110 Vr1 Vin* Vr2 ADC set to Code 00010 Vr1 Vin* Vr2 ADC set to Code 00001 Vr1 Vin* + - 16C 8C 4C 2C C Vr2 Vr1 Switches set to Code Fig.10.8-23 C CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-30 Digital Error Correction Like many of the accuracy enhancing techniques, there are particular applications where certain correcting techniques are useful. In the pipeline, analog-digital converter, a technique called digital error correction is used to remove the imperfections of the components. Pipeline ADC: vIN* Stage 2 Stage 1 B bits B bits Stage K B bits KB bits Digital Logic 041007-11 Operation: 1.) Stage 1 resolves the analog input signal to within one of B subranges which determines the first B bits. 2.) Stage 1 then creates the analog residue (analog input – quantized analog output) and passes on to Stage 2 by either amplifying or subranging. 3.) Stage 2 repeats this process which ends with Stage K. CMOS Analog Circuit Design © P.E. Allen - 2010
- 20. Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-31 Comparator Error in a Pipeline ADC Subranging Pipeline ADC Example (B =2, K = 3): Ideal ADC ADC with first stage erorr Stage 1 Stage 2 Clock 1 Clock 2 VREF 0.75VREF 0.50VREF Vin* = 0.45VREF 0.25VREF 0 Digital output word = 01 11 First Stage Comparator 0.75VREF 0.50VREF Error Vin* = 0.45VREF Time Stage 3 Clock 3 00 Stage 1 Stage 2 Clock 1 Clock 2 Time VREF 0.25VREF 0 Stage 3 Clock 3 Digital output word = 10 00 041007-14 00 Note that if the comparator in the first stage makes the wrong choice, the converter cannot recover as shown in the example on the right. CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-32 Digital Error Correction – Continued Digital error correction uses one of the bits of each stage (except the first) to correct for any errors caused by the previous stage. Subranging Pipeline ADC Example (B =2, K = 3) using Digital Error Correction: ADC with first stage erorr ADC with Digital Error Correction Stage 1 Stage 2 11 10 01 00 11 10 01 00 Clock 1 Clock 2 First Stage Comparator VREF Error 0.75VREF 0.50VREF Vin* = 0.45VREF 0.25VREF 0 Digital output word = 01 00 Stage 1 Stage 2 0.75VREF 0.50VREF Vin* = 0.45VREF 11 10 01 00 Time Stage 3 Clock 3 00 Stage 3 11 10 01 00 111→101 110→100 101→11 100→10 011→01 010→00 001→-01 000→-10 Clock 1 Clock 2 111→101 110→100 101→11 100→10 011→01 010→00 001→-01 000→-10 Time VREF 0.25VREF 0 Clock 3 Digital output word = 10 -01 041007-15 00 Corrected digital output word = 01 11 00 Comments: • Add a correcting bit to the following stage to correct for errors in the previous stage. • The subranging or amplification of the next stage does not include the correcting bit. • Correction can be done after all stages of the pipeline ADC have converted or after each individual stage. CMOS Analog Circuit Design © P.E. Allen - 2010
- 21. Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-33 12-Bit Pipeline ADC with Digital Error Correction Self-Calibration† Digital Error Correction: • Avoids saturation of the next stage • Reduces the number of missing codes • Relaxed specifications for the comparators • Compensates for wrong decisions in the coarse quantizers Self-Calibration: • Can calibrate the effects of the DAC nonlinearity and gain error • Can be done by digital or analog methods or both † J. Goes, et. al., CICC’96 DAC ADC S/H vin 3 bits DAC ADC 3 bits DAC ADC 3 bits DAC ADC 3 bits ADC 4 bits 12 bits Digital Error Correction Logic Clock Fig. 11-30 CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-34 Digital Error Correction using B.5-Bit Pipeline Stages The top and bottom comparators can be removed to achieve digital error correction more efficiently. Input-output characteristics for different per-stage resolutions (B = 1, 2, and 3): vin 9 16 11 16 13 16 B = 3 VREF 061002-01 vout vin VREF VREF 2 0 VREF 2 − −VREF Offset Correction Range B = 1 1 4 -1 4 − 0 VREF −VREF VREF 2 2 VREF vout vin Offset Correction Range 5 8 B = 2 1 8 3 8 -5 8 -3 8 -1 8 − 0 VREF −VREF VREF 2 2 VREF vout Offset Correction Range -1 16 1 16 -13 16 -11 16 -9 16 -7 16 -5 16 -3 16 3 16 5 16 7 16 − 0 VREF −VREF VREF 2 2 VREF 2B+1 . If all else is ideal, the offset voltage correction range is equal to ± CMOS Analog Circuit Design © P.E. Allen - 2010
- 22. Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-35 TIME-INTERLEAVED ADC CONVERTERS Time-Interleaved Analog-Digital Converters Slower ADCs are used in parallel. T1 Illustration: S/H N-bit ADC No. 1 T2 S/H TM S/H Vin N-bit ADC No. 2 N-bit ADC No. M N-bit ADC No. 1 N-bit ADC No. 2 N-bit ADC No. M T=TC M Comments: • Can get the same throughput with less chip area • If M = N, then a digital word is converted at every clock cycle • Multiplexer and timing become challenges at high speeds Digital word out T1 T2 TM T1+TC t T2+TC TM+TC Fig.10.8-20 CMOS Analog Circuit Design © P.E. Allen - 2010 Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-36 SUMMARY Type of ADC Primary Advantage Primary Disadvantage Flash or parallel Fast Area is large if N 6 Interpolating Fast Requires accurate interpolation Folding Fast Bandwidth increases if no S/H used Multiple-Bit, Pipeline Increased number of bits Slower than flash Time-interleaved Small area with large throughput Precise timing and fast multiplexer Typical Performance: • 6-8 bits • 500-2000 Msamples/sec. • The ENOB at the Nyquist frequency is typically 1-2 bits less that the ENOB at low frequencies. • Power is approximately 0.3 to 1W CMOS Analog Circuit Design © P.E. Allen - 2010