![Observations
• Logical effort describes relative ability of gate
topology to deliver current [defined to be 1(best
av. of charge and discharge both] for an
inverter)
• Electrical effort is the ratio of output to input
capacitance
• Delay increases with electrical effort
• Delay increases ---More complex gates have
greater logical effort and parasitic delay
8
• Logical effort describes relative ability of gate
topology to deliver current [defined to be 1(best
av. of charge and discharge both] for an
inverter)
• Electrical effort is the ratio of output to input
capacitance
• Delay increases with electrical effort
• Delay increases ---More complex gates have
greater logical effort and parasitic delay](https://image.slidesharecdn.com/advd-lecture7logicaleffort-170108081630/85/Advd-lecture-7-logical-effort-8-320.jpg)
![T-network Delay Model Of wire
• Star-delta-transformation
• Vout=ZBC/(ZAB+ZBC)
• Vout=[(2/RC)/(S+2/RC)]*(1/S)
• =(1/s)-1/(s+2/RC)
• =U(t)[1-exp(-2/RC)t]
• FOR V50% delay
• tp=(RC ln2)/2=0.35 RC
• Star-delta-transformation
• Vout=ZBC/(ZAB+ZBC)
• Vout=[(2/RC)/(S+2/RC)]*(1/S)
• =(1/s)-1/(s+2/RC)
• =U(t)[1-exp(-2/RC)t]
• FOR V50% delay
• tp=(RC ln2)/2=0.35 RC](https://image.slidesharecdn.com/advd-lecture7logicaleffort-170108081630/85/Advd-lecture-7-logical-effort-30-320.jpg)
![Chain Of Inverters— BEST NO OF STAGES
C2
C1
Ci
CL
1 u u2
uN-1
In Out
uopt = e
gu= gav x [2 µ / (γ+μ)]
gd= gav x [2 γ / (γ+μ)]
C2
C1
Ci
CL
1 u u2
uN-1
In Out
uopt = e](https://image.slidesharecdn.com/advd-lecture7logicaleffort-170108081630/85/Advd-lecture-7-logical-effort-48-320.jpg)
Advd lecture 7 logical effort
- 1. Digital VLSI Design • Full Automation • Maximum benefit of scaling • High speed , • low power • Robustness • Full Automation • Maximum benefit of scaling • High speed , • low power • Robustness
- 2. Need of simple delay model • Delay depends on many factors—charge, discharge, parasitic, w/L, fan in- fanout, topology • Existing delay models do not give clear indication of contribution of each factor • Circuit designers waste too much time simulating and tweaking circuits 2 • Delay depends on many factors—charge, discharge, parasitic, w/L, fan in- fanout, topology • Existing delay models do not give clear indication of contribution of each factor • Circuit designers waste too much time simulating and tweaking circuits
- 3. Using LE in design of inverter chain 3 Using LE in design of inverter chain
- 4. CKT DESIGN PROBLEMS • Chip designers face a bewildering array of choices. • What is the best circuit topology for a function? • How large should the transistors be? • How many stages of logic give least delay? 4 • Chip designers face a bewildering array of choices. • What is the best circuit topology for a function? • How large should the transistors be? • How many stages of logic give least delay?
- 5. Need of simple delay model • Circuit designers waste too much time simulating and tweaking circuits • High speed logic designers need to know where time is going in their logic • CAD engineers need to understand circuits to build better tools 5 • Circuit designers waste too much time simulating and tweaking circuits • High speed logic designers need to know where time is going in their logic • CAD engineers need to understand circuits to build better tools
- 6. Delay in a Logic Gate 6
- 7. Delay contributors • τ is speed of basic transistor • p-intrinsic delay of the gate due to its own internal capacitances • h—combines the effect of external load with sizes of transistors • g– effect of circuit topology 7 • τ is speed of basic transistor • p-intrinsic delay of the gate due to its own internal capacitances • h—combines the effect of external load with sizes of transistors • g– effect of circuit topology
- 8. Observations • Logical effort describes relative ability of gate topology to deliver current [defined to be 1(best av. of charge and discharge both] for an inverter) • Electrical effort is the ratio of output to input capacitance • Delay increases with electrical effort • Delay increases ---More complex gates have greater logical effort and parasitic delay 8 • Logical effort describes relative ability of gate topology to deliver current [defined to be 1(best av. of charge and discharge both] for an inverter) • Electrical effort is the ratio of output to input capacitance • Delay increases with electrical effort • Delay increases ---More complex gates have greater logical effort and parasitic delay
- 9. Estimation of Estimation of
- 10. CMOS Ring Oscillator Circuit • An odd number of inverter circuits connected serially with output brought back to input will be astable and can be used an an oscillator (called a ring oscillator) • Ring oscillators are typically used to characterize a new technology as to its intrinsic device performance • Frequency and stage are related as follows: f = 1/T = 1/(2nP) where n is the number of stages and P is the stage delay • An odd number of inverter circuits connected serially with output brought back to input will be astable and can be used an an oscillator (called a ring oscillator) • Ring oscillators are typically used to characterize a new technology as to its intrinsic device performance • Frequency and stage are related as follows: f = 1/T = 1/(2nP) where n is the number of stages and P is the stage delay
- 11. Ring Oscillator—COMPARING DIFFERENT TECHNOLOGIES v0 v1 v5 v1 v2v0 v3 v4 v5 v0 v1 v5 v1 v2v0 v3 v4 v5 T = 2 tp N 2 N tp >> tf +tr
- 14. Observations • More complex gates have larger logical efforts • Logical efforts grow with increase in no. of inputs • Complex gates exhibit high g, greater delay 14 • More complex gates have larger logical efforts • Logical efforts grow with increase in no. of inputs • Complex gates exhibit high g, greater delay
- 15. Parasitic delay • It is fixed for a gate • More complex gate—higher parasitic delay • Ref. Pinv=1 (inverter parasitic delay ) • For other gates , parasitic delay is written in terms of pinv 15 • It is fixed for a gate • More complex gate—higher parasitic delay • Ref. Pinv=1 (inverter parasitic delay ) • For other gates , parasitic delay is written in terms of pinv
- 17. How to compute Pinv • For inv. g=1, dabs= τ(h+pinv) • In a given tech., plot d vs. h • Plot would be st. line with slope τ, & intercept- (pinv × τ) • Pinv can be estimated after obtaining τ • Draw similar plot for other gates • Once τ is obtained , g and p of other gates can be found out. 17 • For inv. g=1, dabs= τ(h+pinv) • In a given tech., plot d vs. h • Plot would be st. line with slope τ, & intercept- (pinv × τ) • Pinv can be estimated after obtaining τ • Draw similar plot for other gates • Once τ is obtained , g and p of other gates can be found out.
- 19. Choice Of Standard Reference
- 20. Calculating delay of an inverter 20
- 21. Delay of 2 input Nand gate
- 22. Delay of 2 input NOR gate
- 24. Computing Intrinsic Transistor Capacitance • Intrinsic PN junction capacitance of the driving circuit must be added to the load capacitance Cload • Consider the inverter example at left: – Area and perimeter of the PMOS and NMOS transistors are calculated from the layout and inserted into the circuit model • NMOS drain area = Wn x Ddrain • PMOS drain area = Wp x Ddrain • NMOS drain perimeter = 2 (Wn + Ddrain) • PMOS drain perimeter = 2 (Wp + Ddrain) • SPICE simulations were done (bottom left) for a fixed extrinsic load of 100fF with increasing transistor width (Wp/Wn = 2.75) – Results show diminishing returns beyond a certain Wn (say about 6 um) due to effect of the increasing drain capacitance on the overall capacitive load • Intrinsic PN junction capacitance of the driving circuit must be added to the load capacitance Cload • Consider the inverter example at left: – Area and perimeter of the PMOS and NMOS transistors are calculated from the layout and inserted into the circuit model • NMOS drain area = Wn x Ddrain • PMOS drain area = Wp x Ddrain • NMOS drain perimeter = 2 (Wn + Ddrain) • PMOS drain perimeter = 2 (Wp + Ddrain) • SPICE simulations were done (bottom left) for a fixed extrinsic load of 100fF with increasing transistor width (Wp/Wn = 2.75) – Results show diminishing returns beyond a certain Wn (say about 6 um) due to effect of the increasing drain capacitance on the overall capacitive load
- 25. MINIMUM DELAY ~ ZERO DELAY
- 26. R= Wp/Wn
- 27. Non zero value
- 28. Area x Delay Figure of Merit • Increasing device width shows diminishing returns on propagation delay time • Define a figure of merit as area x delay for the inverter circuit – Increasing device width Wn shows a minimum in area x delay product • Unconstrained increase in transistor width in order to improve circuit delay is often a poor tradeoff due to the high cost of silicon real estate on the wafer!! • Increasing device width shows diminishing returns on propagation delay time • Define a figure of merit as area x delay for the inverter circuit – Increasing device width Wn shows a minimum in area x delay product • Unconstrained increase in transistor width in order to improve circuit delay is often a poor tradeoff due to the high cost of silicon real estate on the wafer!!
- 29. Design a chain of inv. for min delay
- 30. T-network Delay Model Of wire • Star-delta-transformation • Vout=ZBC/(ZAB+ZBC) • Vout=[(2/RC)/(S+2/RC)]*(1/S) • =(1/s)-1/(s+2/RC) • =U(t)[1-exp(-2/RC)t] • FOR V50% delay • tp=(RC ln2)/2=0.35 RC • Star-delta-transformation • Vout=ZBC/(ZAB+ZBC) • Vout=[(2/RC)/(S+2/RC)]*(1/S) • =(1/s)-1/(s+2/RC) • =U(t)[1-exp(-2/RC)t] • FOR V50% delay • tp=(RC ln2)/2=0.35 RC
- 32. Delay in the presence of long wires
- 33. Design Of Inverter Chain For Min. Delay
- 34. Sizing a path for minimum delay EE141 34
- 35. Branching effort along a path → Used for sizing for delay EE141 35 Where BH is → Used for sizing for delay
- 36. Observations regarding F • F depends on only topology and loading • F is Indep. of transistor sizes • F is unchanged if inverters are added or removed EE141 36 • F depends on only topology and loading • F is Indep. of transistor sizes • F is unchanged if inverters are added or removed
- 37. Path Delay D • Sum of delay of all stages EE141 37
- 38. Condition for min. path delay EE141 38
- 40. Thus, minimum stage effort of each stage reqd. for min. delay along a path is We shd. choose transistor sizes such that stage effort is same for all blocks EE141 40 Thus, minimum delay achievable along a path is We shd. choose transistor sizes such that stage effort is same for all blocks
- 41. Example Compute for each stage Apply capacitance transformation backwards i EE141 41 Apply capacitance transformation backwards
- 42. Chain Of Inverters C2 C1 Ci CL 1 u u2 uN-1 In Out uopt = e C2 C1 Ci CL 1 u u2 uN-1 In Out uopt = e
- 43. Optimizing no of stages in a path for min. delay 43
- 44. To find optimum N EE14144If pinv = 0,
- 45. For Ň stages in chain with inverters Best delay per stage , d = gh + pinv d = ρ + pinv 45 For Ň stages in chain with inverters Best delay per stage , d = gh + pinv d = ρ + pinv
- 46. Graphical sol As pinv grows, adding inverters become less advantageous EE14146
- 47. Chain Of Inverters— BEST NO OF STAGES C2 C1 Ci CL 1 u u2 uN-1 In Out uopt = e C2 C1 Ci CL 1 u u2 uN-1 In Out uopt = e
- 48. Chain Of Inverters— BEST NO OF STAGES C2 C1 Ci CL 1 u u2 uN-1 In Out uopt = e gu= gav x [2 µ / (γ+μ)] gd= gav x [2 γ / (γ+μ)] C2 C1 Ci CL 1 u u2 uN-1 In Out uopt = e
- 49. For large N, delay expression- 49 For ρ = 4 Ď = log 4F X FO4
- 50. Where FO4 = fanout of 4 inverter delay FO4 DELAY 50 HERE ρ = gh = 1 x 4 = 4; so d = 5τ Thus for ρ = 4 Ď = log 4F X FO4 inverter delay
- 51. 51
- 52. Wrong no of stages 52
- 53. EE14153
- 54. Wrong size, L=1 Ρ=4 W 4sW 16 W C=1 C=4s C=16 54 Mis-sized Ρ=4 Ρ=4/ s Ρ= 4s D = ∑gh + ∑pinv = (4s + 4/s + 4 ) + 3 pinv = 15 units (s=1)
- 55. EE14155