Lecture 1 6844
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This document provides an overview of sequential circuits and flip-flops. It discusses how sequential circuits differ from combinational circuits in that their outputs depend not only on current inputs but also past inputs. Common types of sequential circuits like synchronous and asynchronous circuits are described. The document focuses on different types of flip-flops like SR, JK, D and T flip-flops. It provides details on how SR flip-flops can be constructed using NAND or NOR gates and how adding a clock input makes it a clocked SR flip-flop that only changes state on the clock edge. Examples of truth tables for SR and clocked SR flip-flops are also presented.
Lecture 1 6844
- 1. Welcome to My Presentation Lecture: 01 Engr: Suvadra Chowdhury Chief Instructor Electronics Chittagong Mohila Polytechnic Institute
- 2. 2019/9/16 PJF - 2Sequential Circuits Sequential Circuits Combinational Logic: Output depends only on current input Able to perform useful operations (add/subtract/multiply/…) Has no memory
- 3. 2019/9/16 PJF - 3Sequential Circuits Sequential Circuits (cont.) Sequential Logic: Output depends not only on current input but also on past input values, e.g., design a counter Need some type of memory to remember the past input values
- 4. 2019/9/16 PJF - 4Sequential Circuits Sequential Logic: Concept Sequential Logic circuits remember past inputs and past circuit state. Outputs from the system are “fed back” as new inputs With gate delay and wire delay The storage elements are circuits that are capable of storing binary information: memory.
- 5. 2019/9/16 PJF - 5Sequential Circuits Synchronous vs. Asynchronous There are two types of sequential circuits: Synchronous sequential circuit: circuit output changes only at some discrete instants of time. This type of circuits achieves synchronization by using a timing signal called the clock. Asynchronous sequential circuit: circuit output can change at any time (clockless).
- 6. Flip Flop (Sequential Circuits) What is Flip flop? Answer: In digital circuits, the flip- flop, is a kind of bi-stable multivibrator. It is a Sequential Circuits / an electronic circuit which has two stable states and thereby is capable of serving as one bit of memory , bit 1 or bit 0.
- 7. Introduction – Flip Flop They are 1 (HIGH) or 0 (LOW). Whenever we refer to the state of flip flop, we refer to the state of its normal output (Q). More complicated Flip flop complicated Flip flop complicated Flip flop complicated Flip flop use a clock as the control input. These clocked flip- flops are used whenever the input and output signals must occur within a particular sequence. They have two stable conditions and can be switched from one to the other by appropriate inputs. These stable conditions are usually called the states states states states of the circuit.
- 8. Introduction: Types Of Flip Flop 1. SR Flip Flop SR Flip Flop SR Flip Flop SR Flip Flop a.SR Flip Flop Active Low = NAND gates b. SR Flip Flop Active High = NOR gates 2. Clocked SR Flip Flop 3. JK Flip Flop 4. JK Flip Flop With Pre-set And Clear 5. T Flip Flop 6. D Flip Flop 7. Master-Slave Edge-Triggered Flip-Flop
- 9. The Used of Flip Flop For Memory circuits For Logic Control Devices For Counter Devices For Register Devices
- 10. SR Flip Flop The SR Flip Flop has two inputs, SET (S) and RESET (R). The SR Flip Flop has two outputs, Q and ¯ The Q output is considered the normal output and is the one most used. The other output ¯ is simply the compliment of output Q.
- 11. SR Flip Flop The most basic Flip Flop is called SR Flip Flop SR Flip Flop SR Flip Flop SR Flip Flop. The basic RS flip flop is an asynchronous device. In asynchronous device, the outputs is immediately changed anytime one or more of the inputs change just as in combinational logic circuits. It does not operate in step with a clock or timing. These basic Flip Flop circuit can be constructed using two NAND gates latch or two NOR gates latch. SR Flip Flop Active Low = NAND gates
- 12. SR Flip Flop - NAND GATE LATCH The NAND gate version has two inputs, SET (S) and RESET (R). Two outputs, Q as normal output and ¯ as inverted output and feedback mechanism. The feedback mechanism is required to form a sequential circuit by connecting the output of NAND-1 to the input of NAND-2 and vice versa. The circuit outputs depends on the inputs and also on the outputs.
- 13. SR Flip Flop - NAND GATE LATCH From the description of the NAND gate latch operation, it shows that the SET and RESET inputs are active LOW. The SET input will set Q = 1 when SET is 0 (LOW).RESET input will reset Q = 0 when RESET is 0 (LOW) In the prohibited/INVALID state both outputs are 1. This condition is not used on the RS flip-flop. The set condition means setting the output Q to 1. Likewise, the reset condition means resetting (clearing) the output Q to 0. The last row shows the disabled, or hold , condition of the RS flip-flop. The outputs remain as they were before the hold condition existed. There is no change in the outputs from the previous
- 14. SR Flip Flop - NOR GATE LATCH NOR GATE LATCH NOR GATE LATCH NOR GATE LATCH The latch circuit can also be constructed using two NOR gates latch. The construction is similar to the NAND latch except that the normal output Q and inverted output ¯
- 15. SR Flip Flop - NOR GATE LATCH S = 1, R = 0; This will set Q to 1, it works in SET mode operation. S = 1, R = 1; This condition tries to set and reset the NOR gate latch at the same time, and it produces Q = ¯ = 0 This is an unexpected condition and are not used. Since the two outputs should be inverse of each other. If the inputs are returned to 1 simultaneously, the output states are unpredictable. This input condition should not be used and when circuits are constructed, the design should make this condition SET=RESET = 1 never arises
- 16. SR Flip Flop - NOR GATE LATCH From the description of the NOR gate latch operation, it shows that the SET and RESET inputs are Active HIGH. The SET input will set Q = 1 when SET is 1 (HIGH). RESET input will reset Q when RESET is 1
- 17. The CLOCK When the clock changes from a LOW state to a HIGH state, this is called the positive- going transition (PGT) or positive edge triggered. When the clock changes from a HIGH state to a LOW state, it is called negative going transition (NGT) or negative edge triggered.
- 18. Clocked SR Flip Flop Additional clock input is added to change the SR flip- flop from an element used in asynchronous sequential circuits to one, which can be used in synchronous circuits. The clocked SR flip flop logic symbol that is triggered by the PGT is shown in Figure. Its means that the flip flop can change the output states only when clock signal makes a transition from LOW to HIGH.
- 19. Clocked RS Flip Flop The Truth Table in figure shows how the flip flop output will respond to the PGT at the clocked input for the various combinations of SR inputs and output. The up arrow
- 20. Clocked SR Flip Flop The clocked SR Flip Flop logic symbol that is triggered by the NGT is shown in Figure. It means that the Flip flop can change the output states only when clocked signal makes a transition from
- 21. 2019/9/16 PJF - 21Sequential Circuits SR Latch with Clock signal Latch is sensitive to input changes ONLY when C=1
- 22. Thank You