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Sequential Circuits
Sequential Circuits
• Consist of a combinational circuit to which storage
elements are connected to form a feedback path
• State: –the state of the memory devices now, also
called current state
• Next states and outputs are functions of inputs and
present states of storage elements
Two Types of Sequential Circuits
• Asynchronous sequential circuit
• Depends upon the input signals at any instant of time and
their change order
• May have better performance but hard to design
• Synchronous sequential circuit
• Defined from the knowledge of its signals at discrete instants
of time
• Much easier to design (preferred design style)
• Synchronized by a periodic train of clock pulses
SYNCHRONOUS SEQUENTIAL CIRCUITS
Memory elements
• Latch -—a level-sensitive memory element
• SR latches
• D latches
• Flip-Flop —- an edge-triggered memory element
• Master-slave flip-flop
• Edge-triggered flip-flop
• RAM and ROM —a mass memory element
Latches
• A latch is binary storage element
• Can store a 0 or 1
• The most basic memory
• Easy to build
• Built with gates (NORs, NANDs, NOT)
Latches
• SR LatchR
S
Q
Q
S R Q0 Q Q’
0 0 0
0
1
0
0
0 1 Q = Q0
Initial Value
Latches
• SR LatchR
S
Q
Q
S R Q0 Q Q’
0 0 0 0 1
0 0 1
1
0
0
0
1 0 Q = Q0
Q = Q0
Latches
• SR LatchR
S
Q
Q
S R Q0 Q Q’
0 0 0 0 1
0 0 1 1 0
0 1 0 0
0
1
1
0
1 Q = 0
Q = Q0
Latches
• SR LatchR
S
Q
Q
S R Q0 Q Q’
0 0 0 0 1
0 0 1 1 0
0 1 0 0 1
0 1 11
0
1
0
0 1
Q = 0
Q = Q0
Q = 0
Latches
• SR LatchR
S
Q
Q
S R Q0 Q Q’
0 0 0 0 1
0 0 1 1 0
0 1 0 0 1
0 1 1 0 1
1 0 0
0
1
0
1
1 0
Q = 0
Q = Q0
Q = 1
Latches
• SR LatchR
S
Q
Q
S R Q0 Q Q’
0 0 0 0 1
0 0 1 1 0
0 1 0 0 1
0 1 1 0 1
1 0 0 1 0
1 0 1
1
0
0
1
1 0
Q = 0
Q = Q0
Q = 1
Q = 1
Latches
• SR LatchR
S
Q
Q
S R Q0 Q Q’
0 0 0 0 1
0 0 1 1 0
0 1 0 0 1
0 1 1 0 1
1 0 0 1 0
1 0 1 1 0
1 1 0
0
1
1
1
0 0
Q = 0
Q = Q0
Q = 1
Q = Q’
0
Latches
• SR LatchR
S
Q
Q
S R Q0 Q Q’
0 0 0 0 1
0 0 1 1 0
0 1 0 0 1
0 1 1 0 1
1 0 0 1 0
1 0 1 1 0
1 1 0 0 0
1 1 1
1
0
1
1
0 0
Q = 0
Q = Q0
Q = 1
Q = Q’
0
Q = Q’
SR Latch
R
S
Q
Q
S R Q
0 0 Q0
0 1 0
1 0 1
1 1 Q=Q’=0
No change
Reset
Set
Invalid
S
R
Q
Q
S R Q
0 0 Q=Q’=1
0 1 1
1 0 0
1 1 Q0
Invalid
Set
Reset
No change
FlipFlops(Controlled Latches)
• Digital Devices consist of logic gates can preserve 1 bit (1
or 0)
• Types:
•S-R FlipFlop
•D FlipFlop
•J-K FlipFlop
•T Flipflop
S-R FlipFlops
• SR Latch with Control Input
C S R Q
0 x x Q0
1 0 0 Q0
1 0 1 0
1 1 0 1
1 1 1 Q=Q’
No change
No change
Reset
Set
Invalid
S
R
Q
Q
S
R
C
S
R
Q
Q
S
R
C
D FlipFlop
D Q
QCLK
I/P O/P
CLR
J-K Flip-Flops
D = JQ’ + K’Q
J Q
QK
T Flip-Flops
D = TQ’ + T’Q = T  Q
J Q
QK
T D Q
Q
T
D = JQ’ + K’Q
T Q
Q
THANK U

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Sequential circuits

  • 2. Sequential Circuits • Consist of a combinational circuit to which storage elements are connected to form a feedback path • State: –the state of the memory devices now, also called current state • Next states and outputs are functions of inputs and present states of storage elements
  • 3. Two Types of Sequential Circuits • Asynchronous sequential circuit • Depends upon the input signals at any instant of time and their change order • May have better performance but hard to design • Synchronous sequential circuit • Defined from the knowledge of its signals at discrete instants of time • Much easier to design (preferred design style) • Synchronized by a periodic train of clock pulses
  • 5. Memory elements • Latch -—a level-sensitive memory element • SR latches • D latches • Flip-Flop —- an edge-triggered memory element • Master-slave flip-flop • Edge-triggered flip-flop • RAM and ROM —a mass memory element
  • 6. Latches • A latch is binary storage element • Can store a 0 or 1 • The most basic memory • Easy to build • Built with gates (NORs, NANDs, NOT)
  • 7. Latches • SR LatchR S Q Q S R Q0 Q Q’ 0 0 0 0 1 0 0 0 1 Q = Q0 Initial Value
  • 8. Latches • SR LatchR S Q Q S R Q0 Q Q’ 0 0 0 0 1 0 0 1 1 0 0 0 1 0 Q = Q0 Q = Q0
  • 9. Latches • SR LatchR S Q Q S R Q0 Q Q’ 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 1 1 0 1 Q = 0 Q = Q0
  • 10. Latches • SR LatchR S Q Q S R Q0 Q Q’ 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 11 0 1 0 0 1 Q = 0 Q = Q0 Q = 0
  • 11. Latches • SR LatchR S Q Q S R Q0 Q Q’ 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 0 1 1 0 Q = 0 Q = Q0 Q = 1
  • 12. Latches • SR LatchR S Q Q S R Q0 Q Q’ 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 1 0 1 0 1 1 0 0 1 1 0 Q = 0 Q = Q0 Q = 1 Q = 1
  • 13. Latches • SR LatchR S Q Q S R Q0 Q Q’ 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 1 0 1 0 1 1 0 1 1 0 0 1 1 1 0 0 Q = 0 Q = Q0 Q = 1 Q = Q’ 0
  • 14. Latches • SR LatchR S Q Q S R Q0 Q Q’ 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 1 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 0 1 1 0 0 Q = 0 Q = Q0 Q = 1 Q = Q’ 0 Q = Q’
  • 15. SR Latch R S Q Q S R Q 0 0 Q0 0 1 0 1 0 1 1 1 Q=Q’=0 No change Reset Set Invalid S R Q Q S R Q 0 0 Q=Q’=1 0 1 1 1 0 0 1 1 Q0 Invalid Set Reset No change
  • 16. FlipFlops(Controlled Latches) • Digital Devices consist of logic gates can preserve 1 bit (1 or 0) • Types: •S-R FlipFlop •D FlipFlop •J-K FlipFlop •T Flipflop
  • 17. S-R FlipFlops • SR Latch with Control Input C S R Q 0 x x Q0 1 0 0 Q0 1 0 1 0 1 1 0 1 1 1 1 Q=Q’ No change No change Reset Set Invalid S R Q Q S R C S R Q Q S R C
  • 19. J-K Flip-Flops D = JQ’ + K’Q J Q QK
  • 20. T Flip-Flops D = TQ’ + T’Q = T  Q J Q QK T D Q Q T D = JQ’ + K’Q T Q Q

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