Sequential logic circuits flip-flop pt 1
Download as PPTX, PDF28 likes8,108 views
1) The document discusses sequential logic circuits and flip-flops. It defines sequential logic as circuits whose output depends on the previous inputs and states, requiring memory elements like flip-flops. 2) Flip-flops are described as basic memory storage elements that have two stable states and can be switched between them. Common types include SR, JK, D and T flip-flops. 3) SR and T flip-flops are discussed in detail. Their symbols, truth tables, and implementations using logic gates are presented. SR flip-flops can be built using NOR or NAND gates and can be set, reset, or held in state based on input conditions.
Sequential logic circuits flip-flop pt 1
- 1. Sequential logic circuits Combinational logic circuit Sequential logic circuit Flip-flop Build flip-flop using logic gates 1
- 2. Objectives: • Define sequential logic circuit. • Differentiate between combinational logic circuit and sequential logic circuit. • Describe flip - flop. • Identify various types of flip-flops. • Build SR and T flip – flop using logic gates. • Draw the symbol and truth table of SR and T flip – flop. 1 2 3 4 5 6 2
- 3. Sequential & Combinational logic circuit Define sequential logic circuit. Differentiate between combinational logic circuit and sequential logic circuit. 1 2 3
- 4. Difference between Combinational & Sequential logic circuit Basic building blocks include: Basic building blocks include FLIP-FLOPS: Combinational Logic Circuits Sequential Logic Circuits 4
- 5. Sequential logic circuit • Sequential logic is the type of digital system that does not only depend on current input, but also the previous history of the system. • For that reason sequential logic requires memory elements to function. • The building blocks used to construct devices that store data are called flip-flops. S C R Q Q' 5
- 6. Sequential logic circuit • The output of circuit depends on the previous output and the present inputs. • The inputs must follow a specific sequence to produce a required output. • In order to follow a sequence of inputs the circuits must contain some form of memory to retain knowledge of those inputs, which have already occurred. • This memory is obtained by feedback connections, which are made so that history of the previous inputs is maintained. • Most sequential circuit elements are known as Bistables or Flip Flops. S C R Q Q' 6
- 7. Sequential circuit have loops – these enable circuits to receive feedback Sequential logic circuit 7
- 8. Combinational logic circuit • Combinational logic is an interconnection of logic gates to generate a specific logic function where the inputs result in an immediate output, having no memory or storage capabilities. • They function only based on their inputs, and NOT based on clocks. 8
- 9. Combinational circuit is combination of various logic gates Combinational logic circuit 9
- 10. Flip-Flop Describe flip - flop.3 10
- 11. Flip-Flop • "Flip-flop" is the common name given to two-state devices which offer basic memory for sequential logic operations. • Flip-flops are heavily used for digital data storage and transfer and are commonly used in banks called "registers" for the storage of binary numerical data. 11
- 12. Flip-Flop • They have two stable conditions and can be switched from one to the other by appropriate inputs. These stable conditions are usually called the states of the circuit. • They are 1 (HIGH) or 0 (LOW). • Whenever we refer to the state of flip flop, we refer to the state of its normal output (Q). • More complicated Flip- Flop use a clock as the control input. These clocked flip-flops are used whenever the input and output signals must occur within a particular sequence 12 • This is the general flip-flop symbol.
- 13. Flip-Flop • Flip-flop are basic storage/memory elements. • Flip-flop are essentially 1-bit storage devices. • Types of flip-flops are: • 1. SR Flip-flop • 2. JK Flip-flop • 3. D Flip-flop • 4. T Flip-flop • Application of flip-flop: • 1. Counter 4. Logic controller • 2. Register 5. Frequency Divider • 3. Memory 13
- 14. SR Flip-Flop Identify various types of flip-flops. Build SR and T flip – flop using logic gates. Draw the symbol and truth table of SR and T flip – flop. 4 5 6 14
- 15. SR Flip-Flop • The simplest binary storage device. • SR Flip-flop have 2 inputs (SET & RESET) and 2 outputs (Q & Q’). NOTE: Q & Q’ are complements of each other • The SR flip flop is sometimes referred to as an SR latch. The term latch refers to its use as a temporary memory storage device. S R Q Q' 15
- 16. SR Flip-Flop • The SR Flip-flop have two inputs, SET (S) and RESET (R) • The SR Flip Flop has two outputs, Q and Q’. • The Q output is considered the normal output and is the one most used. • The other output Q’ is simply the complement of output Q. S R Q Q' 16
- 17. SR Flip-Flop • The most basic Flip-Flop. • The basic RS flip flop is an asynchronous device. • In asynchronous devices, the outputs are immediately changed anytime one or more of the inputs change just as in combinational logic circuits. • It does not operate in step with a clock or timing. • These basic Flip Flop circuit can b constructed using two NAND gate latch or two NOR gates latch. • SR Flip Flop Active Low = NAND gates • SR Flip Flop Active High = NOR gates S R Q Q' 17
- 19. SR Flip-Flop Symbol: SR Flip-flop (Active HIGH) NOR gate SR Flip-flop (Active HIGH) Symbol 19
- 20. SR Flip-Flop Symbol: SR Flip-flop (Active LOW) NAND gate SR Flip-flop (Active LOW) Symbol 20
- 21. SR Flip-Flop Truth Table: SR Flip-flop (Active HIGH) S R Q Q' 0 0 NC NC No change. Latch remained in present state. 1 0 1 0 Latch SET. 0 1 0 1 Latch RESET. 1 1 0 0 Invalid condition. S' R' Q Q' 1 1 NC NC No change. Latch remained in present state. 0 1 1 0 Latch SET. 1 0 0 1 Latch RESET. 0 0 1 1 Invalid condition. S R Q Q' S R Q Q' SR Flip-flop (Active LOW) 21
- 22. Quick Revision NOR gate & Truth Table: 22
- 23. SR Flip-Flop Circuit: HOLD/LATCH Mode 23 • The analysis of a SR Flip Flop NOR: • S = 0, R = 0; This is the normal resting state of the circuit and it has no effect on the output states. Q and Q’ will remain in whatever state they were in prior to the occurrence of this input condition. It works in HOLD (no change) mode operation.
- 24. SR Flip-Flop Truth Table: HOLD/LATCH Mode 24
- 25. SR Flip-Flop Circuit: SET Mode 25 • Consider the input S = 1. Any time the input of a NOR gate is 1 the output is 0. So, the output of the second NOR gate is 0, i.e. Q’ = 0. • Q’ = 0 is fed back into the input of the first NOR gate. So, with R = 0, the output of the first NOR gate is 1, i.e. Q=1.
- 26. SR Flip-Flop Truth Table: SET Mode 26
- 27. SR Flip-Flop Circuit: RESET Mode 27 • Consider the input R = 1. Any time the input of a NOR gate is 1 the output is 0. So, the output of the first NOR gate is 0, i.e. Q = 0. • Q = 0 is fed back into the input of the second NOR gate. So, with S = 0, the output of the second NOR gate is 1, i.e. Q’=1.
- 28. SR Flip-Flop Truth Table: RESET Mode 28
- 29. SR Flip-Flop Circuit: INVALID Mode 29 • S = 1, R = 1; This condition tries to set and reset the NOR gate latch at the same time, it produces Q = Q’ = 0. This is an unexpected condition and is not used. • The two outputs should be the inverse of each other.
- 30. SR Flip-Flop Circuit: INVALID Mode 30 • If the inputs are returned to 1 simultaneously, the output states are unpredictable. • This input condition should not be used and when circuits are constructed, the design should make this condition SET=RESET=1 never arises.
- 31. SR Flip-Flop Circuit: INVALID Mode 31
- 33. 33 SR Flip-Flop Operation: AN ANIMATION OF THE FLIP-FLOP PROCESS FOR THE NOR-GATE. IN THIS ANIMATION, RED SIGNIFIES TRUE AND BLACK SIGNIFIES FALSE. (SOURCE)
- 34. SR NOR gate latch Truth Table: SR Flip-flop (Active HIGH) S R Q Q' 0 0 NC NC No change. Latch remained in present state. 1 0 1 0 Latch SET. 0 1 0 1 Latch RESET. 1 1 0 0 Invalid condition. S R Q Q' 34 • From the description of the NOR gate latch operation, it shows that the SET and RESET inputs are Active HIGH. • The SET input will set Q=1 when SET is 1 (HIGH). RESET input will reset Q when RESET is 1 (HIGH).
- 35. SR NOR gate latch Timing Diagram 35 • Exercise: Determine the output of NOR gate latch with Q initially 1 for the given input waveforms. • Example: Determine the output of NOR gate latch with Q initially 0 for the given input waveforms.
- 37. Quick Revision NAND gate & Truth Table: 37
- 38. SR Flip-Flop Circuit: INVALID Mode 38 • The analysis of a SR Flip Flop NAND: • S = 0, R = 0; This condition tries to set and reset the NAND gate latch at the same time. • It produces Q = Q’ =1
- 39. SR Flip-Flop Circuit: INVALID Mode 39 • This is an unexpected condition, since the two outputs should be inverses of each other. • If the inputs are returned to 1 simultaneously, the output states are unpredictable. • This input condition should not be used and when circuits are constructed, the design should make sue this condition. S=R=0 never arises. It is called INVALID/ PROHIBITED
- 40. SR Flip-Flop Circuit: INVALID Mode 40
- 41. 41 • The analysis of a SR Flip Flop NAND: • S = 1, R = 0; This will reset Q = 0. SR Flip-Flop Circuit: RESET Mode
- 42. 42 SR Flip-Flop Truth Table: RESET Mode
- 43. SR Flip-Flop Circuit: SET Mode 43 • Input, S = 0, R = 1 • This will set Q = 1.
- 44. SR Flip-Flop Truth Table: SET Mode 44
- 45. SR Flip-Flop Circuit: HOLD/LATCH Mode 45 • The analysis of a SR Flip Flop NOR: • S = 1, R = 1; This is the normal resting state of the circuit and it has no effect on the output states. Q and Q’ will remain in whatever state they were in prior to the occurrence of this input condition. It works in HOLD (no change) mode operation.
- 46. SR Flip-Flop Truth Table: HOLD/LATCH Mode 46
- 47. SR Flip-Flop Truth Table: S' R' Q Q' 1 1 NC NC No change. Latch remained in present state. 0 1 1 0 Latch SET. 1 0 0 1 Latch RESET. 0 0 1 1 Invalid condition. S R Q Q' SR Flip-flop (Active LOW) 47 • From the description of the NAND gate latch operation, it shows that the SET and RESET inputs are Active LOW. • The SET input will set Q=1 when SET is 0 (LOW). RESET input will reset Q=0 when RESET is 0 (LOW).
- 48. SR Flip-Flop Truth Table: S' R' Q Q' 1 1 NC NC No change. Latch remained in present state. 0 1 1 0 Latch SET. 1 0 0 1 Latch RESET. 0 0 1 1 Invalid condition. S R Q Q' SR Flip-flop (Active LOW) 48 • In the prohibited/INVALID state both outputs are 1. This condition is not used on the RS flip-flop. The set condition means setting the output Q to 1. • Likewise, the reset condition means resetting (clearing) the output Q to 0. The first row shows the disabled, or hold, condition of the RS flip- flop. The outputs remain as they were before the hold condition existed. There is no change in the outputs from the previous states. • The flip-flop memorizes the previous condition.
- 49. SR NAND gate latch Timing Diagram 49 • Exercise: Determine the output of NAND gate latch with Q initially 1 for the given input waveforms. • Example: Determine the output of NAND gate latch with Q initially 0 for the given input waveforms.