Lecture 2vlsi*design22_240222_074858.pdf
- 1. ‘- 1 Khulna University of Engineering & Technology Presented by Dr. Md Nur Kutubul Alam VLSI DESIGN AND TECHNOLOGY EE4121
- 2. Marc Heyns Basics of VLSI Technology Part 2: 2 Lithography is indispensible for defining locations and configurations of circuit elements/functions. Lithography is the designers “brush”
- 3. Marc Heyns Basics of VLSI Technology Part 2: 3 Process flow of photolithography 8) Develop inspect 5) Post-exposure bake 6) Develop 7) Hard bake UV Light/Laser Mask 4) Alignment and Exposure Resist 2) Spin coat 3) Soft bake 1) Vapor prime HMDS
- 4. Marc Heyns Basics of VLSI Technology Part 2: 4 Patterning by optical lithography Photolithography is a patterning process in which a photosensitive polymer is selectively exposed to light through a mask, leaving a latent image in the polymer that can then be selectively dissolved to provide patterned access to an underlying substrate. In general, a photolithography process requires three basic materials, light source, photo mask, and photoresist. Photoresist, a photosensitive material, has two types, positive and negative. The positive photoresist become more soluble after exposure to a light source. On the contrary, the negative photoresist become less soluble after exposure. The pattern on the mask is transferred to the photoresist through an exposure process.
- 5. Marc Heyns Basics of VLSI Technology Part 2: 5 Scanner exposure of a wafer ASML TWINSCAN NXT:1980Di Step-and-Scan system is a high-productivity, dual-stage immersion lithography tool designed for volume production 300-mm wafers at the sub 10-nm node. The system can handle more than 275 wafers (300mm) per hour. Current advanced lithography tool are based on step-and-scan projection lithography using 193nm UV light and immersion optics. UV light Reticle field size 128 mm × 104 mm 4:1 reduction lens Wafer Image exposure on wafer 1/4 of reticle field 32 mm × 26 mm Serpentine stepping pattern
- 6. Marc Heyns Basics of VLSI Technology Part 2: 6 Importance of wafer flatness Wafer geometry is critical to lithography application and has been driven by IC scaling in the past decades. Wafer geometry roadmap is driven by shrinking depth of focus (DOF) of lithography. DOF requirements are the same for un-patterned and patterned wafers. M. Goldstein, INTEL, Semicon Taiwan 2013
- 7. Marc Heyns Basics of VLSI Technology Part 2: 7 22-16nm SRAM fabricated with EUV Nanoscale dimensions by lithography resolution = k1. λ NA Exposure wavelength (λ) 436nm : g-line 365nm : i-line 248nm : Deep-UV (KrF) 193nm : Deep-UV (ArF) 13.5nm: Extreme UV (EUV) Lord Rayleigh Rayleigh equation defines litho roadmap
- 8. Marc Heyns Basics of VLSI Technology Part 2: 8 Lithography imaging principles A. Sekiguchi, IEDM Tutorial 2016 Because the mask essentially acts as a set of slits, we get diffraction within the optical lithography system. The more diffraction orders that are captured by the lens, the more accurate the mask is reproduced. The essential distance information is already contained in the first order diffraction.
- 9. Marc Heyns Basics of VLSI Technology Part 2: 9 Projection (objective) lens system: represented by a 2-lens system illuminator Lens pupil, defines NA wafer reticle ‘effective light source’ → theory: coherent point source → reality: partial coherent light source Light source NA : Annular capture range of the lens NA = n sin q → n = refr. index =1 for air q max max Note: for uniform wafer illumination → lens pupil and image of light source are in same plane Simplified projection tool
- 10. Marc Heyns Basics of VLSI Technology Part 2: 12 Light diffraction Diffraction of light occurs when a light wave passes by a corner or through an opening or slit that is physically the approximate size of, or even smaller than that light's wavelength. – radiation will spread and appears in patterns if projected on a screen – intensity distribution produced: dependent on distance between slit and screen: • short distance: Fresnel or near-field diffraction – contact printers • long distance: Fraunhofer or far-field diffraction – steppers or scanners Principle of Huygens: each point on a wave front may be regarded as a new point source of waves. These sources are equal in phase and intensity plane wave of monochromatic coherent light
- 11. Marc Heyns Basics of VLSI Technology Part 2: 14 Diffraction orders a1 a3 a2 • +2 • +1 • 0 • -1 • -2 Diffraction pattern Objective lens with NA Wafer plane Coherent normal incident light Accuracy of reconstruction of the image – depends on the amount of diffraction orders captured by the lens (amount of information transferred) – dependent on the diffraction pattern and on the NA Formed image = inverse Fourier transformation
- 12. Marc Heyns Basics of VLSI Technology Part 2: 17 Illustration of NA influence on imaging Reducing Numerical Aperture
- 13. 2𝑑𝑠𝑖𝑛𝜃 = 𝜆 𝑛 𝑑 = 𝑛𝜆 2𝑛 𝑠𝑖𝑛𝜃 = 𝑛𝜆 2 𝑁𝐴 If diffraction order n=1 and NA=1, 𝑑 = 𝜆 2 Light Mask Diffracted light Light Focused towards a point substrate Light Focused towards a point… Beam waist is given by diffraction limit Bragg’s law: Therefore, minimum width of a line you can draw on a photoresist is 𝜆 2
- 14. Marc Heyns Basics of VLSI Technology Part 2: 19 Depth of focus for normal incidence The optical path difference between the 0-th order and the order coming from the edge of the lens must be smaller than l/4. Variations in the surface heights of a processed wafer must be less than the optical Depth of Focus. Thus, for high resolution lithography the surface must be perfectly planar (flat). Large lens (large NA), small DOF Small lens (small NA), large DOF
- 15. Marc Heyns Basics of VLSI Technology Part 2: 23 Aerial image Threshold to define CD CD CD The areal image is the normalized light intensity distribution on the wafer.
- 16. Marc Heyns Basics of VLSI Technology Part 2: 24 Aerial image Threshold to define CD CD CD Resist Height after development Exposure Dose Threshold Dose Contrast curve for ideal resist Aerial Image Intensity Resist Height after development It Aerial image for two trenches Resist profile for ideal resist is insensitive to aerial image quality
- 17. Marc Heyns Basics of VLSI Technology Part 2: 26 Aerial image Resist height after development Exposure Dose Contrast curve for actual resist Aerial Image Intensity Resist height after development Aerial image Resist profile for real resist is very sensitive to aerial image quality D0 D1 I1 I0 The final resist profile is very sensitive to the areal image quality.
- 18. Marc Heyns Basics of VLSI Technology Part 2: 30 Dose-to-Size: 17.8 mJ/cm2 Target CD: 40 nm 40nm +10% 40nm -10% D+10% D-10% Quality metric on wafer: exposure latitude (EL) EL = ____________________ The higher the EL, expressed in %, the better obtained CD control: - illumination non-uniformity - errors in dose - swing curve effects - reflective notching …. D-10%CD - D+10%CD Dt Example: 40 nm 1:1 L/S Exposure latitude is an important quality metric to obtain a good control in the critical dimension (CD).
- 19. Marc Heyns Basics of VLSI Technology Part 2: 31 Max DoF Target CD 40 nm 40nm +10% 40nm -10% Example: 40 nm 1:1 L/S Quality metric on wafer: Depth of Focus (DoF) Maximum DoF = maximum focus range over which the CD deviation is smaller than +/- 10% of the target CD.
- 20. Marc Heyns Basics of VLSI Technology Part 2: 32 Positive tone chemically amplified DUV resist H+ H+ H+ H+ H+ H+ Resist coating exposure generation of small amount of acid (H + ) post-exposure bake chemical reaction using H + as a catalyst development dissolution of exposed areas 1 H+ is re-used 100-1000 times mask Typical resist for 248 (KrF) & 193nm (ArF) are positive tone resist, with transparent resins Poly Vinyl Phenol and with chemical amplification.
- 21. Marc Heyns Basics of VLSI Technology Part 2: 33 Chemical amplification exposure generation of small amount of acid (H + ) post-exposure bake (PEB) chemical reaction (often deprotection) using H + as a catalyst R: protection group, makes resin insoluble in base OR OH not soluble in developer soluble in developer + H+ backbone illumination = chemical amplification Photo acid generator Chemical amplification in resist is based on the action of a photo acid generator.
- 22. Marc Heyns Basics of VLSI Technology Part 2: 36 Standing waves i-line 248nm 193nm Reflection of light in transparent resist layer on flat substrate create standing waves. Strategies are needed to reduce the reflection.
- 23. Marc Heyns Basics of VLSI Technology Part 2: 37 Standing waves http://www.glenbrook.k12.il.us/gbssci/phys/mmedia/waves/swf.html 1 2 Depth in resist Absorbed energy Total thickness λ/4n Standing waves in photoresist: N = node A = antinode … standing wave patterns are produced as the result of the repeated interference of two waves of identical frequency while moving in opposite directions along the same medium. All standing wave patterns consist of nodes and antinodes. The nodes are points of no displacement caused by the destructive interference of the two waves. The antinodes result from the constructive interference of the two waves and thus undergo maximum displacement from the rest position.
- 24. Marc Heyns Basics of VLSI Technology Part 2: 38 Standing waves Depth in resist Absorbed energy Total thickness Remaining resist Development time Resist profile Issues with standing waves in the photoresist: • development rate slows down on each location where the amount of energy absorption was low • scalloping of resist sidewalls
- 25. Marc Heyns Basics of VLSI Technology Part 2: 39 Swing effect Variations of CD as a result of (resist) film thickness variations Typical example of effect of standing waves on CD variations:
- 26. Marc Heyns Basics of VLSI Technology Part 2: 41 Standing waves Resist 2 Resist 1 Illustration of impact of absorption and image contrast of resist on standing waves.
- 27. Marc Heyns Basics of VLSI Technology Part 2: 42 Reflection reduction : BARC layers resist BARC Bottom Anti-Reflective Coating (BARC): based on interference effects at resist- BARC interface • if process is optimized: reflections are strongly minimized or even avoided • swing effects are reduced or even avoided • standing waves and reflective notching are avoided • difficult to optimize BARC process
- 28. Marc Heyns Basics of VLSI Technology Part 2: 43 • The masking layers determine the accuracy by which subsequent processes can be performed. • The photoresist mask pattern prepares individual layers for proper placement, orientation, and size of structures to be etched or implanted. • Small sizes and low tolerances do not provide much room for positioning errors. • Overlay accuracy is gaining in importance due to double patterning pMOSFET nMOSFET -VSS +VDD S D D S G G n-type silicon substrate p-well p+ p+ n+ n+ n-well Polysilicon Metal IN OUT pMOSFET nMOSFET -VSS +VDD S D D S G G n-type silicon substrate p-well p+ p+ n+ n+ n-well Polysilicon Metal IN OUT -VSS +VDD S D D S G G p+ p+ p-well n+ n+ n-type silicon substrate n+ p+ pMOSFET nMOSFET Field oxide Interlayer Oxide Metal -VSS +VDD S D D S G G p+ p+ p-well n+ n+ n-type silicon substrate n+ p+ pMOSFET nMOSFET Field oxide Interlayer Oxide Metal Cross section of CMOS inverter Top view of CMOS inverter Importance of mask overlay accuracy
- 29. Marc Heyns Basics of VLSI Technology Part 2: 44 Design rules for advanced litho
- 30. Marc Heyns Basics of VLSI Technology Part 2: 45 Resolution enhancement techniques Mask Alternating PSM Attenuated PSM OPC/Assist features Design split (double exposure) Imaging system Off-axis illumination (annular, quasar, dipole, customized …)
- 31. Marc Heyns Basics of VLSI Technology Part 2: 64 Rayleigh equation defines litho roadmap NA k resolution l . 1 = Lord Rayleigh k1 factor ↓ Low k1 lithography (k1 ≥ 0.25) Resolution enhancement techniques, process control. Projection lens NA Dry lithography : ≤ 0.93 Immersion lithography : ≤ 1.35 EUV lithography: 0.25 – 0.?NA NA ↑ Exposure wavelength (λ) 436nm : g-line 365nm : i-line 248nm : Deep-UV (KrF) 193nm : Deep-UV (ArF) 13.5nm : Extreme UV (EUV) Wavelength λ ↓
- 32. Marc Heyns Basics of VLSI Technology Part 2: 65 Immersion lithography Giovanni Battista Amici – 1840, Oil-Immersion – 1855, Water immersion objective Ernst Abbe – 1877, First micro-lenses with homogeneous immersion for Carl Zeiss 1980, Werner Tabarelli – Basic patent for immersion lithography Immersion lithography allows to extend the NA above the 1.0 limit.
- 33. Marc Heyns Basics of VLSI Technology Part 2: 66 Immersion lithography Immersion lithography is a lithography enhancement technique that replaces the usual air gap between the final lens element and the photoresist surface with a liquid medium with a refractive index greater than one. The smaller wavelength in the liquid allows the imaging of smaller features. Immersion lithography technology allowed a step forward in resolution in the semiconductor industry. The challenge of this technology is how to deal with a purified medium (like water or oil) filling the space between the projection lens and the substrate. Water is currently used as the liquid.
- 34. Marc Heyns Basics of VLSI Technology Part 2: 67 r r f f 0 0 sin sin sin q h q h q h = = = NA Immersion lithography Improvements in resolution Snell’s law : nglass hr hglass h0
- 35. Marc Heyns Basics of VLSI Technology Part 2: 68 Immersion lithography Improvements in resolution nglass hr hglass h0 hf hr r r f f 0 0 sin sin sin q h q h q h = = = NA Snell’s law :
- 36. Marc Heyns Basics of VLSI Technology Part 2: 70 Fluid-in Fluid-out water The immersion fluid between the wafer and the lens substantially changes the light path, which enables higher angles of incident light (i.e. the Numerical Aperture can become larger than 1). stage wafer Lens Lens Air Dry Immersion Immersion Lithography ‘shower hood’ concept Immersion lithography Improvements in resolution
- 37. Marc Heyns Basics of VLSI Technology Part 2: 71 Patterning of critical dimensions Patterning of features at the critical dimensions (such as the gate) has become a complicated process. Si Gate HM BARC resist Si Gate HM Si Gate Si Gate Si BARC etch resist trim HM etch and trim Resist strip HM based gate etch Si HM removal Si Gate HM BARC resist Si Gate HM Si Gate Si Gate Si BARC etch resist trim HM etch and trim Resist strip HM based gate etch Si HM removal Bottom anti-reflection coatings (BARC) are introduced to avoid standing waves. Hard-mask layers (HM) improve the etch process as they have a higher etch resistance than photoresist. Trimming may be used to narrow the lines. This reduces the line width, but does not improve the device pitch (distance between two devices). A second litho step must be used to increase the device density. Optical proximity correction, adding sub-resolution features to the mask, is necessary to avoid line shortening effects and make uniform isolated and dense lines. Optical proximity effects originate from the limited amount of higher order spatial frequencies that can pass the lens (low pass filter) for image formation
- 38. Marc Heyns Basics of VLSI Technology Part 2: 73 Self-aligned double patterning (SADP) A. Sekiguchi, IEDM Tutorial 2016 Multiple exposure takes advantage of the fact that one can expose a wafer with a pattern, transfer the pattern/freeze it (on a resist or a memorization film), come back to the same wafer with a different mask set and expose a different pattern after overlaying the new image onto the old one using alignment marks.
- 39. Marc Heyns Basics of VLSI Technology Part 2: 74 Double line patterning double trench approach Spaces on reticle Positive resist Print trenches and etch HM Strip resist and 2nd photo Etch HM and strip resist Final etch and remove HM double line approach Print lines and etch HM Strip resist and 2nd photo Etch Strip resist and remove HM Lines on reticle Positive resist Multiple exposure allows to make narrow lines at small pitches, but this goes at the expense of a high cost due to the multiple litho and etch steps needed.
- 40. Marc Heyns Basics of VLSI Technology Part 2: 76 HM POLY Si Poly Si BARC HM Resist Litho Etch/strip Litho Etch/strip Double Line for Poly DP k1=0.14: 32nm hp at 0.85NA XT:1250i ArF immersion 0.85NA – Dipole resist 52nm at 130nm pitch LER(3s) 3.1nm HM etch&strip 38nm at 130nm pitch resist+HM 47nm at 130nm pitch LER(3s) 3.1nm Poly 32nm at 65nm pitch
- 41. Marc Heyns Basics of VLSI Technology Part 2: 81 SADP extendibility A. Sekiguchi, IEDM Tutorial 2016 The multiple exposure method can be easily extended by repeating the basic sequence multiple times. LE, LLE, LLLE, LELE...does lithography, followed by etch, or litho-litho-then etch, etc. It is important to remember that the overlay accuracy of one image to another is also an error
- 42. Marc Heyns Basics of VLSI Technology Part 2: 87 Nanoscale dimensions by lithography The cost of a lithography step scales with area, not wafers. Increasing wafer size means that the lithography costs increase as a fraction of total costs (from ≈ 25% for 150 mm wafers to ≈ 50% for 300 mm wafers). Multiple patterning schemes needed in current technologies cause a steep rise in lithography cost. EUV lithography is expected to bring lithography costs back under control, under the assumption that a sufficiently high wafer throughput can be obtained.
- 43. Marc Heyns Basics of VLSI Technology Part 2: 91 Extreme ultraviolet (EUV) lithography is the next step in lithography. It uses radiation of wavelength 13.5 nm. EUV lithography systems have the potential to reduce the resolution to below 10 nm. EUV lithography Because all matter absorbs EUV radiation, the optics for collecting the light (collector), conditioning the beam (illuminator) and pattern transfer (projection optics) must be housed in a near-vacuum environment.
- 44. Marc Heyns Basics of VLSI Technology Part 2: 92 EUV lithography • Extreme UltraViolet (EUV) is Electro Magnetic (EM) radiation at ~13.5 nm (92 eV), which falls into X-ray band. • EUV radiation is absorbed by almost all materials and gases, so the optics must be reflective and fully contained in vacuum. • The reticle too must be reflective, no pellicle can be used to keep defects out of focus. • All mirrors (including the reticle) use an alternating stack of layers (e.g. Mo/Si), with a theoretical maximum normal incidence reflectivity of ~74%. Keeping mirror count to a minimum is a priority. The electromagnetic spectrum
- 45. Marc Heyns Basics of VLSI Technology Part 2: 93 Buffer Low thermal expansion substrate Buffer Multilayer Low thermal expansion substrate substrate Absorber Buffer Multilayer 6o Incident EUV Reflected EUV EUV reflective mask architecture EUV lithography uses reflective optics, based on reflective multilayers. A large variety of multilayers have been made and their reflectivities measured over the years. For the EUV region around 100 eV, two remarkably successful combinations are molybdenum-silicon and molybdenum-beryllium. With Mo-Si, a normal-incidence reflectivity of 68% has been achieved at a wavelength of 13.4 nm; Mo-Be multilayers have achieved a reflectivity close to 70% at 11.4 nm. These relatively high reflectivities are the basis for current efforts in the field of EUV lithography. Wavelength (nm) Reflectivity
- 46. Marc Heyns Basics of VLSI Technology Part 2: 104 § Etching of film material transfers litho- defined pattern onto the wafer § Provides more control for small features § Material is lifted off during mask removal § Can be used when no good etch for film material is available § Not suited for small geometries Etching Liftoff Lithography Lithography Etching Strip mask (resists) Remove mask (resists) Liftoff Deposit film Pattern generation: etching vs lift-off
- 47. Marc Heyns Basics of VLSI Technology Part 2: 105 Resist Hard mask Resist Hard mask Hard mask Hard mask hard mask based etching Resist Resist normal etching Pattern is transferred from the photoresist layer into another material that is used as the masking material during etching. – To be used when the etch process provides limited selectivity towards resist (e.g. deep trench, gate, STI, damascene,… ) – Hard mask must be selectively removed after the etching process Hard mask based etching
- 48. Marc Heyns Basics of VLSI Technology Part 2: 106 Reactive +ions bombard surface Surface reactions of radicals + surface film Desorption of by-products Anisotropic etch Isotropic etch Sputtered surface material Chemical Etching Physical Etching Etch technology consists of a combination of chemical and physical dry etch mechanisms: Dry etching • Purely chemical etching (using only reactive neutral species) ⇒ isotropic etching. • Purely physical etching (using only charged ions) ⇒ anisotropic etching.
- 49. Marc Heyns Basics of VLSI Technology Part 2: 107 Because of their low density, most gas phase etching chemistries have rates that are too slow at room temperature. Increasing the rate requires exciting the reacting species to form radicals and giving these radicals kinetic energy. Electromagnetically coupled energy from an electrical discharge is used to create a plasma state. Plasma excitation Solar corona Fusion reactor Solar core Sparks Water plasma Flames Industrial reactor Aurora Nebula Plasma is by far the most common form of matter: plasma in stars and in tenuous space between stars makes up for over 99% of visible universe. Plasma is characterized by a high population density of charged particles: equal share of electrons and ions → plasma is conductive. Plasma for IC processing are typically weak, degree of ionization: 10-3 to 10-6.
- 50. Marc Heyns Basics of VLSI Technology Part 2: 108 Plasma can be generated by a high DC voltage across two electrodes. The voltage needed for this depends on the pressure and the electrode spacing (Paschen curve). DC plasma generation Left part of the curve: the particle number is too small for ionization and the electrons reach the anode without collisions (no avalanche). Right part of the curve: the electrons experience too many collisions of electrons in which they loose energy and a high potential is needed to provide sufficient energy for ionization. Pressure x electrode spacing (Torr cm) breakdown voltage (V) Paschen curve
- 51. Marc Heyns Basics of VLSI Technology Part 2: 111 RF plasma generation Usually an RF field is used to generate a plasma. The electrons pick up sufficient energy during the field oscillation to cause ionization. The plasma also shows the Paschen behaviour. The electrode capacitively coupled to the RF generator develops a negative DC bias and becomes the cathode. This is because upon initiating the plasma arc, more mobile electrons charge up the capacitively coupled electrode. No charge transfer via the capacitor is possible and the electrode retains negative bias. The other electrode is grounded and conductive. Therefore no charges build up and this electrode becomes the anode. As the plasma is conductive there is almost no voltage drop across it. A dark space develops in front of the cathode where most of the voltage drop occurs. In this area charged ions are accelerated by the field and directed towards the cathode.
- 52. Marc Heyns Basics of VLSI Technology Part 2: 118 Plasma etching (PE) • Substrates are placed on the grounded electrode • Low DC bias is generated • The energy of bombarding ions is not sufficient to sputter the substrate • Chemical species are produced in plasma • Removal of substrate materials occurs due to chemistry
- 53. Marc Heyns Basics of VLSI Technology Part 2: 119 Process gases Plasma MW or RF Process chamber By-products to the pump Remote plasma chamber Free radicals Heated plate In cases when free radicals are needed to enhance the chemical reactions, but you don’t want ion bombardment to avoid plasma-induced damage, a remote plasma system can be used. Remote plasma system Remote plasma is sometimes used to remove the photoresist right after the etch: O* + PR ⇒ H2O + CO + CO2 + ….
- 54. Marc Heyns Basics of VLSI Technology Part 2: 120 Reactive Ion Etching (RIE) Reactive Ion Etching (RIE) combines physical and chemical etching. The neutral gas in RF sputtering systems is replaced by chemically active species (atoms, radicals or ions) and chemically inert ions. The high anisotropy in RIE is due to the directional nature of the ion bombardment on the surface. The high selectivity arises from the details of the chemical interactions between the reactive species in the plasma and the substrate.
- 55. Marc Heyns Basics of VLSI Technology Part 2: 129 • Chemically reactive plasma is generated • Positive molecular ions are generated • Flux of chemically reactive radicals is reaching the substrate • Both ion sputtering and chemical etching can be observed Reactive Ion Beam Etching (RIBE)
- 56. Marc Heyns Basics of VLSI Technology Part 2: 131 • The xenon fluoride is adsorbing at the substrate surface • The beam of argon ion is applied • The ions induce the dissociation of xenon fluoride molecules • Released florin radicals etch the substrate surface Chemically Assisted reactive Ion Beam Etching (CAIBE)
- 57. Marc Heyns Basics of VLSI Technology Part 2: 134 A fluorine source, such as SF6 or CF4 can be cracked by the plasma to produce F− radicals. The F− radicals will preferentially bind to exposed Si atoms, displacing other atoms sitting on these sites. Once 4 F− radicals have saturated the available bonds of a Si atom, the SiF4 will desorb as a volatile species. Bond energies: (ΔH°) – Si-Si: 52 kcal/mole (energy to break a bond in single crystal Si) – F-F: 36.6 kcal/mole (energy to break a bond in F2) – S-F: 68 kcal/mole (energy to break a bond in SF6) – C-F: 116 kcal/mole (energy to break a bond in CF4) – Si-F: 135 kcal/mole (energy supplied by creating a bond in SiF4) F2 and SF6 will etch Si with no additional supplied energy. CF4 will etch Si, but requires a little additional energy. Silicon etching: fluorine chemistry
- 58. Marc Heyns Basics of VLSI Technology Part 2: 135 Analogous to fluorocarbons, chlorocarbons can be cracked by the plasma, producing Cl− radicals, which can then combine with Si to form SiCl4, which is volatile and desorbs from the etched surface. Bond energies: (ΔH°) – Si-Si: 52 kcal/mole (energy to break a bond in single crystal Si) – Cl-Cl: 58 kcal/mole (energy to break a bond in Cl2) – C-Cl: 81 kcal/mole (energy to break a bond in CCl4) – Si-Cl: 90 kcal/mole (energy supplied by creating a bond in SiCl4) Chlorine etching always requires additional energy from the plasma, so it is always anisotropic. Silicon etching: chlorine chemistry