lecture one of fpga course on reconfig sys

ADVANCED RECONFIGURABLE SYSTEMS
USING VERILOG AND FPGAs
Dr Arsalan Habib Khawaja
School of Information Engineering
Lecture #1 – Introduction

KHAWAJA ARSALAN HABIB
• Present: Distinguished Associate Professor (SWUST)
Previous work experience
• Post Doctorate and PhD (UESTC, China)
• MSc Electronics Engineering (United Kingdom)
• Energy Research Training (Arizona State University USA)
• 01 Book (IEEE-Wiley Press)
• 30+ Top Publications
• 01 Patent in USA, 04 Patents in China, 02 Patents in
Pakistan
• Assistant Professor (National University of Sciences and
Technology, Pakistan QS World Ranking 334)

YOUR INTRODUCTION
• NAME
• COUNTRY
• EDUCATION
• PAST EXPERIENCE
• FUTURE PLANS AFTER THE MASTERS

What is Reconfigurable Computing?
• configurable (adj.) – written to permit
modification by users; able to be modified or
arranged differently
• computing (n.) – the procedure of calculating;
determining something by mathematical or
logical methods
• Reconfigurable computing – a procedure of
calculating that is able to be modified by users
• Any examples?

What is Reconfigurable Computing?
• In its current usage, the term reconfigurable
computing refers to some form of hardware
programmability
• Hardware that can be customized using some physical
control points
• Goal: to adapt at the logic level to solve specific
problems
• Why do we care?
• Certain applications aren’t well suited to
general-purpose computing model
• Exponential growth in available chip resources
– what to do with them?
• Other advantages (fast time-to-market,
performance competitive with custom ASIC,
bugs can be fixed in the field)

What Characterizes RC?
• Parallelism customized to meet design objectives
• Logic specialization to perform a specific function
• Hardware-level adaptation of functionality to meet
changing problem requirements
x
+
xi
w1 x
+
w2 x
+
w3 x
+
w4
yi
Example: 4-tap FIR
filter [DeHon 2000]

Temporal (Microprocessor) Systems
• Generalized – can perform many functions well
• Sequential – inherently constrained even with
multiple data paths
• Fixed logic – data sizes, number of
computational units, etc. cannot be changed
x4  x3 // x[i-3]
x3  x2 // x[i-2]
x2  x1 // x[i-1]
Ax  Ax + 1
x1  [Ax] // x[i]
t1  w1 x x1
t2  t1 + t2
…
Ax
t1
x1
x2
x3
x4
Ay
t2
w1
w2
w3
w4
ALU
t2  w2 x x2
t1  t1 + t2
t2  w3 x x3
t1  t1 + t2
t2  w4 x x4
t1  t1 + t2
Ay  Ay + 1
[Ay]  t1

Example: Comparison Operation
• Specialization? Check.
• Optimization? Check.
• Parallelism??
M1: process(CLK, A, B)
begin
if rising_edge(CLK) then
if (A > B) then
H <= A;
L <= B;
else
H <= B;
L <= A;
end if;
end if;
end process;
0
1
A
B
CLK
H
1
0
L
<

Example: Sorting an Array
A B
H L
A B
H L
A B
H L
A B
H L
0 1 2 3 4 5 6 7
in[8]
A B
H L
A B
H L
A B
H L
A B
H L
A B
H L
A B
H L
A B
H L
A B
H L
0 1 2 3 4 5 6 7
out[8]
A B
H L
A B
H L
A B
H L

Hardware Spectrum
• ASIC gives high
performance at cost of
programmability
• Processor is very
programmable but not
tuned to the application
• Reconfigurable hardware
is a nice compromise
Full Custom
ASIC
Gate Array
FPGA
PLD
GP Processor
SP Processor
Multifunction
Fixed Function
Cost
/
Performance

History of IC Technology
• 1947: First transistor (Shockley, Bell Labs)
• 1958: First integrated circuit (Kilby, TI)
• 1971: First microprocessor (4004, Intel)
• Today: six+ wire layers, 45nm feature
sizes

History of Reconfigurable Computing
• Earliest reconfigurable computer proposed in the
1960s (Gerald Estrin, UCLA) [1]
• Basic concepts well ahead of the enabling technology:
• Could only prototype a crude approximation
• The availability of high-density VLSI devices that use
programmable switches spurred current interest
• Current chips – contain memory cells that hold both
configuration and state information
• Only a partial architecture exists before programming
• After configuration, the device provides an execution
environment for a specific application
[1] G. Estrin et al., “Parallel Processing in a Restructurable Computer System,”
IEEE Trans. Electronic Computers, pp. 747-755, Dec. 1963.

Moore’s Law
• Exponential rate of increase in the number of
transistors per chip - Gordon Moore, Intel [1965]

Classifying Reconfigurable Systems
• Current reconfigurable computing systems can be
classified by three main design decisions [2]:
• Granularity of programmable hardware
• Low-level components with traditional ASIC design flow?
• More complex base units like multipliers, ALUs, etc.?
• Proximity of the CPU to the programmable hardware
• On the chip? On the bus? On the board? On the network?
• Capacity
• How many equivalent ASIC gates?
• How to allocate resources? Set ratios of memory to computation
to interconnect?
[2] W. Mangione-Smith et al., “Seeking Solutions in Configurable Computing,”
IEEE Computer, pp. 38-43, Dec. 1997.

LUT-based Logic Element
carry
logic
4-LUT
DFF
I1 I2 I3 I4
Cout
Cout
OUT
• Each LUT operates on four
one-bit inputs
• Output is one data bit
• Can perform any Boolean
function of four inputs
• 224
= 65536 functions (4096
patterns)
• The basic logic element can be more complex
(multiplier, ALU, etc.)
• Contains some sort of programmable interconnect

Coupling in a Reconfigurable System
Standalone Processing Unit
I/O
Interface
Attached Processing Unit
Workstation
Memory
Caches
Coprocessor
CPU
FU
• Some advantages of each?
• Some disadvantages?

Capacity Trends
Year
1985
Xilinx
Device
Complexity
XC2000
50 MHz
1K gates
XC4000
100 MHz
250K gates
Virtex
200 MHz
1M gates
Virtex-II
450 MHz
8M gates
Spartan
80 MHz
40K gates
Spartan-II
200 MHz
200K gates
Spartan-3
326 MHz
5M gates
1991
1987
XC3000
85 MHz
7.5K gates
Virtex-E
240 MHz
4M gates
XC5200
50 MHz
23K gates
1995 1998 1999 2000 2002 2003
Virtex-II Pro
450 MHz
8M gates*
2004 2006
Virtex-4
500 MHz
16M gates*
Virtex-5
550 MHz
24M gates*

The Density Computing Advantage
• Claim – reconfigurable processors offer a definite advantage over
general-purpose counterparts with regards to functional density [3]
• Computations per chip area per cycle time
• Will visit this concept in more detail on Thursday
[3] A. DeHon. “The Density Advantage of Configurable Computing,” IEEE
Computer, pp. 41-49, Apr. 2000.
Intel Pentium 4
Actel ProASIC

Introduction to the FPGA
• Field-Programmable Gate Arrays
• Literally, an array of logic gates that can be programmed
with new functionality in the field.
• Target Applications
• Image/video processing
• Cryptographic ciphers
• Military and aerospace applications
• What are the advantages of FPGA technology?
• Algorithmic agility / upload
• Cost efficiency
• Resource efficiency
• Throughput

Introduction (cont.)
• Major players in the FPGA industry:
• Chipmakers – device families
• Xilinx – Spartan, Spartan-II, Spartan-3, Virtex, Virtex-II
• Actel – eX, MX, SX, Axcelerator, ProASIC
• Altera – ACEX, FLEX, APEX, Cyclone, Mercury, Stratix
• Atmel – AT6000, AT40K
• Software developers – CAD tools
• Synopsys – FPGA Compiler
• Mentor Graphics – HDL Designer, ModelSim
• Synplicity – Synplify, Synplify Pro

FPGA Architecture
• FPGAs are composed of the following:
• Configurable Logic Blocks (CLBs)
• Programmable interconnect
• Input/Output Buffers (IOBs)
• Other stuff (clock trees, timers, memory, multipliers,
processors, etc.)
• CLBs contain a number of Look-Up Tables (LUTs) and
some sequential storage.
• LUTs are individually configured as logic gates, or can
be combined into n bit wide arithmetic functions.
• Architecture Specific

FPGA Architecture (cont.)
CLB CLB CLB CLB CLB
CLB CLB CLB CLB CLB
CLB CLB CLB CLB CLB
CLB CLB CLB CLB CLB
CLB CLB CLB CLB CLB
IOB IOB IOB IOB IOBc
IOB IOB IOB IOB IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
• Input/Output Buffers
(IOBs)
• Configurable Logic
Blocks (CLBs)
• Programmable
interconnect mesh
• Generic island-style
FPGA architecture

Summary
• Reconfigurable hardware – can be customized using some
physical control mechanism
• Goal is to adapt at the logic level to solve specific problems
• Programmable computational components and interconnect
• Certain applications are well-suited to reconfigurable hardware
• FPGA – Field-Programmable Gate Array
• More flexibility (compared to ASIC)
• Better cost efficiency (compared to ASIC)
• Greater resource efficiency (compared to CPU)
• Higher throughputs (compared to CPU)

System-on-Chip Design
Introduction to Zynq

Source: The Zynq Book
Traditional Architecture

FPGA with Soft Processor Core

Zynq Architecture

Embedded SoC Architecture

Implement Embedded SoC on Zynq

Source: Xilinx Video Tutorials
Zynq Highlights

ARM Processor Roadmap
Source: Xilinx White Paper: Extensible Processing Platform

Basic Design Flow for Zynq SoC

Zynq SoC Ecosystem

Xilinx Zynq
Zynq-7000 All Programmable
SoCs with Cortex-A9 MPCore
Altera Arria V & Cyclone V
Hard processor system (HPS)
with Cortex-A9 MPCore
Microsemi Smartfusion2
Cortex M3
Alternative Solutions

The Zynq Processing System

Application Processing Unit (APU)
APU programming is through Xlinx SDK

NEON Co-Processor
SIMD Execution for media and DSP applications

PS External Interfaces: MIO

Programmable Logic (PL) CLBs and IOBs

Basic Logic Elements (BLEs)
12 2 FPGA Architectures: An Overview

Switch Matrix
16 2 FPGA Architectures: An Overview

PL: Special Resources

AXI Interconnects and Interfaces
9 AXI interfaces
between PS and
PL.

Basic AXI Signaling – 5 Channels
1. Read Address Channel
2. Read Data Channel
3. Write Address Channel
4. Write Data Channel
5. Write Response Channel
Zynq Architecture 12-33 © Copyright 2012 Xilinx

The AXI Interface—AX4-Lite
No burst
Data width 32 or 64 only
– Xilinx IP only supports 32-bits
Very small footprint
Bridging to AXI4 handled
automatically by
AXI_Interconnect (if needed)
AXI4-Lite Read
AXI4-Lite Write

The AXI Interface—AXI4
Sometimes called “Full AXI” or “AXI
Memory Mapped”
– Not ARM-sanctioned names
Single address multiple data
– Burst up to 256 data beats
Data Width parameterizable
– 1024 bits
AXI4 Read
AXI4 Write

The AXI Interface—AXI4-Stream
No address channel, no read and write,
always just master to slave
– Effectively an AXI4 “write data” channel
Unlimited burst length
– AXI4 max 256
– AXI4-Lite does not burst
Virtually same signaling as AXI Data
Channels
– Protocol allows merging, packing, width
conversion
– Supports sparse, continuous, aligned,
unaligned streams
AXI4-Stream Transfer

Using Extended Multiplexed Input/Output
(EMIO) to Interface Between PS and PL

lecture one of fpga course on reconfig sys

Choice Among Various
Implementation Platforms
Source: Xcell Journal, no. 88, Q3 2014

Advantages of Zynq
Source: Xcell Journal, no. 88, Q3 2014

Academic Subjects to which Zynq is Relevant

Zedboard
Zynq device
DDR3 mem
VGA port
Ethernet
SD card

System-on-a-Board

System-on-Chip (SoC)

Design Flow for Zynq SoC
Source: Xilinx White Paper: Extensible Processing Platform

Automotive Applications
Lane and Road Sign Recognition

Computer Vision
Detection of Cars at a Junction

Smart
Home

Communication Systems
Wireless
Basestation
Satellite
Groundstation
Wired Network
Switches

Control and Instrumentation Systems
Industrial
Control
Room
Wind
Turbines
High Energy
Physics
Experiment

Medical Applications
MRI Scanning Robot Assisted Surgery

ZYBO General Purpose Input Output (GPIO)
Source: ZYBO Reference Manual

Pmod Connector
Source: ZYBO Reference Manual

lecture one of fpga course on reconfig sys

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