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Reconfigurable Computing: Systems historical contextualization Reasons behind FPGA(s)-based solution Marco D. Santambrogio: marco.santambrogio@polimi.it 3DDRESD  3rd Edition, Goglio 2008
Outline Basic Idea A bird’s eye view on the Reconfigurable Computing The roadmap Reasons behind Xilinx
What’s next Basic Idea A bird’s eye view on the Reconfigurable Computing The roadmap Reasons behind Xilinx
Reconfiguration The process of physically altering the location or functionality of network or system elements. Automatic configuration describes the way sophisticated networks can readjust themselves in the event of a link or device failing, enabling the network to continue operation. Gerald Estrin, 1960
Reconfigurable Computing Reconfigurable computing is defined as the study of computation using reconfigurable devices Christophe Bobda, 2007 Processor FPGA Full Custom Compilation time Performance low high low high
What’s next Basic Idea A bird’s eye view on the Reconfigurable Computing The RC dawn and the FPGA revolution Some !FPGA architecture The accademic efforts Choose the optimal hardware platform for a given application The roadmap Reasons behind Xilinx
The RC Dawn The Estrin Fix-Plus Machine, 1959 The Ramming Machine, 1977 Hartenstein’s  XPuter , 1980 mid-1980s: the FPGA revolution/era The PAM Machine, SPLASH II, PRISM, Garp, DISC, DPGA
Data Flow Machine (!FPGA) The Pact XPP Device The NEC-DRP Architecture The picoChip Reconfigurable Device PicoChip solution: Array of heterogeneous processors Communication flexibility between processors achieved through reconfigurable technology Array Processing Element Switch Matrix Inter-picoArray Interface
The Academic Efforts The Reconfigurable Architecture Workstation (RAW) - MIT The Matrix Architecture - MIT The Reconfigurable Multimedia Array Coprocessor (REMARC) - Stanford MorphoSys -  University of California, Irvine  Chimaera – Northwestern PipeRench - CMU RaPiD - University of Washington Garp – UC Berkeley Bee2- UC Berkeley
What are the drivers for this choice? Time: How long does it take to compute the answer? Area: How much silicon space is required to determined the answer? Costs: How much does it costs (performance, $)? Power: How much does it consume? Processor generally fixes computing area. Problem evaluated over time through instructions. FPGA can create flexible amount of computing area. Effectively, the configuration memory is the computing instruction.
What’s next Basic Idea A bird’s eye view on the Reconfigurable Computing The roadmap The 90% – 10% Rule Programmable System on a Chip Multi-FPGA Reasons behind Xilinx
The 90% – 10% Rule 90% of the execution is spent in  10% of the code Inner loops in algorithms Computational intense code 10% of the execution is spent in  90% of the code Exceptions User interaction The  10% computational intense code  has to be executed as hardware on  reconfigurable devices The  90% exception code  is run as executable files on  processors
Programmable System on a Chip No longer just a bunch of reconfigurable elements DSPs, GPP, reconfigurable elements, etc. etc...
Multi-FPGA Heterogeneous Multi-FPGA system
What’s next Basic Idea A bird’s eye view on the Reconfigurable Computing The roadmap Reasons behind Xilinx
Commercial FPGA Companies Lattice official webiste
Reconfigurable Multi-FPGA (taxonomy)  and FPGA vendors
Reconfigurable SoC (taxonomy)  and FPGA vendors
Xilinx FPGA and Configuration Memory
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3rd 3DDRESD: RC historical contextualization

  • 1. Reconfigurable Computing: Systems historical contextualization Reasons behind FPGA(s)-based solution Marco D. Santambrogio: marco.santambrogio@polimi.it 3DDRESD 3rd Edition, Goglio 2008
  • 2. Outline Basic Idea A bird’s eye view on the Reconfigurable Computing The roadmap Reasons behind Xilinx
  • 3. What’s next Basic Idea A bird’s eye view on the Reconfigurable Computing The roadmap Reasons behind Xilinx
  • 4. Reconfiguration The process of physically altering the location or functionality of network or system elements. Automatic configuration describes the way sophisticated networks can readjust themselves in the event of a link or device failing, enabling the network to continue operation. Gerald Estrin, 1960
  • 5. Reconfigurable Computing Reconfigurable computing is defined as the study of computation using reconfigurable devices Christophe Bobda, 2007 Processor FPGA Full Custom Compilation time Performance low high low high
  • 6. What’s next Basic Idea A bird’s eye view on the Reconfigurable Computing The RC dawn and the FPGA revolution Some !FPGA architecture The accademic efforts Choose the optimal hardware platform for a given application The roadmap Reasons behind Xilinx
  • 7. The RC Dawn The Estrin Fix-Plus Machine, 1959 The Ramming Machine, 1977 Hartenstein’s XPuter , 1980 mid-1980s: the FPGA revolution/era The PAM Machine, SPLASH II, PRISM, Garp, DISC, DPGA
  • 8. Data Flow Machine (!FPGA) The Pact XPP Device The NEC-DRP Architecture The picoChip Reconfigurable Device PicoChip solution: Array of heterogeneous processors Communication flexibility between processors achieved through reconfigurable technology Array Processing Element Switch Matrix Inter-picoArray Interface
  • 9. The Academic Efforts The Reconfigurable Architecture Workstation (RAW) - MIT The Matrix Architecture - MIT The Reconfigurable Multimedia Array Coprocessor (REMARC) - Stanford MorphoSys - University of California, Irvine Chimaera – Northwestern PipeRench - CMU RaPiD - University of Washington Garp – UC Berkeley Bee2- UC Berkeley
  • 10. What are the drivers for this choice? Time: How long does it take to compute the answer? Area: How much silicon space is required to determined the answer? Costs: How much does it costs (performance, $)? Power: How much does it consume? Processor generally fixes computing area. Problem evaluated over time through instructions. FPGA can create flexible amount of computing area. Effectively, the configuration memory is the computing instruction.
  • 11. What’s next Basic Idea A bird’s eye view on the Reconfigurable Computing The roadmap The 90% – 10% Rule Programmable System on a Chip Multi-FPGA Reasons behind Xilinx
  • 12. The 90% – 10% Rule 90% of the execution is spent in 10% of the code Inner loops in algorithms Computational intense code 10% of the execution is spent in 90% of the code Exceptions User interaction The 10% computational intense code has to be executed as hardware on reconfigurable devices The 90% exception code is run as executable files on processors
  • 13. Programmable System on a Chip No longer just a bunch of reconfigurable elements DSPs, GPP, reconfigurable elements, etc. etc...
  • 15. What’s next Basic Idea A bird’s eye view on the Reconfigurable Computing The roadmap Reasons behind Xilinx
  • 16. Commercial FPGA Companies Lattice official webiste
  • 18. Reconfigurable SoC (taxonomy) and FPGA vendors
  • 19. Xilinx FPGA and Configuration Memory