MPHD RC Overview
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The document discusses reconfigurable computing and field programmable gate arrays (FPGAs). It provides an overview of FPGA configuration, partitioning and scheduling techniques for reconfigurable architectures. Specific projects involving reconfigurable computing frameworks and tools are also mentioned.
MPHD RC Overview
- 1. M etodologie di P rogettazine H ardware e S oftware Reconfigurable Computing - Overview -
- 2. Outline Reconfigurable Computing An overview FPGA Configuration bitstream Partitioning and scheduling MicroLAB MPHS Projects Earendil LimboWARE VIRGIL YaRA with Leon DRPC Scheduling for reconfigurable architecture Linux and reconfiguration DRESD Philosophy Team and meeting Web In the world Questions?
- 3. What’s next… Reconfigurable Computing An overview FPGA Configuration bitstream Partitioning and scheduling MicroLAB MPHS Projects Earendil LimboWARE VIRGIL YaRA with Leon DRPC Scheduling for reconfigurable architecture Linux and reconfiguration DRESD Philosophy Team and meeting Web In the world Questions?
- 4. Reconfiguration The process of physically altering the location or functionality of network or system elements. Automatic configuration describes the way sophisticated networks can readjust themselves in the event of a link or device failing, enabling the network to continue operation. Gerald Estrin, 1960
- 5. Reconfiguration in everyday life Soccer Hockey Football (Partial – Static) (Complete – Static) (Partial – Dynamic)
- 6. Where we are working Partial Total
- 7. Where we are working Partial Embedded f i x
- 8. Where we are working Single Device Distributed System
- 9. FPGA: overview CLB IOB Switch Box
- 10. FPGA: CLB VCC Switch Box SLICE TBUF Y X 67 66 75 74 SLICE_X66Y74
- 12. FPGA: Column-wise Structure 5 kinds of column: Clock, RAM, I-RAM, I/O, CLB Composed of a variable number of frames Double addressing: Major Address, Minor Address Major Address CLB Column
- 13. FPGA: Configuration Bitstreams Represents initial module location Cyclic Redundancy Check is also involved
- 15. Architecture Model Due to technology limitations (or specification limitations?) the smallest reconfigurable portion is a column 1 CLB wide --> |U|=68 reconfigurable units : 1 CLB … FPGA
- 16. Architecture Model Each reconfigurable unit contains Also, it can contain execution units requiring CLBs
- 17. Architecture Model Reconfiguration takes an affine time with respect to the size (in CLBs) of the reconfigured area: Or, in terms of clock cycles:
- 18. Specification We are given a directed acyclic graph (DAG) where O is the set of operations and P are the precedences. We also add a start node o S and a sink node o E so that all the other nodes are dominated by o S as post-dominated by o E .
- 19. Temporal partitioning Temporal partitioning No partial reconfiguration: all the chip is running, then it is stopped, totally reconfigured, and then runs again.
- 20. Temporal partitioning Can be highly suboptimal:
- 22. Loops Tasks being repeated several times are commonly exploited to hide reconfiguration overhead.
- 23. Questions