Lecture9-FlipFlops.pdf
- 1. Nov 2007 E1.2 Digital Electronics I 9.1 Lecture 9: Flip-flops Professor Peter Cheung Department of EEE, Imperial College London (Floyd 7.1-7.4) (Tocci 5.1-5.9) Nov 2007 E1.2 Digital Electronics I 9.2 Points Addressed in this Lecture • Properties of synchronous and asynchronous sequential circuits • Overview of flip-flops and latches Nov 2007 E1.2 Digital Electronics I 9.3 General digital system diagram Nov 2007 E1.2 Digital Electronics I 9.4 Properties of Sequential Circuits • So far we have seen Combinational Logic – the output(s) depends only on the current values of the input variables • Here we will look at Sequential Logic circuits – the output(s) can depend on present and also past values of the input and the output variables • Sequential circuits exist in one of a defined number of states at any one time – they move "sequentially" through a defined sequence of transitions from one state to the next – The output variables are used to describe the state of a sequential circuit either directly or by deriving state variables from them
- 2. Nov 2007 E1.2 Digital Electronics I 9.5 Synchronous and Asynchronous Sequential Logic • Synchronous – the timing of all state transitions is controlled by a common clock – changes in all variables occur simultaneously • Asynchronous – state transitions occur independently of any clock and normally dependent on the timing of transitions in the input variables – changes in more than one output do not necessarily occur simultaneously • Clock – A clock signal is a square wave of fixed frequency – Often, transitions will occur on one of the edges of clock pulses • i.e. the rising edge or the falling edge Nov 2007 E1.2 Digital Electronics I 9.6 Flip-Flops • Flip-flops are the fundamental element of sequential circuits – bistable – (gates are the fundamental element for combinational circuits) • Flip-flops are essentially 1-bit storage devices – outputs can be set to store either 0 or 1 depending on the inputs – even when the inputs are de-asserted, the outputs retain their prescribed value • Flip-flops have (normally) 2 complimentary outputs – and • Three main types of flip-flop – R-S J-K D-type Q Q Nov 2007 E1.2 Digital Electronics I 9.7 FF = latch = bistable circuit Flip-Flop Nov 2007 E1.2 Digital Electronics I 9.8 NAND Gate Latch A NAND latch has two possible resting states when SET = CLEAR = 1.
- 3. Nov 2007 E1.2 Digital Electronics I 9.9 NAND Gate Latch (cont.) Negative Pulse on SET input put the latch in a HIGH (SET) state Nov 2007 E1.2 Digital Electronics I 9.10 NAND Gate Latch (cont.) Negative Pulse on CLEAR input put the latch in a LOW (Clear or RESET) state Nov 2007 E1.2 Digital Electronics I 9.11 NAND Gate Latch (cont.) Truth table for the NAND Set-Clear (Set-Reset or SR) Latch Nov 2007 E1.2 Digital Electronics I 9.12 Alternative representation of SR Latch
- 4. Nov 2007 E1.2 Digital Electronics I 9.13 SR Latch to deglitch a switch Nov 2007 E1.2 Digital Electronics I 9.14 NOR gate Latch • Made of two cross-coupled NOR gates Nov 2007 E1.2 Digital Electronics I 9.15 Clock Signals and Clocked FFs • Digital systems can operate - Asynchronously: output can change state whenever inputs change - Synchronously: output only change state at clock transitions (edges) • Clock signal - Outputs change state at the transition (edge) of the input clock - Positive-going transitions (PGT) - Negative-going transitions (NGT) Nov 2007 E1.2 Digital Electronics I 9.16 Control inputs must be held stable for (a) a time tS prior to active clock transition and for (b) a time tH after the active block transition.
- 5. Nov 2007 E1.2 Digital Electronics I 9.17 Clocked S-C FF (a) Clocked S-C FF that responds only to the positive-going edge of a clock pulse; (b) truth table; (c) Typical waveforms. Nov 2007 E1.2 Digital Electronics I 9.18 Internal Circuitry of S-C FF Simplified version of the internal circuitry for an edge-triggered S-C FF Implementation of edge- detector circuits used in edge-triggered FFs: (a) PGT; (b) NGT. The duration of the CLK* pulses is typically 2-5 ns Nov 2007 E1.2 Digital Electronics I 9.19 Clocked J-K FF (a) Clocked J-K flip-flop that responds only to the positive edge of the clock; (b) waveforms. J=K=1 condition does not result in an ambiguous output Nov 2007 E1.2 Digital Electronics I 9.20 Internal circuitry of edge-triggered J-K flip-flop
- 6. Nov 2007 E1.2 Digital Electronics I 9.21 Clocked D Flip-Flop D FF that triggers only on positive-going transitions; (b) waveforms. Nov 2007 E1.2 Digital Electronics I 9.22 Clocked D Flip-Flop from J-K Flip-Flop Nov 2007 E1.2 Digital Electronics I 9.23 Parallel Data Transfer using D-FF Nov 2007 E1.2 Digital Electronics I 9.24 D Latch (transparent latch)
- 7. Nov 2007 E1.2 Digital Electronics I 9.25 Transparent Latch Timing Nov 2007 E1.2 Digital Electronics I 9.26 Asynchronous Inputs to FF The S, C, J, K, and D inputs is called synchronous inputs because their effects on the output are synchronized with the CLK input. Asynchronous inputs (override inputs) operate independently of the synchronous inputs and clock and can be used to set the FF to 1/0 states at any time. Nov 2007 E1.2 Digital Electronics I 9.27 Asynchronous Inputs cont.