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Enabling hardware acceleration in
OVS-DPDK using DPDK ‘Framework’
Sugesh Chandran
Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on
system configuration. Check with your system manufacturer or retailer or learn more at intel.com.
No computer system can be absolutely secure.
Tests document performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult
other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit
http://www.intel.com/benchmarks .
Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and
MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary.
You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when
combined with other products. For more complete information visit http://www.intel.com/benchmarks .
Intel's	compilers	may	or	may	not	optimize	to	the	same	degree	for	non-Intel	microprocessors	for	optimizations	that	are	not	unique to	Intel	microprocessors.	These	optimizations	
include	SSE2,	SSE3,	and	SSSE3	instruction	sets	and	other	optimizations.	Intel	does	not	guarantee	the	availability,	functionality,	or	effectiveness	of	any	optimization	on	
microprocessors	not	manufactured	by	Intel.	Microprocessor-dependent	 optimizations	in	this	product	are	intended	for	use	with	Intel	microprocessors.	Certain	optimizations	not	
specific	to	Intel	microarchitecture	are	reserved	for	Intel	microprocessors.	Please	refer	to	the	applicable	product	User	and	Reference	Guides	for	more	information	regarding	the	
specific	instruction	sets	covered	by	this	notice.	
Cost reduction scenarios described are intended as examples of how a given Intel-based product, in the specified circumstances and configurations, may affect future costs and
provide cost savings. Circumstances will vary. Intel does not guarantee any costs or cost reduction.
Intel does not control or audit third-party benchmark data or the web sites referenced in this document. You should visit the referenced web site and confirm whether referenced
data are accurate.
© 2017 Intel Corporation.
Intel, the Intel logo, and Intel Xeon are trademarks of Intel Corporation in the U.S. and/or other countries.
*Other names and brands may be claimed as property of others.
Notice & Disclaimers
Introduction
• Hardware acceleration in OVS-DPDK.
• Challenges of enabling hardware acceleration in OVS-DPDK
• DPDK ‘Framework’ , what is it?
• DPDK Framework components primer.
• Hardware acceleration enablement in OVS-DPDK using DPDK
‘Framework’
• Future work/Next steps.
Hardware acceleration in OVS-DPDK
• Partial acceleration:-Accelerate software datapath by
offloading a portion from the packet processing pipeline.
• Full acceleration:- Hardware can do end to end packet
processing pipeline. Packets are either handled in
Software or Hardware datapath.
Partial HW acceleration in OVS-DPDK
Datapath
User
NIC
OVSDB vswitchd
Match
Flow ActionsIngress Egress
Pre-
processing
Post-
processing
HW
Host
Virtio
Partial HW acceleration in OVS-DPDK
6
Datapath
User
NIC
OVSDB vswitchd
Match
Flow ActionsIngress Egress
Pre-
processing
Post-
processing
HW
Host
Virtio
Full HW acceleration in OVS-DPDK
Datapath
7
SW	DP
User
HW	DP
OVSDB vswitchd
Match
Flow ActionsIngress Egress
Match
Flow ActionsIngress Egress
Virtio/
VF
Host
HW
Challenges
• Feature Parity and Interoperability.
• Scalability.
• Optimized hardware resource allocation.
• Availability of HW acceleration support in OS, tools and other SW
components.
• Cost of Hardware acceleration setup Vs achievable performance
improvement with it.
• Live migration support.
Challenges
• Feature Parity and Interoperability.
• Scalability.
• Optimized hardware resource allocation.
• Availability of HW acceleration support in OS, tools and other SW
components.
• Cost of Hardware acceleration setup Vs achievable performance
improvement with it.
• Live migration support.
DPDK Framework
DPDK Framework
DPDK Framework
DPDK Framework
DPDK Framework
DPDK Framework
DPDK Framework
DPDK Framework
DPDK ‘Framework’ in OVS-DPDK
1. OVS-DPDK init with
hardware acceleration.
18
FPGA Driver
DPDK Framework
SWITCH
APIs
PORT
REP.
EXPT-
HANDLE
R
VDPA
RTE-
FLOW
QOS
TUNNEL
APIs
SW Datapath
FPGA
PHY
OVSDB vswitchd
Host
HW
DPDK ‘Framework’ in OVS-DPDK
1. OVS-DPDK init with
hardware acceleration.
• $ ovs-vsctl set Open_vSwitch . other_config:dpdk-
hw-offload-init=true
• $ ovs-vsctl set Open_vSwitch . other_config:dpdk-
hw-offload-ids="0000:5e:00.0“
FPGA Driver
DPDK Framework
SWITCH
APIs
PORT
REP.
EXPT-
HANDLE
R
VDPA
RTE-
FLOW
QOS
TUNNEL
APIs
SW Datapath
FPGA
PHY
OVSDB vswitchd
Host
HW
1
DPDK ‘Framework’ in OVS-DPDK
1. OVS-DPDK init with
hardware acceleration.
• $ ovs-vsctl set Open_vSwitch . other_config:dpdk-
hw-offload-init=true
• $ ovs-vsctl set Open_vSwitch . other_config:dpdk-
hw-offload-ids="0000:5e:00.0“
FPGA Driver
DPDK Framework
SWITCH
APIs
PORT
REP.
EXPT-
HANDLE
R
VDPA
RTE-
FLOW
QOS
TUNNEL
APIs
SW Datapath
FPGA
PHY
OVSDB vswitchd
Host
HW
1
2
DPDK ‘Framework’ in OVS-DPDK
1. OVS-DPDK init with
hardware acceleration.
• $ ovs-vsctl set Open_vSwitch . other_config:dpdk-
hw-offload-init=true
• $ ovs-vsctl set Open_vSwitch . other_config:dpdk-
hw-offload-ids="0000:5e:00.0“
FPGA Driver
DPDK Framework
SWITCH
APIs
PORT
REP.
EXPT-
HANDLE
R
VDPA
RTE-
FLOW
QOS
TUNNEL
APIs
SW Datapath
FPGA
PHY
OVSDB vswitchd
Host
HW
1
2
3
DPDK ‘Framework’ in OVS-DPDK
1. OVS-DPDK init with
hardware acceleration.
• $ ovs-vsctl set Open_vSwitch . other_config:dpdk-
hw-offload-init=true
• $ ovs-vsctl set Open_vSwitch . other_config:dpdk-
hw-offload-ids="0000:5e:00.0“
FPGA Driver
DPDK Framework
SWITCH
APIs
PORT
REP.
EXPT-
HANDLE
R
VDPA
RTE-
FLOW
QOS
TUNNEL
APIs
SW Datapath
FPGA
PHY
OVSDB vswitchd
Host
HW
1
2
3
4
DPDK ‘Framework’ in OVS-DPDK -contd
2. Add a hardware accelerated
port to OVS-DPDK.
• ovs-vsctl --timeout 10 add-port br0 port0 – set
Interface port0 type=dpdkhw options:device-
id=0,port-id=0
FPGA Driver
DPDK Framework
SWITCH
APIs
PORT
REP.
EXPT-
HANDLE
R
VDPA
RTE-
FLOW
QOS
TUNNEL
APIs
SW Datapath
FPGA
PHY
OVSDB vswitchd
Host
HW
1
DPDK ‘Framework’ in OVS-DPDK -contd
3. Report exception packet to
OVS-DPDK.
FPGA Driver
DPDK Framework
SWITCH
APIs
PORT
REP.
EXPT-
HANDLE
R
VDPA
RTE-
FLOW
QOS
TUNNEL
APIs
SW Datapath
FPGA
PHY
OVSDB vswitchd
Host
HW
DPDK ‘Framework’ in OVS-DPDK -contd
3. Report exception packet to
OVS-DPDK.
FPGA Driver
DPDK Framework
SWITCH
APIs
PORT
REP.
EXPT-
HANDLE
R
VDPA
RTE-
FLOW
QOS
TUNNEL
APIs
SW Datapath
FPGA
PHY
OVSDB vswitchd
Host
HW
DPDK ‘Framework’ in OVS-DPDK -contd
4. Install flow into SW
datapath.
FPGA Driver
DPDK Framework
SWITCH
APIs
PORT
REP.
EXPT-
HANDLE
R
VDPA
RTE-
FLOW
QOS
TUNNEL
APIs
SW Datapath
FPGA
PHY
OVSDB vswitchd
Host
HW
DPDK ‘Framework’ in OVS-DPDK -contd
4. Install flow into FPGA
hardware.
FPGA Driver
DPDK Framework
SWITCH
APIs
PORT
REP.
EXPT-
HANDLE
R
VDPA
RTE-
FLOW
QOS
TUNNEL
APIs
SW Datapath
FPGA
PHY
OVSDB vswitchd
Host
HW
Current Status
FPGA Driver
DPDK Framework
SWITCH
APIs
PORT REP.
EXPT-
HANDLER
VDPA RTE-FLOW
QOS
TUNNEL
APIs
SW Datapath
FPGA
PHY
OVSDB vswitchd
Host
HW
% completed
Next Steps
• Continue the publishing of DPDK ‘Framework’APIs and
implementation in the DPDK ML.
• Publish the RFC design to the OVS-DPDK mailing list to get
early feedback on the proposal and implementation.
• Publish OVS-DPDK implementation using DPDK ‘Framework’
to OVS mailing list.
Summary
§ The marriage of OVS-DPDK with hardware acceleration provides a compelling
solution to meet the needs of telco NFV workloads.
§ Abstracting away all the hardware features by handling them implicitly doesn’t
always yield an optimum solution .
§ OVS-DPDK hardware acceleration enablement should be flexible, extendable and
capable of using the hardware features in generic way.
§ DPDK ‘Framework’offers all the needed libraries for hardware acceleration
enablement in applications such as OVS-DPDK.
Questions?
sugesh.chandran@intel.com

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LF_OVS_17_Enabling hardware acceleration in OVS-DPDK using DPDK Framework.

  • 1. Enabling hardware acceleration in OVS-DPDK using DPDK ‘Framework’ Sugesh Chandran
  • 2. Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. Check with your system manufacturer or retailer or learn more at intel.com. No computer system can be absolutely secure. Tests document performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit http://www.intel.com/benchmarks . Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more complete information visit http://www.intel.com/benchmarks . Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Cost reduction scenarios described are intended as examples of how a given Intel-based product, in the specified circumstances and configurations, may affect future costs and provide cost savings. Circumstances will vary. Intel does not guarantee any costs or cost reduction. Intel does not control or audit third-party benchmark data or the web sites referenced in this document. You should visit the referenced web site and confirm whether referenced data are accurate. © 2017 Intel Corporation. Intel, the Intel logo, and Intel Xeon are trademarks of Intel Corporation in the U.S. and/or other countries. *Other names and brands may be claimed as property of others. Notice & Disclaimers
  • 3. Introduction • Hardware acceleration in OVS-DPDK. • Challenges of enabling hardware acceleration in OVS-DPDK • DPDK ‘Framework’ , what is it? • DPDK Framework components primer. • Hardware acceleration enablement in OVS-DPDK using DPDK ‘Framework’ • Future work/Next steps.
  • 4. Hardware acceleration in OVS-DPDK • Partial acceleration:-Accelerate software datapath by offloading a portion from the packet processing pipeline. • Full acceleration:- Hardware can do end to end packet processing pipeline. Packets are either handled in Software or Hardware datapath.
  • 5. Partial HW acceleration in OVS-DPDK Datapath User NIC OVSDB vswitchd Match Flow ActionsIngress Egress Pre- processing Post- processing HW Host Virtio
  • 6. Partial HW acceleration in OVS-DPDK 6 Datapath User NIC OVSDB vswitchd Match Flow ActionsIngress Egress Pre- processing Post- processing HW Host Virtio
  • 7. Full HW acceleration in OVS-DPDK Datapath 7 SW DP User HW DP OVSDB vswitchd Match Flow ActionsIngress Egress Match Flow ActionsIngress Egress Virtio/ VF Host HW
  • 8. Challenges • Feature Parity and Interoperability. • Scalability. • Optimized hardware resource allocation. • Availability of HW acceleration support in OS, tools and other SW components. • Cost of Hardware acceleration setup Vs achievable performance improvement with it. • Live migration support.
  • 9. Challenges • Feature Parity and Interoperability. • Scalability. • Optimized hardware resource allocation. • Availability of HW acceleration support in OS, tools and other SW components. • Cost of Hardware acceleration setup Vs achievable performance improvement with it. • Live migration support.
  • 18. DPDK ‘Framework’ in OVS-DPDK 1. OVS-DPDK init with hardware acceleration. 18 FPGA Driver DPDK Framework SWITCH APIs PORT REP. EXPT- HANDLE R VDPA RTE- FLOW QOS TUNNEL APIs SW Datapath FPGA PHY OVSDB vswitchd Host HW
  • 19. DPDK ‘Framework’ in OVS-DPDK 1. OVS-DPDK init with hardware acceleration. • $ ovs-vsctl set Open_vSwitch . other_config:dpdk- hw-offload-init=true • $ ovs-vsctl set Open_vSwitch . other_config:dpdk- hw-offload-ids="0000:5e:00.0“ FPGA Driver DPDK Framework SWITCH APIs PORT REP. EXPT- HANDLE R VDPA RTE- FLOW QOS TUNNEL APIs SW Datapath FPGA PHY OVSDB vswitchd Host HW 1
  • 20. DPDK ‘Framework’ in OVS-DPDK 1. OVS-DPDK init with hardware acceleration. • $ ovs-vsctl set Open_vSwitch . other_config:dpdk- hw-offload-init=true • $ ovs-vsctl set Open_vSwitch . other_config:dpdk- hw-offload-ids="0000:5e:00.0“ FPGA Driver DPDK Framework SWITCH APIs PORT REP. EXPT- HANDLE R VDPA RTE- FLOW QOS TUNNEL APIs SW Datapath FPGA PHY OVSDB vswitchd Host HW 1 2
  • 21. DPDK ‘Framework’ in OVS-DPDK 1. OVS-DPDK init with hardware acceleration. • $ ovs-vsctl set Open_vSwitch . other_config:dpdk- hw-offload-init=true • $ ovs-vsctl set Open_vSwitch . other_config:dpdk- hw-offload-ids="0000:5e:00.0“ FPGA Driver DPDK Framework SWITCH APIs PORT REP. EXPT- HANDLE R VDPA RTE- FLOW QOS TUNNEL APIs SW Datapath FPGA PHY OVSDB vswitchd Host HW 1 2 3
  • 22. DPDK ‘Framework’ in OVS-DPDK 1. OVS-DPDK init with hardware acceleration. • $ ovs-vsctl set Open_vSwitch . other_config:dpdk- hw-offload-init=true • $ ovs-vsctl set Open_vSwitch . other_config:dpdk- hw-offload-ids="0000:5e:00.0“ FPGA Driver DPDK Framework SWITCH APIs PORT REP. EXPT- HANDLE R VDPA RTE- FLOW QOS TUNNEL APIs SW Datapath FPGA PHY OVSDB vswitchd Host HW 1 2 3 4
  • 23. DPDK ‘Framework’ in OVS-DPDK -contd 2. Add a hardware accelerated port to OVS-DPDK. • ovs-vsctl --timeout 10 add-port br0 port0 – set Interface port0 type=dpdkhw options:device- id=0,port-id=0 FPGA Driver DPDK Framework SWITCH APIs PORT REP. EXPT- HANDLE R VDPA RTE- FLOW QOS TUNNEL APIs SW Datapath FPGA PHY OVSDB vswitchd Host HW 1
  • 24. DPDK ‘Framework’ in OVS-DPDK -contd 3. Report exception packet to OVS-DPDK. FPGA Driver DPDK Framework SWITCH APIs PORT REP. EXPT- HANDLE R VDPA RTE- FLOW QOS TUNNEL APIs SW Datapath FPGA PHY OVSDB vswitchd Host HW
  • 25. DPDK ‘Framework’ in OVS-DPDK -contd 3. Report exception packet to OVS-DPDK. FPGA Driver DPDK Framework SWITCH APIs PORT REP. EXPT- HANDLE R VDPA RTE- FLOW QOS TUNNEL APIs SW Datapath FPGA PHY OVSDB vswitchd Host HW
  • 26. DPDK ‘Framework’ in OVS-DPDK -contd 4. Install flow into SW datapath. FPGA Driver DPDK Framework SWITCH APIs PORT REP. EXPT- HANDLE R VDPA RTE- FLOW QOS TUNNEL APIs SW Datapath FPGA PHY OVSDB vswitchd Host HW
  • 27. DPDK ‘Framework’ in OVS-DPDK -contd 4. Install flow into FPGA hardware. FPGA Driver DPDK Framework SWITCH APIs PORT REP. EXPT- HANDLE R VDPA RTE- FLOW QOS TUNNEL APIs SW Datapath FPGA PHY OVSDB vswitchd Host HW
  • 28. Current Status FPGA Driver DPDK Framework SWITCH APIs PORT REP. EXPT- HANDLER VDPA RTE-FLOW QOS TUNNEL APIs SW Datapath FPGA PHY OVSDB vswitchd Host HW % completed
  • 29. Next Steps • Continue the publishing of DPDK ‘Framework’APIs and implementation in the DPDK ML. • Publish the RFC design to the OVS-DPDK mailing list to get early feedback on the proposal and implementation. • Publish OVS-DPDK implementation using DPDK ‘Framework’ to OVS mailing list.
  • 30. Summary § The marriage of OVS-DPDK with hardware acceleration provides a compelling solution to meet the needs of telco NFV workloads. § Abstracting away all the hardware features by handling them implicitly doesn’t always yield an optimum solution . § OVS-DPDK hardware acceleration enablement should be flexible, extendable and capable of using the hardware features in generic way. § DPDK ‘Framework’offers all the needed libraries for hardware acceleration enablement in applications such as OVS-DPDK.