Logic gates
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This document provides an overview of digital logic circuits. It begins with an introduction to logic gates and Boolean algebra. Common logic gates like AND, OR, NOT are described along with their truth tables. Boolean algebra is discussed as a way to analyze and synthesize digital logic circuits using Boolean variables and logic operations. Combinational logic and sequential logic are defined. Techniques for simplifying Boolean functions are covered, including Karnaugh maps and Boolean identities. Implementation of logic functions using sum-of-products form is also summarized.
![7Digital Logic Circuits
Computer Organization Computer Architectures Lab
BASIC IDENTITIES OF BOOLEAN ALGEBRA
[1] x + 0 = x
[3] x + 1 = 1
[5] x + x = x
[7] x + x’ = 1
[9] x + y = y + x
[11] x + (y + z) = (x + y) + z
[13] x(y + z) = xy +xz
[15] (x + y)’ = x’y’
[17] (x’)’ = x
[2] x • 0 = 0
[4] x • 1 = x
[6] x • x = x
[8] x • X’ = 0
[10] xy = yx
[12] x(yz) = (xy)z
[14] x + yz = (x + y)(x + z)
[16] (xy)’ = x’ + y’
[15] and [16] : De Morgan’s Theorem
Usefulness of this Table
- Simplification of the Boolean function
- Derivation of equivalent Boolean functions
to obtain logic diagrams utilizing different logic gates
-- Ordinarily ANDs, ORs, and Inverters
-- But a certain different form of Boolean function may be convenient
to obtain circuits with NANDs or NORs
→ Applications of De Morgans Theorem
x’y’ = (x + y)’ x’+ y’= (xy)’
I, AND → NOR I, OR → NAND
Boolean Algebra](https://image.slidesharecdn.com/logicgate-150811192835-lva1-app6891/85/Logic-gates-7-320.jpg)
![8Digital Logic Circuits
Computer Organization Computer Architectures Lab
EQUIVALENT CIRCUITS
F = ABC + ABC’ + A’C .......…… (1)
= AB(C + C’) + A’C [13] ..…. (2)
= AB • 1 + A’C [7]
= AB + A’C [4] ...…. (3)
(1)
(2)
(3)
Many different logic diagrams are possible for a given Function
Boolean Algebra
A
B
C
F
A
B
C F
F
A
B
C](https://image.slidesharecdn.com/logicgate-150811192835-lva1-app6891/85/Logic-gates-8-320.jpg)
Logic gates
- 1. 1Digital Logic Circuits Computer Organization Computer Architectures Lab Logic Gates Boolean Algebra Map Specification Combinational Circuits Flip-Flops Sequential Circuits Memory Components Integrated Circuits DIGITAL LOGIC CIRCUITS Introduction
- 2. 2Digital Logic Circuits Computer Organization Computer Architectures Lab Logic Gates LOGIC GATES Digital Computers - Imply that the computer deals with digital information, i.e., it deals with the information that is represented by binary digits - Why BINARY ? instead of Decimal or other number system ? * Consider electronic signal signal range 0 1 2 3 4 5 6 7 8 9 0 0 1 2 3 4 5 6 7 8 9 1 1 2 3 4 5 6 7 8 9 10 2 2 3 4 5 6 7 8 9 1011 3 3 4 5 6 7 8 9 101112 4 4 5 6 7 8 9 10111213 5 5 6 7 8 9 1011121314 6 6 7 8 9 101112131415 7 7 8 9 10111213141516 8 8 9 1011121314151617 9 9 101112131415161718 0 1 7 6 5 4 3 2 1 0 binary octal 0 1 0 1 1 10 0 1 * Consider the calculation cost - Add
- 3. 3Digital Logic Circuits Computer Organization Computer Architectures Lab BASIC LOGIC BLOCK - GATE - Types of Basic Logic Blocks - Combinational Logic Block Logic Blocks whose output logic value depends only on the input logic values - Sequential Logic Block Logic Blocks whose output logic value depends on the input values and the state (stored information) of the blocks Functions of Gates can be described by - Truth Table - Boolean Function - Karnaugh Map Logic Gates Gate. . . Binary Digital Input Signal Binary Digital Output Signal
- 4. 4Digital Logic Circuits Computer Organization Computer Architectures Lab COMBINATIONAL GATES A X X = (A + B)’ B Name Symbol Function Truth Table Logic Gates AND A X = A • B X or B X = AB 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 1 1 1 0 1 1 1 1 OR A X X = A + B B I A X X = A’ 0 1 1 0 Buffer A X X = A A X 0 0 1 1 NAND A X X = (AB)’ B 0 0 1 0 1 1 1 0 1 1 1 0 NOR 0 0 1 0 1 0 1 0 0 1 1 0 XOR Exclusive OR A X = A ⊕ B X or B X = A’B + AB’ 0 0 0 0 1 1 1 0 1 1 1 0 A X = (A ⊕ B)’ X or B X = A’B’+ AB 0 0 1 0 1 0 1 0 0 1 1 1 XNOR Exclusive NOR or Equivalence A B X A B X A X A B X A B X A B X A B X
- 5. 5Digital Logic Circuits Computer Organization Computer Architectures Lab BOOLEAN ALGEBRA Boolean Algebra * Algebra with Binary(Boolean) Variable and Logic Operations * Boolean Algebra is useful in Analysis and Synthesis of Digital Logic Circuits - Input and Output signals can be represented by Boolean Variables, and - Function of the Digital Logic Circuits can be represented by Logic Operations, i.e., Boolean Function(s) - From a Boolean function, a logic diagram can be constructed using AND, OR, and I Truth Table * The most elementary specification of the function of a Digital Logic Circuit is the Truth Table - Table that describes the Output Values for all the combinations of the Input Values, called MINTERMS - n input variables → 2n minterms Boolean Algebra
- 6. 6Digital Logic Circuits Computer Organization Computer Architectures Lab LOGIC CIRCUIT DESIGN x y z F 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 F = x + y’z Boolean Algebra x y z F Truth Table Boolean Function Logic Diagram
- 7. 7Digital Logic Circuits Computer Organization Computer Architectures Lab BASIC IDENTITIES OF BOOLEAN ALGEBRA [1] x + 0 = x [3] x + 1 = 1 [5] x + x = x [7] x + x’ = 1 [9] x + y = y + x [11] x + (y + z) = (x + y) + z [13] x(y + z) = xy +xz [15] (x + y)’ = x’y’ [17] (x’)’ = x [2] x • 0 = 0 [4] x • 1 = x [6] x • x = x [8] x • X’ = 0 [10] xy = yx [12] x(yz) = (xy)z [14] x + yz = (x + y)(x + z) [16] (xy)’ = x’ + y’ [15] and [16] : De Morgan’s Theorem Usefulness of this Table - Simplification of the Boolean function - Derivation of equivalent Boolean functions to obtain logic diagrams utilizing different logic gates -- Ordinarily ANDs, ORs, and Inverters -- But a certain different form of Boolean function may be convenient to obtain circuits with NANDs or NORs → Applications of De Morgans Theorem x’y’ = (x + y)’ x’+ y’= (xy)’ I, AND → NOR I, OR → NAND Boolean Algebra
- 8. 8Digital Logic Circuits Computer Organization Computer Architectures Lab EQUIVALENT CIRCUITS F = ABC + ABC’ + A’C .......…… (1) = AB(C + C’) + A’C [13] ..…. (2) = AB • 1 + A’C [7] = AB + A’C [4] ...…. (3) (1) (2) (3) Many different logic diagrams are possible for a given Function Boolean Algebra A B C F A B C F F A B C
- 9. 9Digital Logic Circuits Computer Organization Computer Architectures Lab COMPLEMENT OF FUNCTIONS A Boolean function of a digital logic circuit is represented by only using logical variables and AND, OR, and Invert operators. → Complement of a Boolean function - Replace all the variables and subexpressions in the parentheses appearing in the function expression with their respective complements A,B,...,Z,a,b,...,z ⇒ A’,B’,...,Z’,a’,b’,...,z’ (p + q) ⇒ (p + q)’ - Replace all the operators with their respective complementary operators AND ⇒ OR OR ⇒ AND - Basically, extensive applications of the De Morgan’s theorem (x1 + x2 + ... + xn )’ ⇒ x1’x2’... xn’ (x1x2 ... xn)' ⇒ x1' + x2' +...+ xn' Boolean Algebra
- 10. 10Digital Logic Circuits Computer Organization Computer Architectures Lab SIMPLIFICATION Truth Table Boolean Function Unique Many different expressions exist Simplification from Boolean function - Finding an equivalent expression that is least expensive to implement - For a simple function, it is possible to obtain a simple expression for low cost implementation - But, with complex functions, it is a very difficult task Karnaugh Map (K-map) is a simple procedure for simplifying Boolean expressions. Truth Table Boolean function Karnaugh Map Simplified Boolean Function Map Simplification
- 11. 11Digital Logic Circuits Computer Organization Computer Architectures Lab KARNAUGH MAP Karnaugh Map for an n-input digital logic circuit (n-variable sum-of-products form of Boolean Function, or Truth Table) is - Rectangle divided into 2n cells - Each cell is associated with a Minterm - An output(function) value for each input value associated with a mintern is written in the cell representing the minterm → 1-cell, 0-cell Each Minterm is identified by a decimal number whose binary representation is identical to the binary interpretation of the input values of the minterm. x F 0 1 1 0 x 0 1 0 1 x 0 1 0 1 Karnaugh Map value of F Identification of the cell x y F 0 0 0 0 1 1 1 0 1 1 1 1 y x 0 1 0 1 0 1 2 3 y x 0 1 0 1 0 1 1 0 F(x) = F(x,y) = ∑ (1,2) 1-cell ∑ (1) Map Simplification
- 12. 12Digital Logic Circuits Computer Organization Computer Architectures Lab KARNAUGH MAP 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 0 1 0 1 1 1 1 1 0 0 0 1 1 0 1 0 1 1 1 0 1 1 1 1 1 0 x yz 00 01 11 10 0 0 1 3 2 4 5 7 6 x yz 00 01 11 10 0 1 F(x,y,z) = ∑ (1,2,4) 1x y z uv wx 00 01 11 10 00 01 11 10 0 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 uv wx 00 01 11 10 00 01 11 0 0 0 1 10 1 1 1 0 0 1 1 0 0 0 0 1 F(u,v,w,x) = ∑ (1,3,6,8,9,11,14) u v w x Map Simplification x y z F u v w x F
- 13. 13Digital Logic Circuits Computer Organization Computer Architectures Lab MAP SIMPLIFICATION - 2 ADJACENT CELLS - Adjacent cells - binary identifications are different in one bit → minterms associated with the adjacent cells have one variable complemented each other Cells (1,0) and (1,1) are adjacent Minterms for (1,0) and (1,1) are x • y’ --> x=1, y=0 x • y --> x=1, y=1 F = xy’+ xy can be reduced to F = x From the map Rule: xy’ +xy = x(y+y’) = x x y 0 1 0 1 1 1 0 0 ∑ (2,3)F(x,y) = 2 adjacent cells xy’ and xy → merge them to a larger cell x = xy’+ xy = x Map Simplification
- 14. 14Digital Logic Circuits Computer Organization Computer Architectures Lab MAP SIMPLIFICATION - MORE THAN 2 CELLS - u’v’w’x’ + u’v’w’x + u’v’wx + u’v’wx’ = u’v’w’(x’+x) + u’v’w(x+x’) = u’v’w’ + u’v’w = u’v’(w’+w) = u’v’ uv wx 1 1 1 1 1 1 1 1 uv wx 1 1 1 1 1 1 1 1 u v w x u v w x u’v’ uw u’x’ v’x 1 1 1 1 vw’ u’v’w’x’+u’v’w’x+u’vw’x’+u’vw’x+uvw’x’+uvw’x+uv’w’x’+uv’w’x = u’v’w’(x’+x) + u’vw’(x’+x) + uvw’(x’+x) + uv’w’(x’+x) = u’(v’+v)w’ + u(v’+v)w’ = (u’+u)w’ = w’ Map Simplification u v w x uv wx 1 1 1 1 1 1 1 1 u v uv 1 1 1 1 1 1 1 1 1 1 1 1 x w’ u V’w
- 15. 15Digital Logic Circuits Computer Organization Computer Architectures Lab MAP SIMPLIFICATION (0,1), (0,2), (0,4), (0,8) Adjacent Cells of 1 Adjacent Cells of 0 (1,0), (1,3), (1,5), (1,9) ... ... Adjacent Cells of 15 (15,7), (15,11), (15,13), (15,14) uv wx 00 01 11 10 00 01 0 0 0 0 11 0 1 1 0 10 0 1 0 0 1 1 0 1 F(u,v,w,x) = ∑ (0,1,2,9,13,15) u v w x Merge (0,1) and (0,2) --> u’v’w’ + u’v’x’ Merge (1,9) --> v’w’x Merge (9,13) --> uw’x Merge (13,15) --> uvx F = u’v’w’ + u’v’x’ + v’w’x + uw’x + uvx But (9,13) is covered by (1,9) and (13,15) F = u’v’w’ + u’v’x’ + v’w’x + uvx Map Simplification 0 0 0 0 1 1 0 1 0 1 1 0 0 1 0 0
- 16. 16Digital Logic Circuits Computer Organization Computer Architectures Lab IMPLEMENTATION OF K-MAPS - Sum-of-Products Form - Logic function represented by a Karnaugh map can be implemented in the form of I-AND-OR A cell or a collection of the adjacent 1-cells can be realized by an AND gate, with some inversion of the input variables. x y z x’ y’ z’ x’ y z’ x y z’ 1 1 1 F(x,y,z) = ∑ (0,2,6) 1 1 1 x’ z’ y z’ Map Simplification ⇒ x’ y x y z’ x’ y’ z’ F x z y z F I AND OR z’ ⇒
- 17. 17Digital Logic Circuits Computer Organization Computer Architectures Lab IMPLEMENTATION OF K-MAPS - Product-of-Sums Form - Logic function represented by a Karnaugh map can be implemented in the form of I-OR-AND If we implement a Karnaugh map using 0-cells, the complement of F, i.e., F’, can be obtained. Thus, by complementing F’ using DeMorgan’s theorem F can be obtained F(x,y,z) = (0,2,6) x y zx y’ z F’ = xy’ + z F = (xy’)z’ = (x’ + y)z’ x y z F I OR AND Map Simplification 0 01 1 0 0 0 1
- 18. 18Digital Logic Circuits Computer Organization Computer Architectures Lab IMPLEMENTATION OF K-MAPS - Don’t-Care Conditions - In some logic circuits, the output responses for some input conditions are don’t care whether they are 1 or 0. In K-maps, don’t-care conditions are represented by d’s in the corresponding cells. Don’t-care conditions are useful in minimizing the logic functions using K-map. - Can be considered either 1 or 0 - Thus increases the chances of merging cells into the larger cells --> Reduce the number of variables in the product terms x y z 1 d d 1 d 1 x’ yz’ x y z F Map Simplification
- 19. 19Digital Logic Circuits Computer Organization Computer Architectures Lab COMBINATIONAL LOGIC CIRCUITS Half Adder 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 cn = xy + xcn-1+ ycn-1 = xy + (x ⊕ y)cn-1 s = x’y’cn-1+x’yc’n-1+xy’c’n-1+xycn-1 = x ⊕ y ⊕ cn-1 = (x ⊕ y) ⊕ cn-1 x y cn-1 x y cn-1 cn s Combinational Logic Circuits x y x y c = xy s = xy’ + x’y = x ⊕ y x y c s x y cn-1 S cn Full Adder 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 x y c s 0 1 0 0 0 0 1 1 x y cn-1 cn s 0 0 1 0 0 1 1 1 0 1 0 1 1 0 1 0
- 20. 20Digital Logic Circuits Computer Organization Computer Architectures Lab COMBINATIONAL LOGIC CIRCUITS Other Combinational Circuits Multiplexer Encoder Decoder Parity Checker Parity Generator etc Combinational Logic Circuits
- 21. 21Digital Logic Circuits Computer Organization Computer Architectures Lab MULTIPLEXER Combinational Logic Circuits 4-to-1 Multiplexer I0 I1 I2 I3 S0 S1 Y 0 0 I0 0 1 I1 1 0 I2 1 1 I3 Select Output S1 S0 Y
- 22. 22Digital Logic Circuits Computer Organization Computer Architectures Lab ENCODER/DECODER Octal-to-Binary Encoder Combinational Logic Circuits D1 D2 D3 D5 D6 D7 D4 A0 A1 A2 A0 A1 E D0 D1 D2 D3 0 0 0 0 1 1 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 0 1 1 1 1 1 0 1 d d 1 1 1 1 E A1 A0 D0 D1 D2 D3 2-to-4 Decoder
- 23. 23Digital Logic Circuits Computer Organization Computer Architectures Lab FLIP FLOPS Characteristics - 2 stable states - Memory capability - Operation is specified by a Characteristic Table 0-state 1-state In order to be used in the computer circuits, state of the flip flop should have input terminals and output terminals so that it can be set to a certain state, and its state can be read externally. R S Q Q’ S R Q(t+1) 0 0 Q(t) 0 1 0 1 0 1 1 1 indeterminate (forbidden) Flip Flops 1 0 0 1 0 1 1 0
- 24. 24Digital Logic Circuits Computer Organization Computer Architectures Lab CLOCKED FLIP FLOPS In a large digital system with many flip flops, operations of individual flip flops are required to be synchronized to a clock pulse. Otherwise, the operations of the system may be unpredictable. R S Q Q’ c (clock) Flip Flops S Q c R Q’ S Q c R Q’ operates when operates when clock is high clock is low Clock pulse allows the flip flop to change state only when there is a clock pulse appearing at the c terminal. We call above flip flop a Clocked RS Latch, and symbolically as
- 25. 25Digital Logic Circuits Computer Organization Computer Architectures Lab RS-LATCH WITH PRESET AND CLEAR INPUTS Flip Flops R S Q Q’ c (clock) P(preset) clr(clear) S Q c R Q’ S Q c R Q’ P clr P clr S Q c R Q’ P clr S Q c R Q’ P clr
- 26. 26Digital Logic Circuits Computer Organization Computer Architectures Lab D-LATCH D-Latch Forbidden input values are forced not to occur by using an inverter between the inputs Flip Flops Q Q’ D(data) E (enable) D Q E Q’ E Q’ D Q D Q(t+1) 0 0 1 1
- 27. 27Digital Logic Circuits Computer Organization Computer Architectures Lab EDGE-TRIGGERED FLIP FLOPS Characteristics - State transition occurs at the rising edge or falling edge of the clock pulse Latches Edge-triggered Flip Flops (positive) respond to the input only during these periods respond to the input only at this time Flip Flops
- 28. 28Digital Logic Circuits Computer Organization Computer Architectures Lab POSITIVE EDGE-TRIGGERED T-Flip Flop: JK-Flip Flop whose J and K inputs are tied together to make T input. Toggles whenever there is a pulse on T input. Flip Flops D-Flip Flop JK-Flip Flop S1 Q1 C1 R1 Q1' S2 Q2 C2 R2 Q2' D C Q Q' D C Q Q' SR1 SR2 SR1 active SR2 active D-FF S1 Q1 C1 R1 Q1' S2 Q2 C2 R2 Q2' SR1 SR2 J K C Q Q' J Q C K Q' SR1 active SR2 inactive SR2 inactive SR1 inactive
- 29. 29Digital Logic Circuits Computer Organization Computer Architectures Lab CLOCK PERIOD Clock period determines how fast the digital circuit operates. How can we determine the clock period ? Usually, digital circuits are sequential circuits which has some flip flops Combinational Logic Circuit FF FF Combinational logic Delay FF Setup Time FF Hold TimeFF Delay td ts,th clock period T = td + ts + th Flip Flops . . . ...FF C Combinational Logic Circuit FF FF . . .
- 30. 30Digital Logic Circuits Computer Organization Computer Architectures Lab DESIGN EXAMPLE Design Procedure: Specification ⇒ State Diagram ⇒ State Table ⇒ Excitation Table ⇒ Karnaugh Map ⇒ Circuit Diagram Example: 2-bit Counter -> 2 FF's current next state input state FF inputs A B x A B Ja Ka Jb Kb 0 0 0 0 0 0 d 0 d 0 0 1 0 1 0 d 1 d 0 1 0 0 1 0 d d 0 0 1 1 1 0 1 d d 1 1 0 0 1 0 d 0 0 d 1 0 1 1 1 d 0 1 d 1 1 0 1 1 d 0 d 0 1 1 1 0 0 d 1 d 1 A B x Ja 1 d d d d x A B Ka d d d d 1 Kb A B x1 1 d d d d Ja = Bx Ka = Bx Jb = x Kb = x clock 00 01 10 11 x=0 x=1 x=0 x=1 x=0 x=1 x=0 x=1 Sequential Circuits J Q C K Q' J Q C K Q' x AA B x1 d 1 d d d Jb B
- 31. 31Digital Logic Circuits Computer Organization Computer Architectures Lab SEQUENTIAL CIRCUITS - Registers Bidirectional Shift Register with Parallel Load Sequential Circuits D Q C D Q C D Q C D Q C A0 A1 A2 A3 Clock I0 I1 I2 I3 Shift Registers D Q C D Q C D Q C D Q C Serial Input Clock Serial Output D Q C D Q C D Q C D Q C A0 A1 A2 A3 4 x 1 MUX 4 x 1 MUX 4 x 1 MUX 4 x 1 MUX Clock S0S1 SeriaI Input I0 I1 I2 I3 Serial Input
- 32. 32Digital Logic Circuits Computer Organization Computer Architectures Lab SEQUENTIUAL CIRCUITS - Counters Sequential Circuits J K Q J K Q J K Q J K Q Clock Counter Enable A0 A1 A2 A3 Output Carry
- 33. 33Digital Logic Circuits Computer Organization Computer Architectures Lab MEMORY COMPONENTS Logical Organization Random Access Memory - Each word has a unique address - Access to a word requires the same time independent of the location of the word - Organization Memory Components words (byte, or n bytes) 2k Words (n bits/word) n data input lines n data output lines k address lines Read Write 0 N - 1
- 34. 34Digital Logic Circuits Computer Organization Computer Architectures Lab READ ONLY MEMORY(ROM) Characteristics - Perform read operation only, write operation is not possible - Information stored in a ROM is made permanent during production, and cannot be changed - Organization Information on the data output line depends only on the information on the address input lines. --> Combinational Logic Circuit X0=A’B’ + B’C X1=A’B’C + A’BC’ X2=BC + AB’C’ X3=A’BC’ + AB’ X4=AB X0=A’B’C’ + A’B’C + AB’C X1=A’B’C + A’BC’ X2=A’BC + AB’C’ + ABC X3=A’BC’ + AB’C’ + AB’C X4=ABC’ + ABC Canonical minterms 1 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 1 address Output ABC X0 X1 X2 X3 X4 000 001 010 011 100 101 110 111 Memory Components m x n ROM (m=2k ) k address input lines n data output lines
- 35. 35Digital Logic Circuits Computer Organization Computer Architectures Lab TYPES OF ROM ROM - Store information (function) during production - Mask is used in the production process - Unalterable - Low cost for large quantity production --> used in the final products PROM (Programmable ROM) - Store info electrically using PROM programmer at the user’s site - Unalterable - Higher cost than ROM -> used in the system development phase -> Can be used in small quantity system EPROM (Erasable PROM) - Store info electrically using PROM programmer at the user’s site - Stored info is erasable (alterable) using UV light (electrically in some devices) and rewriteable - Higher cost than PROM but reusable --> used in the system development phase. Not used in the system production due to eras ability Memory Components
- 36. 36Digital Logic Circuits Computer Organization Computer Architectures Lab INTEGRATED CIRCUITS Classification by the Circuit Density SSI - several (less than 10) independent gates MSI - 10 to 200 gates; Perform elementary digital functions; Decoder, adder, register, parity checker, etc LSI - 200 to few thousand gates; Digital subsystem Processor, memory, etc VLSI - Thousands of gates; Digital system Microprocessor, memory module Classification by Technology TTL - Transistor-Transistor Logic Bipolar transistors NAND ECL - Emitter-coupled Logic Bipolar transistor NOR MOS - Metal-Oxide Semiconductor Unipolar transistor High density CMOS - Complementary MOS Low power consumption Memory Components