Magnitude comparator
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1) A magnitude comparator is a circuit that compares two numbers and determines their relative magnitudes, indicating whether the first number is greater than, equal to, or less than the second number. 2) For an n-bit magnitude comparator, there are 2n inputs and 22n entries in the truth table. A 2-bit comparator has 4 inputs and 16 truth table entries, while a 3-bit comparator has 6 inputs and 64 truth table entries. 3) The document describes designing a 2-bit magnitude comparator using Karnaugh mapping to minimize the logic functions and drawing the logic diagram based on the minimized functions.
![Magnitude
Comparator
Indigital system,comparison oftwonumbers isanarithmetic
operationthatdeterminesifonenumber
isgreaterthan,equalto,orlessthantheothernumber[1].Socomparatorisusedforthispu
rpose.Magnitude
Comparatorisacombinationalcircuitthatcomparestwonumbers,AandB,anddetermi
nestheirrelative
magnitudes.Theoutcomeofcomparisonisspecifiedbythreebinaryvariablesthatindic
atewhether
A>B,A=B,orA<B.
Figure1.BlockDiagramofn-BitMagnitudeComparator
Thecircuit,forcomparingtwon-
Bitnumbers,has2ninputs&22nentriesinthetruthtable,for2-Bit numbers,4-
inputs&16-rowsinthetruthtable,similarly,for3-Bitnumbers6-inputs&64-
rowsinthetruth table[2].
Thelogicstyleusedinlogicgatesbasicallyinfluencesthespeed,size,powerdissi
pation,andthe
wiringcomplexityofacircuit.Circuitsizedependsonthenumberoftransistorsandtheir
sizesandonthe
wiringcomplexity.Thewiringcomplexityisdeterminedbythenumberofconnections
andtheirlengths.All thesecharacteristics](https://image.slidesharecdn.com/magnitudecomparator-140426125609-phpapp02/85/Magnitude-comparator-1-320.jpg)
![mayvaryconsiderablyfromonelogicstyletoanother andthus properchoice
oflogicstyle isveryimportantforcircuitperformance.
2-BITMAGNITUDECOMPARATOR
2-BitMagnitudeComparatorComparestwo
numberseachhavingtwobits(A1,A0&B1,B0).
Forthisarrangementtruthtable[5] has4 inputs&16entries asin Table1.
Table1.TruthTableof2-BitMagnitudeComparator
INPUT OUTPUT
A1 A0 B1 B0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1](https://image.slidesharecdn.com/magnitudecomparator-140426125609-phpapp02/85/Magnitude-comparator-2-320.jpg)
Magnitude comparator
- 1. Magnitude Comparator Indigital system,comparison oftwonumbers isanarithmetic operationthatdeterminesifonenumber isgreaterthan,equalto,orlessthantheothernumber[1].Socomparatorisusedforthispu rpose.Magnitude Comparatorisacombinationalcircuitthatcomparestwonumbers,AandB,anddetermi nestheirrelative magnitudes.Theoutcomeofcomparisonisspecifiedbythreebinaryvariablesthatindic atewhether A>B,A=B,orA<B. Figure1.BlockDiagramofn-BitMagnitudeComparator Thecircuit,forcomparingtwon- Bitnumbers,has2ninputs&22nentriesinthetruthtable,for2-Bit numbers,4- inputs&16-rowsinthetruthtable,similarly,for3-Bitnumbers6-inputs&64- rowsinthetruth table[2]. Thelogicstyleusedinlogicgatesbasicallyinfluencesthespeed,size,powerdissi pation,andthe wiringcomplexityofacircuit.Circuitsizedependsonthenumberoftransistorsandtheir sizesandonthe wiringcomplexity.Thewiringcomplexityisdeterminedbythenumberofconnections andtheirlengths.All thesecharacteristics
- 2. mayvaryconsiderablyfromonelogicstyletoanother andthus properchoice oflogicstyle isveryimportantforcircuitperformance. 2-BITMAGNITUDECOMPARATOR 2-BitMagnitudeComparatorComparestwo numberseachhavingtwobits(A1,A0&B1,B0). Forthisarrangementtruthtable[5] has4 inputs&16entries asin Table1. Table1.TruthTableof2-BitMagnitudeComparator INPUT OUTPUT A1 A0 B1 B0 A>B A=B A<B 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 1 1 0 0 1
- 3. 1 1 0 0 1 0 0 1 1 0 1 1 0 0 1 1 1 0 1 0 0 1 1 1 1 0 1 0 Karnaugh Mapping K-MapisusedtominimizeBooleanfunctionobtainedfromtruthtable. ForA>B A>B:=A1B1‟ +A0B0‟ A1‟ B1‟ +A0B0‟ A1B1 = A1B1‟ +A0B0‟ (A1‟ B1‟ +A1B1) = A1B1‟ +A0B0‟ X1 ForA=B
- 4. A=B:=A1‟ A0‟ B1‟ B0‟ +A1‟ A0B1‟ B0+A1A0‟ B1B0‟ +A1A0B1B0 = (A1‟ B1‟ +A1B1)(A0‟ B0‟ +A0B0) = X1X0 ForA<B A<B:=A1‟ B1+A0‟ B0A1‟ B1‟ +A0‟ B0A1B1 = A1‟ B1+A0‟ B0(A1‟ B1‟ +A1B1) = A1‟ B1+A0‟ B0X1 Logic Diagram