Memory Management Strategies - IV.pdf
- 1. Amrita School of Engineering, Bangalore Ms. Harika Pudugosula Lecturer Department of Electronics & Communication Engineering
- 2. • Background • Swapping • Contiguous Memory Allocation • Segmentation • Paging • Structure of the Page Table 2
- 3. Structure of the Page Table 3 • Memory structures for paging can get huge using straight-forward methods • Consider a 32-bit logical address space as on modern computers • Page size of 4 KB (212) • Page table would have 1 million entries (232 / 212)= 2^20 • If each entry is 4 bytes -> 4 MB of physical address space / memory for page table alone • That amount of memory used to cost a lot • Don’t want to allocate that contiguously in main memory • Hierarchical Paging • Hashed Page Tables • Inverted Page Tables
- 4. Hierarchical Paging 4 • Assumming that each entry consists of 4 bytes, each process may need up to 4 MB of physical address space for the page table alone • Clearly, we would not want to allocate the page table contiguously in main memory • One simple solution to this problem is to divide the page table into smaller pieces • One way is to use a two-level paging algorithm, in which the page table itself is also paged
- 5. Hierarchical Paging 5 Figure. A two-level page-table scheme • A logical address (on 32-bit machine with 1K page size) is divided into: • a page number consisting of 22 bits • a page offset consisting of 10 bits • Since the page table is paged, the page number is further divided into: • a 12-bit page number • a 10-bit page offset • Thus, a logical address is as follows: where p1 is an index into the outer page table, and p2 is the displacement within the page of the inner page table
- 6. Hierarchical Paging 6 Figure. Address translation for a two-level 32-bit paging architecture • Address translation works from the outer page table inward, this scheme is also known as a forward-mapped page table
- 7. Hierarchical Paging 7 • Even two-level paging scheme not sufficient • If page size is 4 KB (212) • Then page table has 252 entries • If two level scheme, inner page tables could be 210 4-byte entries • Address would look like • Outer page table has 242 entries or 244 bytes • One solution is to add a 2nd outer page table • But in the following example the 2nd outer page table is still 234 bytes in size • And possibly 4 memory access to get to one physical memory location
- 8. Hashed Page Tables 8 • Common in address spaces -> 32 bits • The virtual page number is hashed into a page table • This page table contains a chain of elements hashing to the same location • Each element contains (1) the virtual page number (2) the value of the mapped page frame (3) a pointer to the next element • Virtual page numbers are compared in this chain searching for a match • If a match is found, the corresponding physical frame is extracted • Variation for 64-bit addresses is clustered page tables • Similar to hashed but each entry refers to several pages (such as 16) rather than 1 • Especially useful for sparse address spaces (where memory references are non- contiguous and scattered)
- 9. Hashed Page Tables 9 Figure. Hashed Page table
- 10. Inverted Page Tables 10 • Rather than each process having a page table and keeping track of all possible logical pages, track all physical pages • One entry for each real page of memory • Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page • Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs • Use hash table to limit the search to one — or at most a few — page-table entries • TLB can accelerate access • But how to implement shared memory? • One mapping of a virtual address to the shared physical address
- 11. Inverted Page Tables 11 Figure. Inverted Page table
- 12. • Consider modern, 64-bit operating system example with tightly integrated • Goals are efficiency, low overhead • Based on hashing, but more complex • Two hash tables • One kernel and one for all user processes • Each maps memory addresses from virtual to physical memory • Each entry represents a contiguous area of mapped virtual memory, • More efficient than having a separate hash-table entry for each page • Each entry has base address and span (indicating the number of pages the entry represents) Oracle SPARC Solaris 12
- 13. • TLB holds translation table entries (TTEs) for fast hardware lookups • A cache of TTEs reside in a translation storage buffer (TSB) • Includes an entry per recently accessed page • Virtual address reference causes TLB search • If miss, hardware walks the in-memory TSB looking for the TTE corresponding to the address • If match found, the CPU copies the TSB entry into the TLB and translation completes • If no match found, kernel interrupted to search the hash table • The kernel then creates a TTE from the appropriate hash table and stores it in the TSB, Interrupt handler returns control to the MMU, which completes the address translation. 13 Oracle SPARC Solaris
- 14. 14 References 1. Silberscatnz and Galvin, “Operating System Concepts,” Ninth Edition, John Wiley and Sons, 2012.
- 15. 15 Thank you