Paging and Segmentation
- 1. 11/30/17 1 Paging and Segmentation By SATHISHKUMAR G (sathishsak111@gmail.com)
- 2. 11/30/17 2 Paging • Goals » make allocation and swapping easier • Make all chunks of memory the same size » call each chunk a “PAGE” » example page sizes are 512 bytes, 1K, 4K, 8K, etc » pages have been getting bigger with time » we’ll discuss reasons why pages should be of a certain size as the week progresses. Page # Offset Virtual Address Page Table Base Register + + => physical address Page Table Each entry in the page table is a “Page Table Entry”
- 3. 11/30/17 3 An Example • Pages are 1024 bytes long » this says that bottom 10 bits of the VA is the offset • PTBR contains 2000 » this says that the first page table entry for this process is at physical memory location 2000 • Virtual address is 2256 » this says “page 2, offset 256” • Physical memory location 2004 contains 8192 » this says that each PTE is 4 bytes (1 word) » and that the second page of this process’s address space can be found at memory location 8192. • So, we add 256 to 8192 and we get the real data!
- 4. 11/30/17 4 What does a PTE contain? M-bit V-bit Protection bits Page Frame Number • The Modify bit says whether or not the page has been written. » it is updated each time a WRITE to the page occurs. • The Reference bit says whether or not the page has been touched » it is updated each time a READ or a WRITE occurs • The V bit says whether or not the PTE can be used » it is checked each time the virtual address is used • The Protection bits say what operations are allowed on this page » READ, WRITE, EXECUTE • The Page Frame Number says where in memory is the page R-bit 1 1 1 1-2 about 20
- 5. 11/30/17 5 Evaluating Paging • Easy to allocate memory » memory comes from a free list of fixed size chunks. » to find a new page, get anything off the free list. » external fragmentation not a problem • easy to swap out pieces of a program » since all pieces are the same size. » use valid bit to detect references to swapped pages » pages are a nice multiple of the disk block size. • Can still have internal fragmentation • Table space can become a serious problem » especially bad with small pages – eg, w/a 32bit address space and 1k size pages, that’s 222 pages or that many ptes which is a lot! • Memory reference overhead can be high » 2 refs for every one
- 6. 11/30/17 6 Segmentation and Paging at the Same Time • Provide for two levels of mapping • Use segments to contain logically related things » code, data, stack » can vary in size but are generally large. • Use pages to describe components of the segments » makes segments easy to manage and can swap memory between segments. » need to allocate page table entries only for those pieces of the segments that have themselves been allocated. • Segments that are shared can be represented with shared page tables for the segments themselves.
- 7. 11/30/17 7 An Early Example -- IBM System 370 24 bit virtual address 4 bits 8 bits 12 bits Segment Table Page Table + simple bit operation Real Memory
- 8. 11/30/17 8 Lookups • Each memory reference can be 3 » assuming no fault • Can exploit locality to improve lookup strategy » a process is likely to use only a few pages at a time • Use Translation Lookaside buffer to exploit locality » a TLB is a fast associative memory that keeps track of recent translations. • The hardware searches the TLB on a memory reference • On a TLB miss, either a hardware or software exception can occur » older machines reloaded the TLB in hardware » newer RISC machines tend to use software loaded TLBs – can have any structure you want for the page table – fast handler computes and goes. Eg, the MIPS.
- 9. 11/30/17 9 Hard versus soft page faults • Hard page faults are those page faults that require issuing a read from secondary storage. • Soft page faults are those page faults where the page is already in main memory however the TLB and/or the PTE has marked the page as invalid. » Soft faults are used when Hardware support is not available to handle TLB misses » Soft faults can also be used in implement certain page replacement algorithms. More to come.
- 10. 11/30/17 10 A TLB • A small fully associative cache • Each entry contains a tag and a value. » tags are virtual page numbers » values are physical page table entries. • Problems include » keeping the TLB consistent with the PTE in main memory – valid and ref bits, for example » keeping TLBs consistent on an MP. » quickly loading the TLB on a miss. • Hit rates are important. Tag Value 0xfff1000 0xfff1000 0xa10100 0xbbbb00 0x1111aa11 ? 0x12341111
- 11. 11/30/17 11 Selecting a page size • Small pages give you lots of flexibility but at a high cost. • Big pages are easy to manage, but not very flexible. • Issues include » TLB coverage – product of page size and # entries » internal fragmentation – likely to use less of a big page » # page faults and prefetch effect – small pages will force you to fault often » match to I/O bandwidth – want one miss to bring in a lot of data since it will take a long time.
- 12. 11/30/17 12 State of maintained by MM • MM usually maintains a list of physical pages according to the following attributes (various implementations use slightly different lists) » Zeroed pages » Free pages » Standby pages » Modified pages » Modified No Write pages » Bad pages • MM’s goal is to use these pages on these lists to supply memory for both soft and hard page faults • MM can have a modified page writer process that goes around and flushes out dirty pages.