microprocessor and interfaces ppt of pin diagram
- 1. PIN DIAGRAM & ARCHITECTURE OF 8085 MICROPROCESSOR (UNIT-1) (SUB: Microprocessor and Interfaces) PREPARED BY: ER. MOHIT MISHRA ASSOCIATE PROFESSOR COMPUTER SCIENCE DEPARTMENT
- 2. Introduction to 8085 It has three advanced versions: ◦ 8085 AH ◦ 8085 AH2 ◦ 8085 AH1 These advanced versions are designed using HMOS technology.
- 3. Introduction to 8085 The advanced versions consume 20% less power supply. The clock frequencies of 8085 are: ◦ 8085 A 3 MHz ◦ 8085 AH 3 MHz ◦ 8085 AH2 5 MHz ◦ 8085 AH1 6 MHz
- 4. Pin Diagram of 8085
- 5. VSS and VCC Pin 20 (Input) and Pin 40 (Input) • +5V power supply is connected to VCC. • Ground signal is connected to VSS.
- 6. X1 & X2 Pin 1 and Pin 2 (Input) These are also called Crystal Input Pins. 8085 can generate clock signals internally. To generate clock signals internally, 8085 requires external inputs from X1 and X2.
- 7. Address and Data Pins • Address Bus: • The address bus is used to send address to memory. • It selects one of the many locations in memory. • Its size is 16-bit.
- 8. Address and Data Pins • Data Bus: • It is used to transfer data between microprocessor and memory. • Data bus is of 8-bit.
- 9. AD0 – AD7 Pin 19-12 (Bidirectional) • These pins serve the dual purpose of transmitting lower order address and data byte. • During 1st clock cycle, these pins act as lower half of address. • In remaining clock cycles, these pins act as data bus. • The separation of lower order address and data is done by address latch.
- 10. A8 – A15 Pin 21-28 (Unidirectional) • These pins carry the higher order of address bus. • The address is sent from microprocessor to memory. • These 8 pins are switched to high impedance state during HOLD and RESET mode.
- 11. ALE Pin 30 (Output) • It is used to enable Address Latch. • It indicates whether bus functions as address bus or data bus. • If ALE = 1 then – Bus functions as address bus. • If ALE = 0 then – Bus functions as data bus.
- 12. S0 and S1 Pin 29 (Output) and Pin 33 (Output) • S0 and S1 are called Status Pins. • They tell the current operation which is in progress in 8085. S0 S1 Operation 0 0 Halt 0 1 Write 1 0 Read 1 1 Opcode Fetch
- 13. IO/M Pin 34 (Output) • This pin tells whether I/O or memory operation is being performed. • If IO/M = 1 then – I/O operation is being performed. • If IO/M = 0 then – Memory operation is being performed.
- 14. IO/M Pin 34 (Output) • The operation being performed is indicated by S0 and S1. • If S0 = 0 and S1 = 1 then – It indicates WRITE operation. • If IO/M = 0 then – It indicates Memory operation. • Combining these two we get Memory Write Operation.
- 15. Table Showing IO/M, S0, S1 and Corresponding Operations Operations IO/M S0 S1 Opcode Fetch 0 1 1 Memory Read 0 1 0 Memory Write 0 0 1 I/O Read 1 1 0 I/O Write 1 0 1 Interrupt Ack. 1 1 1 Halt High Impedance 0 0
- 16. RD Pin 32 (Output) • RD stands for Read. • It is an active low signal. • It is a control signal used for Read operation either from memory or from Input device. • A low signal indicates that data on the data bus must be placed either from selected memory location or from input device.
- 17. WR Pin 31 (Output) • WR stands for Write. • It is also active low signal. • It is a control signal used for Write operation either into memory or into output device. • A low signal indicates that data on the data bus must be written into selected memory location or into output device.
- 18. RESET IN and RESET OUT Pin 36 (Input) and Pin 3 (Output) RESET IN: ◦ It is used to reset the microprocessor. ◦ . It is active low signal ◦ When the signal on this pin is low for at least 3 clocking cycles, it forces the microprocessor to reset itself.
- 19. RESET IN and RESET OUT Pin 36 (Input) and Pin 3 (Output) Resetting the microprocessor means: ◦ Clearing the PC and IR. ◦ Disabling all interrupts (except TRAP). ◦ Disabling the SOD pin. ◦ All the buses (data, address, control) are tri-stated. ◦ Gives HIGH output to RESET OUT pin.
- 20. RESET IN and RESET OUT Pin 36 (Input) and Pin 3 (Output) RESET OUT: ◦ It is used to reset the peripheral devices and other ICs on the circuit. ◦ It is an output signal. ◦ It is an active high signal. ◦ The output on this pin goes high whenever RESET IN is given low signal. ◦ The output remains high as long as RESET IN is kept low.
- 21. SID and SOD Pin 4 (Input) and Pin 5 (Output) SID (Serial Input Data): o It takes 1 bit input from serial port of 8085. o Stores the bit at the 8th position (MSB) of the Accumulator. o RIM (Read Interrupt Mask) instruction is used to transfer the bit.
- 22. SID and SOD Pin 4 (Input) and Pin 5 (Output) SOD (Serial Output Data): o It takes 1 bit from Accumulator to serial port of 8085. o Takes the bit from the 8th position (MSB) of the Accumulator. o SIM (Set Interrupt Mask) instruction is used to transfer the bit.
- 23. Interrupt Pins Interrupt: • It means interrupting the normal execution of the microprocessor. • When microprocessor receives interrupt signal, it discontinues whatever it was executing. • It starts executing new program indicated by the interrupt signal. • Interrupt signals are generated by external peripheral devices. • After execution of the new program, microprocessor goes back to the previous program.
- 24. Five Hardware Interrupts in 8085 TRAP RST 7.5 RST 6.5 RST 5.5 INTR
- 25. Classification of Interrupts • Maskable and Non-Maskable • Vectored and Non-Vectored • Edge Triggered and Level Triggered • Priority Based Interrupts
- 26. TRAP Pin 6 (Input) It is an non-maskable interrupt. It has the highest priority. It cannot be disabled. It is both edge and level triggered. It means TRAP signal must go from low to high. And must remain high for a certain period of time. TRAP is usually used for power failure and emergency shutoff.
- 27. RST 7.5 Pin 7 (Input) It is a maskable interrupt. It has the second highest priority. It is positive edge triggered only. The internal flip-flop is triggered by the rising edge. The flip-flop remains high until it is cleared by RESET IN.
- 28. RST 6.5 Pin 8 (Input) It is a maskable interrupt. It has the third highest priority. It is level triggered only. The pin has to be held high for a specific period of time. RST 6.5 can be enabled by EI instruction. It can be disabled by DI instruction.
- 29. RST 5.5 Pin 9 (Input) It is a maskable interrupt. It has the fourth highest priority. It is also level triggered. The pin has to be held high for a specific period of time. This interrupt is very similar to RST 6.5.
- 30. INTR Pin 10 (Input) It is a maskable interrupt. It has the lowest priority. It is also level triggered. It is a general purpose interrupt. By general purpose we mean that it can be used to vector microprocessor to any specific subroutine having any address.
- 31. INTA Pin 11 (Output) It stands for interrupt acknowledge. It is an out going signal. It is an active low signal. Low output on this pin indicates that microprocessor has acknowledged the INTR request.
- 32. READY Pin 35 (Input) • This pin is used to synchronize slower peripheral devices with fast microprocessor. • A low value causes the microprocessor to enter into wait state. • The microprocessor remains in wait state until the input at this pin goes high.
- 33. HOLD Pin 38 (Input) • HOLD pin is used to request the microprocessor for DMA transfer. • A high signal on this pin is a request to microprocessor to relinquish the hold on buses. • This request is sent by DMA controller. • Intel 8257 and Intel 8237 are two DMA controllers.
- 34. HLDA Pin 39 (Output) • HLDA stands for Hold Acknowledge. • The microprocessor uses this pin to acknowledge the receipt of HOLD signal. • When HLDA signal goes high, address bus, data bus, RD, WR, IO/M pins are tri-stated. • This means they are cut-off from external environment.
- 35. HLDA Pin 39 (Output) • The control of these buses goes to DMA Controller. • Control remains at DMA Controller until HOLD is held high. • When HOLD goes low, HLDA also goes low and the microprocessor takes control of the buses.
- 37. Demultiplexing AD7-AD0 – From the above description, it becomes obvious that the AD7– AD0 lines are serving a dual purpose and that they need to be demultiplexed to get all the information. – The high order bits of the address remain on the bus for three clock periods. However, the low order bits remain for only one clock period and they would be lost if they are not saved externally. Also, notice that the low order bits of the address disappear when they are needed most. – To make sure we have the entire address for the full three clock cycles, we will use an external latch to save the value of AD7– AD0 when it is carrying the address bits. We use the ALE signal to enable this latch.
- 38. Demultiplexing AD7-AD0 – Given that ALE operates as a pulse during T1, we will be able to latch the address. Then when ALE goes low, the address is saved and the AD7– AD0 lines can be used for their purpose as the bi-directional data lines. A15-A8 Latch AD7-AD0 D7- D0 A7- A0 8085 ALE