3. Functional units of a computer
• Computer consists of five functionally independent main parts:
⮚ Input unit
⮚ Memory unit
⮚ Arithmetic and logic unit
⮚ Output unit
⮚ Control unit
4. Input unit
● The input unit accepts information from human operators,
from electromechanical devices such as keyboards, or
from other computers through communication lines.
● Whenever a key is pressed, the corresponding letter or
number is automatically translated into its
corresponding binary code (a format the computer
understands) and sent to the computer’s memory or
processor.
● Examples of input devices: keyboard, mouse, joystick,
microphone, scanner & web cam.
6. Memory unit
• The memory unit in a computer is used to store
programs and data.
• There are two main types of storage in a
computer:
• Primary storage (like RAM)
• Secondary storage (like hard drives or
USBs)
• A program must be kept in memory (primary
storage) while it is running.
7. • Memory is made up of many tiny electronic
cells where each cell can hold one bit of
information.
• These bits are grouped together into words
of fixed size (like blocks).
• A computer word can be 16 to 64 bits long,
depending on the system.
• Each word in memory has a special number
called an address.
• These addresses help the computer find and
use the information stored in memory
quickly.
8. Primary storage (Fast Memory)
• RAM(Random Access memory):- can quickly
access any location of the memory in a short
and fixed amount of time by giving its address.
• The time required to access one word is
called memory access time.
10. Memory hierarchy
• The computer’s memory is arranged in levels, called a memory
hierarchy, with 3 or 4 types of RAM. These levels differ in speed, size,
and cost.
• Cache Memory:
This is a small and very fast memory made using SRAM (Static RAM).
It is placed very close to the processor so that data can be accessed
quickly.
• Main Memory (Primary Memory):
This is larger but slower than cache memory and is made using
DRAM
(Dynamic RAM).
It stores programs and data currently being used.
• Primary storage is more expensive than secondary storage (like hard
disks), especially the faster types like cache.
11. • Memory hierarchy
• Secondary(Auxillary) memory
• It is used when large amounts of data and many programs
have to be stored.
• Examples are hard disk drives, solid state drives, magnetic disks,
magnetic tapes and optical disks.
13. Arithmetic and Logic unit (ALU)
• Most computer operations are executed inside a part of the
processor called the ALU (Arithmetic and Logic Unit).
• The ALU performs:
• Arithmetic operations like: addition, subtraction, multiplication,
and division.
• Logical operations like: AND, OR, NOT, and EX-OR.
• Steps in performing operations:
• Get the data (operands) from memory.
• Bring the data into the processor’s fast storage area called
registers.
• The ALU performs the operation using this data.
• The result is then stored back in memory or kept in the
processor.
• ALU works faster than other parts connected to the computer.
14. Output unit
•
Output units are used to send the processed
results to the user.
•
These devices display information that is stored
or created inside the computer.
•
Common output devices include printers and
visual display units (monitors).
16. Control unit
• Control unit is used to coordinate the operations
of the input, output, memory, ALU in some way.
• It creates timing signals which tell these parts
when to do their tasks.
• These timing signals make sure that data moves
in the right order and at the right time.
• A group of control lines (wires) carries these
signals, helping all the parts stay synchronized
and work smoothly together.
17. Operations of a computer
• A computer accepts information as programs and
data through an input unit and stores it in memory.
• The information stored in memory is
brought
Arithmetic Logic Unit (ALU) under the control
to the
of
the
program, where it is processed.
• After processing, the information is sent out of
the computer through an output unit.
• All the actions inside the computer are managed
and controlled by the control unit.
18. BASIC OPERATIONAL CONCEPTS
• A Typical instruction
Add LOCA, R0
• This instruction adds two values:
• One from memory location LOCA
• One from register R0 (inside the processor)
• The sum is stored back in R0
• Step by step
•The instruction is fetched from memory.
•The value at LOCA (memory) is read.
•That value is added to the current value in R0.
•The new result replaces the old value in R0.
•The value in LOCA stays the same.
20. Fundamental Concepts
• Central processing unit (CPU): The CPU is the main working
part of a computer. It gets instructions, understands
them, and performs tasks like calculations and making
decisions.
• A typical computing task is done by following a set of steps.
These steps are written as machine instructions, which
together form a program.
• Each instruction is carried out by breaking it into smaller
basic steps and performing them one by one.
21. Fundamental Concepts
• The processor fetches one instruction at a time and carries out the
operation specified.
• Instructions are fetched from successive memory locations until a
branch or a jump instruction is encountered.
• Processor uses the Program Counter (PC) to keep track of the
memory address of the next instruction to be fetched and executed.
The PC always holds the address of the next instruction in the
instruction sequence.
• Instruction Register (IR) holds the instruction that is currently being
processed
23. Executing an Instruction
• Fetch the instruction from the memory location pointed to by the PC.
The is instruction is loaded into the IR (fetch phase).
written as IR ← [[PC]]
• Since the memory is byte-addressable and each instruction is 4 bytes
long, after fetching an instruction, the Program Counter (PC) is
incremented by 4 to point to the next instruction in memory (fetch
phase).
PC ← [PC] + 4
• Perform the operation specified by the instruction in the IR
(execution phase).
24. Processor Organization
•The Address Bus carries the address from
the processor to memory — telling which
memory location to access.
•The Data Bus transfers data both ways —
reading data from memory or writing data to
memory.
•The Control Bus sends control signals like
Read, Write, and Clock to coordinate the
data transfer.
25. Internal organization of the processor
• ALU and all the registers are interconnected via single
common bus which is internal to the processor.
• ALU:- used to perform arithmetic and logic
operations.
• Registers inside the processor for temporary storage
• Various digital circuits for executing different micro
operations (gates, MUX, decoders, counters for shifting
bits, selecting inputs, counting, and controlling data
flow.).
26. • Driver circuits for transmitting signals to external
units (Amplify and prepare signals for external
transmission).
• Receiver circuits for incoming signals from external
units. (Ensure signals are correctly received and
interpreted.)
• Program Counter (PC):
• Keeps track of execution of a program
• It stores the memory address of the next instruction
to be fetched and executed.
27. • The data and address lines of the external memory bus are
connected to the internal processor bus via
• MDR(Memory Data Register) and MAR (Memory Address
Register).
• MAR: Holds the address of the memory location to be
accessed. Input of MAR is connected to Internal bus and
output to external memory bus.
• MDR: Holds the data to be written into or read out from the
memory. It has 2 inputs and 2 Outputs. Data can be loaded
into MDR either from memory bus or from internal
processor bus.
28. • The control lines of the memory bus are connected to the instruction
decoder and control logic block. This unit is responsible for issuing
the signals that control the operation of all the units inside the
processor and for interacting with the memory bus.
29. • Registers:
• The processor registers R0 to R(n-1) vary considerably from one processor to
another.
• Some are general-purpose — used by the programmer to store values.
• Some are special-purpose — like index registers or stack pointers used for
specific tasks.
• Registers Y, Z &TEMP are used for temporary storage by processor during the
execution of some instruction. These registers are never used for
storing data for future reference.
30. • Multiplexer:
• It chooses between two inputs:
• the output of the register Y or
• a constant value 4
• The selected value goes to input A of the ALU.
• The constant 4 is often used by the processor to
increment the value of the Program Counter (PC) to move
to the next instruction.
31. •During the execution of an instruction, data are transferred
from one register to another through ALU to perform some
arithmetic and logic operation.
•Instruction Decoder and Control Logic Unit
•This unit carries out the action of the instruction that is
loaded in the Instruction Register (IR).
•The decoder creates control signals to:
• Select the registers involved
• direct the movement of data
32. An instruction can be executed by performing one or more of
the following operations in some sequence
• Transfer a word of data (typically 8, 16, 32, or 64 bits)
from one processor register to another.
• Performing an Arithmetic or Logic Operation and store the
result in a processor register.
• Fetch the contents of a specified memory location and
load them into a processor register.
• Store a word of data from a processor register into a
specified memory location.
34. • The input and output of register Ri are connected to the bus
via switches controlled by control signals Riin and Riout .
• These 2 control signals are used to place the contents of that
register on the bus or to load the data on the bus into the
register.
• When Riin is set to 1 – data available on bus are loaded into
Ri.
• When Riout is set to 1 – the contents of register are
placed on the bus.
• When Riout is set to 0 – the bus can be used for
transferring data from other registers .
35. Data transfer between two registers:
• Eg: Transfer the contents of R1 to R4.
• Enable the output of register R1
• Set R1out=1.
• This places the contents of R1 onto the processor bus.
• Enable the input of register R4
• Set R4in=1.
• This loads the data from the processor bus into register R4.
• All operations and data transfer within the processor takes place
within time periods defined by processor clock.
• Data transfer may use both rising & falling edges of the clock.
36. 2. Performing an Arithmetic or Logic Operation
• The ALU is a combinational circuit that has no internal
storage.
• ALU gets the two operands from MUX and bus. The
result is temporarily stored in register Z.
• What is the sequence of operations/control sequence to add
the contents of register R1 to those of R2 and store the
result in R3? (Add R1, R2, R3)
1. R1out, Yin
2. R2out, SelectY, Add, Zin
3. Zout, R3in
37. • Step 1: Output of the register R1 and input of the
register Y are enabled, causing the contents of
be transferred to Y.
R1 to
• Step 2: The multiplexer’s select signal is set to select Y
causing the multiplexer to gate the contents of register Y
to input A of the ALU. The contents of register R2 are
gated onto the bus and hence to input B. The Add line is
set to 1, causing the output of the ALU to be the sum of
the two inputs A and B.
• Step 3: The contents of Z are transferred to the
destination register R3.
38. 3. Fetching a Word from Memory
• To fetch a word of data from memory, the processor
performs the following steps:
• Specify the Memory Address
• The processor identifies the address of the memory location
where the data is stored.
• Load the Address into MAR
• This address is transferred to the Memory Address Register
(MAR).
• The output of MAR is connected to the address lines of the
memory bus, allowing the memory to know which location
to access.
39. • Initiate a Read Operation
• The processor uses the control lines of the memory bus to
request a Read operation.
• Receive and Store the Data in MDR
• Once the memory responds, the requested data is
transferred from memory to the Memory Data Register
(MDR).
• Make Data Available to Processor
• The MDR now holds the fetched data, which can be
transferred to other registers in the processor.
40. Fetching a Word from Memory
Figure 7.4. Connection and control signals for register MDR.
• Address into MAR; issue Read operation; data into MDR.
or
41. • MDRin and MDRout control connection to the internal bus.
• MDRinE and MDRoutE control connection to the external
bus.
• MDRinE = 1, input is selected from memory bus
• Processor completes one internal data transfer in one clock
cycle
• The processor waits until it receives an indication that the
requested operation has been completed (Memory-Function-
Completed, MFC)
42. Fetching a Word from Memory- Example
of a read operation
• Mov (R1), R2 , the action needed to execute this
instruction are;
⮚ MAR ← [R1]
⮚ Start a Read operation on the memory bus
⮚ Wait for the MFC response from the memory
⮚ Load MDR from the memory bus
⮚ R2 ← [MDR]
44. 4. Storing a word in memory
• Address is loaded into MAR
• Data to be written loaded into MDR.
• Write command is issued.
• Example: Mov R2,(R1)
• R1out,MARin
• R2out,MDRin,Write
• MDRoutE, WMFC
45. Execution of a Complete Instruction
• Add (R3), R1
• Fetch the instruction
• Fetch the first operand (the contents of the
memory location pointed to by R3)
• Perform the addition
• Load the result into R1
55. Execution of Branch Instructions
• A branch instruction replaces the contents of PC with the
branch target address, which is usually obtained by
adding an offset X given in the branch instruction to the
updated value of PC.
• The offset X is usually the difference between the
branch target address and the address immediately
following the branch instruction.
• Control sequence for UnConditional branch
56. •Branching instructions refer to the act of switching
execution to a different instruction sequence as a
result of executing a branch instruction.
58. •Processing starts with the fetch phase and ends when
the instruction is loaded into the IR in step 3.
•The offset value is extracted from the IR by the
instruction decoding circuit.
•Since the value of the updated PC is already available
in register Y, the offset X is gated onto the bus in step
4 & an addition operation is performed.
•The result, which is the branch target address is
loaded into the PC in step 5.
59. • For eg: if the branch instruction is at
location 2000 & if the branch target address
is 2050.
•The value of X = 2050 – 2004 = 46
60. Multiple-Bus Organization
• Multiple internal paths that allow
several transfers to take place in
parallel.
• Two registers can be read at the
same time, and their data can be
placed on buses A and B.
• At the same time, data on bus C
can be written into a different
register.
• Incrementer unit
• Fig: 3 bus organization of the
datapath
61. • General purpose registers are combined into a single block
called register file.
-3 ports,2 output ports –access two different registers
simultaneously and have their contents on buses A
and B
-Third port allows data on bus C to be loaded into a
third register during same clock cycle
• Inputs to the ALU and outputs from the ALU
-Bus A & B are used to transfer the source operands
to A & B inputs of the ALU.
- ALU operation is performed.
-The result is transferred to the destination over
the bus C.
62. • ALU may simply pass one of its 2 input operands
unmodified to bus C.
• The ALU control signals for such an operation
R=A or R=B.
• Incrementer unit is used to increment the PC by
4.
• Using the incrementer eliminates the need to add the constant
value 4 to the PC using the main ALU.
• The source for the constant 4 at the ALU input multiplexer can
be used to increment other address such as load
multiple & store multiple
64. • Step 1:The contents of PC are passed through the ALU
using R=B control signal & loaded into MAR to start a
memory read operation. At the same time PC is
incremented by 4.
• Step 2:The processor waits for MFC
• Step 3: Loads the data ,received into MDR, then transfers
them to IR.
• Step 4: The execution phase of the instruction
requires only one control step to complete.
65. • Based on how the processor accesses memory, there
are two types of architectures.
• Von Neumann
• Harvard
66. Von-Neumann Architecture
• Single memory for both instructions (program) and data.
• Uses one bus for both data transfer and instruction fetch.
• The CPU fetches instructions and data one after another (sequentially).
• It has simple hardware.
The main drawback:
• CPU is unable to access program memory and data memory
simultaneously by sharing a common bus. This case is called the
"bottleneck" that affects system performance.
67. Harvard Architecture
• Separate memory for instructions and data.
• Uses two buses — one for instructions and one for data.
• The CPU can fetch instructions and read/write data at the same time.
• The main advantage:
• Computers designed with the Harvard architecture have separate memory
areas for program instructions and data using internal data buses,
allowing simultaneous access to both instructions and data.
• Faster execution & more efficient.
![Executing an Instruction
• Fetch the instruction from the memory location pointed to by the PC.
The is instruction is loaded into the IR (fetch phase).
written as IR ← [[PC]]
• Since the memory is byte-addressable and each instruction is 4 bytes
long, after fetching an instruction, the Program Counter (PC) is
incremented by 4 to point to the next instruction in memory (fetch
phase).
PC ← [PC] + 4
• Perform the operation specified by the instruction in the IR
(execution phase).](https://image.slidesharecdn.com/module1-part1-250819153943-5e2dd4a3/85/module-1-Part-1-pptxdddddddddddddddddddddddddddddddddddd-23-320.jpg)
![Fetching a Word from Memory- Example
of a read operation
• Mov (R1), R2 , the action needed to execute this
instruction are;
⮚ MAR ← [R1]
⮚ Start a Read operation on the memory bus
⮚ Wait for the MFC response from the memory
⮚ Load MDR from the memory bus
⮚ R2 ← [MDR]](https://image.slidesharecdn.com/module1-part1-250819153943-5e2dd4a3/85/module-1-Part-1-pptxdddddddddddddddddddddddddddddddddddd-42-320.jpg)
