NoC simulators presentation
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The document provides an overview of simulators used for modeling and evaluating Networks-on-Chip (NoCs). It discusses what a simulator is and the benefits of using simulators. It also describes different types of simulators, such as cycle-accurate versus event-driven simulators. Finally, it summarizes several popular NoC simulators, including BookSim, NNSE, Noxim, Wormsim, HNoCS, SICOSYS, TOPAZ, and NIRGAM. The document provides high-level information on the capabilities and features of these simulators in 1-3 sentences for each.
NoC simulators presentation
- 1. 12/28/2013 1
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- 3. What is a Simulator? • Simulation: – It is the discipline of designing a model of an actual or theoretical physical system, executing the model on a digital computer, and analyzing the execution output. – The simulation allows researchers to explore the design space as well as to evaluate the performance and efficiency of novel microarchitecture features. • Simulator: – It is a piece of software to model devices (or components) to predict outputs and performance metrics on a given input. (Wikipedia) • Simulators can be classified into many different categories: – Scope: micro-architecture vs. full-system simulators. – Detail: functional vs. timing (or performance) simulators. – Input (sometimes called Workload): trace-driven (or event-driven) vs. cycle accurate simulators. 3
- 4. Benefits of Simulators • Simulators are very useful for the following purposes: – Evaluating different hardware designs without building costly physical hardware systems. – Enabling the opportunities to access non-existing components or systems – Obtaining detailed performance metrics: A single execution of simulators can often generate A large set of performance data. – Debugging: debugging on real hardware typically require re-booting and rerunning the code (or the design) to reproduce the problems. In contrast, some simulators have A fully controlled environment and allow software developers to run code backward once an error is detected. 4
- 5. Cycle-accurate vs. Event-driven simulation • Cycle-accurate simulation: – Simulates a microarchitecture on a cycle-by-cycle basis. • Often used where time precisions are very important. – Incremented in fixed steps. • After each increment we check to see which events happened at the current time point. – Cycle and bit accurate simulation is necessary when the actual router’s RTL description needs to be evaluated and verified. • Event-driven simulation: – Systems consisting of several tens or hundreds of modules, Cycle-accurate simulation leads to excessive simulation times. – It is a modelling paradigm in which flow of control within the system is driven by events rather than sequence. • events aren't guaranteed to occur at regular intervals. – This approach uses a list of events that occur at various time, and handles them in order of increasing time. 5
- 6. Why NoC Simulation? • Design decisions on NoC architectures are typically made on the basis of simulation before resorting to emulation or implementation since it is cheap and flexible. • To make a right decision on the network architecture, a simulation tool should enable: 1. Faster exploration of the architectural design space; 2. Assessment of design quality regarding performance, cost, power and reliability etc.; 3. Extensive evaluation of various regular traffic patterns and application-oriented traffic. 6
- 7. Main characteristics of NoC • Topology: Arrangement of the Network Elements. • Switching: The way the data is transferred from the input port to the output port. • Routing: Determine message path. • Flow Control: Determine allocation of the channels. • Buffering: The way the packets are stored when they cannot be processed. • Arbitration: Plans the use of channels and buffers. 7
- 8. Dealing with Simulators Study of NoCs Characteristics and Parameters Study of NoCs Simulators Parameters and Capabilities Choose a NoC Simulator Implementation 8
- 9. NoC Evaluation methods • NoC Evaluation is an important step to classify the proposed architecture among the others*. • To compare and contrast different NoC architectures, a standard set of performance metrics can be used: – Latency – Throughput – Area – Power * “A Survey of Network-On-Chip Tools” Ahmed Ben Achballah, et al. National Institute of Applied Sciences and Technology, Dept. of Electrical Engineering. Centre Urbain Nord, BP 676- 1080 Tunis Cedex, Tunisia. 9
- 10. NoC Simulators Comparison Simulato r Framewor k Availability Parallelis m Topologies Open Source Heterogeneous Support Synchronous / Asynchronous SICOSYS C++ + - Limited + - Synchronous Noxim SystemC + - Mesh + - Synchronous BookSim C++ + - Many + - Synchronous NNSE SystemC + - Mesh/Torus + - Synchronous Nirgam SystemC + - All + - Synchronous gpNoCsim Java + - All + - Both Parm NoC OMNeT++ - + All - - Synchronous HNOCS OMNeT++ + + All + + Both 10
- 11. BookSim • cycle-accurate simulator. • Supports a wide range of topologies such as mesh, torus and flattened butterfly networks • Provides diverse routing algorithms and includes numerous options for customizing the network's router microarchitecture. • Most of the simulator's components are designed to be modular so tasks such as adding a new routing algorithm, topology, or router microarchitecture should not require a complete redesign of the code. • Implemented in C++. • the configuration file contains basic information about the topology, routing algorithm, flow control, and traffic. • Packet size defaults to a single flit. 11
- 13. Royal Institute of Technology NNSE Nostrum Network-on-Chip Simulation Environment • Enables to analyze the performance impact of NoC configuration parameters – Configure a network with respect to topology, flow control and routing algorithm etc.; – Configure various regular and application specific traffic patterns; – Evaluate the network with the traffic patterns in terms of latency and throughput. • The tool realizes only a limited set of configurations, which are as follows: – Topology: 2D mesh and 2D torus. – Flow control: Wormhole routing and deflection routing. • • For wormhole routing, one can choose virtual channel (VC) parameters like the number and depth of VCs. For deflection routing (hot potato), one can specify a deflection policy. Deflection routing is a routing strategy for networks based on packet switching which can reduce the need of buffering packets 13
- 14. NNSE Nostrum Network-on-Chip Simulation Environment Network configuration tree Network evaluation flow 14
- 15. Wormsim Simulator • • • • • • a cycle accurate simulator for Networks-on-Chip It can be used to simulate a wide range of NoC architectures (e.g. NoCs with different topologies and different routing algorithms, etc.), using user controllable performance parameters (e.g. channel buffer size, routing engine delay, crossbar arbitration delay, etc.). It has built-in traffic generator allow users to simulate the system under several popular traffic patterns, such as uniform traffic pattern, hot spot traffic pattern, transpose traffic pattern, etc. It provides an efficient way to allow user specify arbitrary traffic condition for the NoC under simulation. – user has the control over the packet generating rate at individual IP node, the size of the packet and its distribution, etc. Worm_sim uses a simple command line interface to setup different parameters for systems under simulation. Worm_sim was developed and tested mainly in GNU/Linux. 15
- 16. University of Catania (Italy) Noxim • It is developed using SystemC. • It has a command line interface for defining several parameters of a NoC. • The user can customize the network size, buffer size, packet size distribution, routing algorithm, selection strategy, packet injection rate, traffic time distribution, traffic pattern, hot-spot traffic distribution. • It allows NoC evaluation in terms of throughput, delay and power consumption. – This information is delivered to the user both in terms of average and percommunication results. • The user is allowed to collect different evaluation metrics including the total number of received packets/flits, global average throughput, max/min global delay, total energy consumption, percommunications delay/throughput/energy etc. 16
- 17. Heterogeneous NoCs (HNoCS) • • • • HNOCS is an open-source implementation of a NoC simulation framework using OMNeT++. As an event driven simulation engine OMNeT++ provides C++ APIs to a reach set of services that can be used to model, configure, describe the topology, collect simulation data and perform analysis. Support heterogeneous NoCs with variable link capacities and number of VCs per each unidirectional port. Supports parallelism and arbitrary topologies. 17
- 18. SICOSYS Universidad de Cantabria, Spain • • • • It is a general-purpose interconnection network simulator for multiprocessor systems that allows the modeling a wide variety of message routers in a precise way. Results are very close to those obtained by using hardware simulators but at lower computational cost. implementation is in C++ language. The portability is very high and practically it can be executed in any UNIX platform with a C++ standard compiler. 18
- 19. TOPAZ • TOPAZ is a general-purpose interconnection network simulator that allows the modeling a wide variety of message routers with different tradeoffs between speed and precision. • TOPAZ comes from SICOSYS simulator, which was originally conceived to obtain results are very close to those obtained by using HDL description of networks components by hardware simulators but at lower computational cost. • implementation is in C++ language. • The simulator has support for parallel execution using standard POSIX threads. • used in any UNIX platform with a C++ standard compiler. 19
- 20. TOPAZ COMPONENTS SUPPLIED WITH TOPAZ 20
- 21. NIRGAM* • • • It is a systemC based discrete event, cycle accurate simulator. It provides substantial support to experiment with NoC design in terms of routing algorithms and applications on various topologies. Current Capabilities: 1. 2. 3. 4. Topology: 2-D Mesh,2-D Torus Switching Mechanism: Wormhole Routing Algorithms: Deterministic XY, Adaptive Odd-Even(OE), and Source Routing Applications: Source (sender), Sink (reciever) and Traffic Generator: Constant Bit Rate, Bursty, and Trace-based 5. Plug-in support for applications and routers • Configurable NoC parameters: – Topology size (m x n), Clock frequency, Buffer depth, Flit size, and Virtual channels *NIRGAM is a collaborative research between Electronic Systems Design group, School of Electronics and Computer Science, University of Southampton UK and Department of Computer Science and Engineering, Malaviya National Institute of Technology, Jaipur India. 21
- 22. NIRGAM • • It generates gnuplot graphs and matlab script that can be run to generate graphs in matlab. It records the following performance metrics for each simulation: – – – • Average latency per packet (in clock cycles) for each channel Average latency per flit (in clock cycles) for each channel Average throughput (in Gbps) for each channel Adding New Router 22
- 23. General Purpose Simulator for Network-on-Chip • • • • an open-source, component based network simulation environment that is developed entirely in Java. gpNoCsim provides the designers with the flexibility of incorporating different network and traffic configurations. Network configuration has been considered as the conglomeration of topologies, switching techniques, and routing algorithms. Reconfigurable topologies allow comparison between different architectures: Mesh, Torus, Butterfly Fat Tree. 23
- 24. Booksim Vs. TOPAZ Booksim • • • • • • • • Developed by Concurrent VLSI Architecture group at Stanford University. Supports broad range of network architectures Cycle-accurate implementation is in C++. very simple to use. Most of research use it for evaluation. Functionality continuously extended. Very good Support by its designer. TOPAZ • • • • • • Actively in use by galerna project from the University of Cantabria, Spain. The infrastructure inherited from SICOSYS. Cycle-accurate obtain results are very close to HDL description of networks components by hardware simulators at lower computational cost. Very well Documented. Support 2-D and 3-D NoCs.
- 25. Booksim Vs. TOPAZ Booksim TOPAZ • Booksim Based reseach: • – DART’s simulation results uses Booksim as a reference. – Project “Floorplanning and performance evaluation for ondie communication fabrics". • • • http://networkonchip.wordpress.com Most routers support to work with 3D NoCs. Support multi-threaded to be executed on multi-core systems. Can be easily employed to extract power and energy. Integrates with General Executiondriven Multiprocessor Simulator GEMS/GEM5.
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Editor's Notes
- #2: What is the interconnection network?Bus Crossbar Hypercube Tree Torus Multistage Fully Connected Mesh RingHybrid
- #4: Simulation is a technique that allows a cheap and fast way of studying, tuning and testing real systems without actually building them.Functional simulators emphasize achieving the same function as the modeled components, while timing simulators strive to accurately reproduce the performance/timing features of the targets in addition to their functionalities.
- #5: The simulation phase covers the necessity of obtaining the NoC communication infrastructure suited for a particular application.It increases the efficiency by selecting the appropriate parameters, allowing a better latency and throughput.
- #6: software that simulates a microprocessor executing a program on a cycle-by-cycle basis is known as cycle-accurate simulatorSimulation of the NoC architecture with cycle and bit accuracy is prohibitively time consuming.
- #8: By using NoC in the communication infrastructure we achieved the division of computation and communication.
- #9: Once the specifications are closed, the next step is the design process.
- #10: Latency is defined as the time (in clock cycles) that elapses from between the occurrence of a message header injection into the network at the source node and the occurrence of a tail flit reception at the destination node.Throughput is defined as the average number of bits received per cycle at all resources in the network.areapower
- #19: SICOSYS is a general-purpose interconnection network simulator for multiprocesor systems that allows the modeling a wide variety of message routers in a precise way. Results are very close to those obtained by using hardware simulators but at lower computational cost. In order to make the tool easily comprehensible, extensible and reusable, the design of the tool is object-oriented and its implementation is in C++ language.The implementation of the simulator is based on technology intimately related to the OO design: the design patterns. In particular, approximately 110 classes, distributed in about 50,000 lines of code have been necessary. The portability is very high and practically it can be executed in any UNIX platform with a C++ standard compiler.SICOSYS was developed having in mind modularity, versatility and connectivity with other systems. In fact, now it is possible to run SICOSYS with full systems simulators like RSIM and SIMOS. The models used are intended to resemble the hardware implementations in some aspects while keeping the complexity as low as possible.In this way, the simulator mimics the hardware structure of the routers instead of just implementing their functionality. In order to benchmark the routers and networks against other alternatives and to enable the system to keep up with new developments while presenting a homogeneous user interface, the design of the simulator has payed much attention at its extensibility and the simplicity of the user interface. Thus, SICOSYS has a collection of hardware-inspired components like multiplexers, buffers or crossbars. Routers can be built by connecting components to each other, as they are in the hardware description. Then the routers are connected in a certain network fashion. All this is defined in SGML which can be thought of as a superset of HTML. This allows SICOSYS to handle hierarchical descriptions of routers easily while keeping high readability of the configuration files .
- #20: http://code.google.com/p/tpzsimul/
- #25: conceived to obtain results are very close to those obtained by using HDL description of networks components by hardware simulators but at lower computational cost.
- #26: The gem5 simulation infrastructure is the merger of the best aspects of the M5 [4] and GEMS [9] simulators. M5 provides a highly configurable simulation framework, multiple ISAs, and diverse CPU models. GEMS complements these features with a detailed and exible memory system, including support for multiple cache coherence protocols and interconnect models.