OIF 2015 FOE Architecture Presentation
1 like2,710 views
The document provides an overview of the OIF's efforts in developing the Common Electrical Interface (CEI) for 56G applications, highlighting the evolution of electrical interconnect standards and addressing key architectural considerations. It discusses various application spaces for 56G technology, including chip-to-chip and module interfaces, and emphasizes ongoing trends such as increased integration and power efficiency demands. The paper notes that the development of high-performance systems at 56Gb/s signaling rates is supported by advancements in semiconductor technology and integrated optics.
![Insertion Loss
DAUGHTER CARD
• Board Material = Megtron6 VLP
• Trace length = 5”
• Trace geometry = Stripline
• Trace width = 6 mils
• Differential trace spacing = 9 mils
• PCB thickness = 110mils, 14 layers
• Counterbored vias, 1 – 6mil stub
• Test Points = 2.4mm (included in data)
PCB BACKPLANE
• Board Material = Megtron6 HVLP
• Trace length = 30”
• Trace geometry = Stripline
• Trace width = 6 mils
• Differential trace spacing = 9 mils
• PCB thickness = 200 mils, 20 layers
• Counterbored vias, 1 – 6mil stub
• STRADA Whisper Vertical Header and
Right Angled Receptacle
CABLED BACKPLANE
• TE-Madison TurboTwin 40G Cable
• 30AWG, 1 meter [39.37”]
• STRADA Whisper Cabled Header and
Right Angled Receptacle
5 10 15 20 25 30 350 40
-80
-60
-40
-20
-100
0
freq, GHz
16.9dB
@12.89GHz
30dB
@12.89GHz
Source: TE Connectivity
16](https://image.slidesharecdn.com/oif2015foearchitecturepresentation-150409181153-conversion-gate01/85/OIF-2015-FOE-Architecture-Presentation-17-320.jpg)
OIF 2015 FOE Architecture Presentation
- 1. System Architectures Using OIF CEI-56G Interfaces Nathan Tracy Technologist, TE Connectivity Technical Committee Chair, OIF
- 2. Agenda OIF History of Common Electrical Interface (CEI) Identification of CEI-56Gb/s Requirements Typical Architectures for 56Gb/s Applications 56Gb/s Technology and Architecture Considerations Channel Improvements to Enable Architectures Summary 1
- 3. 2 Notice: This contribution has been created to assist the Optical Internetworking Forum (OIF). This document is offered to the OIF solely as a basis for discussion and is not a binding proposal on the companies listed as resources above. Each company in the source list, and the OIF, reserves the rights to at any time to add, amend, or withdraw statements contained herein. This Working Text represents work in progress by the OIF, and must not be construed as an official OIF Technical Report. Nothing in this document is in any way binding on the OIF or any of its members. The document is offered as a basis for discussion and communication, both within and without the OIF. For additional information contact: The Optical Internetworking Forum, 48377 Fremont Blvd, Suite 117, Fremont, CA 94538 510-492-4040 phone info@oiforum.com © 2015 Optical Internetworking Forum
- 4. 3 OIF Common Electrical Interface (CEI) Electrical Implementation Agreements CEI IA (Common Electrical Interface) is a clause-based format supporting publication of new clauses over time: CEI-1.0: included CEI-6G-SR, CEI-6G-LR, and CEI-11G-SR clauses. CEI-2.0: added CEI-11G-LR clause CEI-3.0: added work from CEI-25G-LR, CEI-28G-SR CEI-3.1: includes CEI-28G-MR and CEI-28G-VSR CEI-11G and -28G specifications have been used as a basis for specifications developed in IEEE 802.3, ANSI/INCITS T11, and IBTA. 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 SxI-5 CEI-1.0 CEI-2.0 CEI-3.0 3G 6G 11G 25G & 28G 56G CEI-3.1
- 5. 4 CEI-25G Application Space Chip-to-Chip (300 mm) Chip-to-Optics Chip Chip Chip Optics CEI-28G-VSR Published in CEI 3.0: LR: Backplane, passive copper cable. SR: Chip-to-chip, and chip-to-module. Published in CEI 3.1: MR: Chip-to-chip, and low loss backplane. VSR: Chip-to-module (fully retimed optics) Optics Chip Low loss Backplane (500 mm) Chip Chip CEI-28G-MR Backplane (700 mm) or Passive Copper Cable Chip Chip CEI-25G-LRCEI-28G-SR
- 6. 5 CEI Application Space is Evolving The “OIF Next Generation Interconnect Framework” white paper lays out a roadmap for CEI-56G serial links. 2.5D and 3D applications are becoming increasingly relevant. High function ASICs (such as switch chips) are driving requirements for higher I/O density and lower interface power. Emerging trends Pin density is not increasing fast enough for high density ASICs. Power reduction of 30% from one generation to next is not good enough.
- 7. 6 CEI-56G Application Spaces Chip-to-Chip & Midplane Chip-to-Module Chip Pluggable Optics CEI-56G-USR USR: 2.5D/3D applications 1 cm, no connectors, no packages XSR: Chip to nearby optics engine 5 cm, no connectors 5-10 dB loss @28 GHz VSR: Chip-to-module 10 cm, 1 connector 10-20 dB loss @28 GHz MR: Interfaces for chip to chip and midrange backplane 50 cm, 1 connector 15-25 dB loss @14 GHz 20-50 dB loss @28 GHz LR: Interface for chip to chip over a backplane 100cm, 2 connectors 35dB at 14Ghz Chip Chip Backplane or Passive Copper Cable Chip Chip 3D Stack CEI-56G-XSR CEI-56G-VSR 2.5D Chip-to-OE Optics Chip Chip to Nearby OE CEI-56G-MR CEI-56G-LR Ultra short reach Extra short reach Very short reach Medium reach Long reach
- 8. 7 Optical Line Card Evolution Today’s 100G based optical system based on 28G electrical interconnects These 100G systems could eventually increase density by migrating to 2x50G optical modules leveraging the OIF’s 56G-VSR specification Line Card CFP4/QSFP28 100G Module Tx/Rx Optics RetimerRetimer BackplaneSwitch Card Retimer ASICASIC 4x 25GNx 25GNx 25G Nx 25G (CEI-25G-LR, 100GBASE-KR4) (CEI-28G- SR/MR, CAUI-4 c2c) (CEI-28G-VSR, CAUI-4 c2m) (CEI-28G- SR/MR) 4x 25G 10-12 dB chip-to-module interface 35dB 100GBASE-KR4 backplane interface 15-20 dB chip-to-chip interface Source: Semtech
- 9. 8 200G/400G Optical Line Card Possible long term 4x/8x 50G optical system 56G-VSR enables higher density 200G/400G optical line card Note that 56G PAM4 max interconnect losses reflect those of 28G NRZ allowing for similar component placement to today’s 100G line card! Line Card 400G Module Tx/Rx Optics Retimer Retimer BackplaneSwitch Card Retimer ASICASIC 8x 56G Nx 56GNx 56G Nx 56G (CEI-56G-LR-PAM4) (CEI-56G- MR-PAM4, CDAUI-8 c2c) (CEI-56G-VSR-PAM4, CDAUI-8 c2m) 8x 56G 10dB PAM4 chip-to-module interface 35dB PAM4 backplane interface 15-20 dB PAM4 chip-to-chip interface (CEI-56G- MR-PAM4, CDAUI-8 c2c) 200G Module Tx/Rx Optics Retimer 4x 56G 4x 56G Source: Semtech Note: PAM4 examples shown, could also be NRZ
- 10. 9 56G PAM-4 IC Technology Selection CMOS/SiGe implementation tradeoffs CMOS suitable for Line Card SerDes Potentially SiGe or CMOS for Module Retimer depending upon IC functionality & complexity Factor CMOS SiGe BiCMOS Notes Analog Performance Favors SiGe SiGe analog performance typically better (jitter, NF, etc) Digital Complexity Favors CMOS Functions such as FEC challenging in SiGe Cost Favors SiGe NRZ likely to require more complex equalization Equalization Options Analog ADC/DSP Analog PAM-4 lends itself to DAC/ADC approach though analog approaches still feasible pJ/bit efficiency Expect comparable transceiver efficiencies Source: Semtech
- 11. Cable Backplane Demo 50G NRZ Eval Board (Tx) Cable Backplane • 46” total channel length • 40” copper backplane (30 gauge) • Two STRADA Whisper connectors • Two break out cards (5” & 1”) 50G NRZ Eval Board (Rx) Cables Cables Insertion Loss ~ 23dB at 25Ghz Insertion Loss ~ 1.5dB at 25Ghz Insertion Loss ~ 1.5dB at 25Ghz BER ~ 1e-12 50G NRZ Progress Test board Source: Credo 10
- 12. Transitioning from 25Gb/s to 56Gb/s Same number of IO Core logic complexity scales to 4X • 28nm to 16nm process node But LR Serdes may hardly scale • Limitations in die area and power density USR and XSR may enable higher density architectures by providing a low power interface Ability to escape to a SerDes which can support multiple applications (VSR, MR, LR) 11 45mm 45mm 27mm 27m m Core Logic 16nm Serdes Serdes Serdes Serdes Serdes Serdes Serdes Serdes Package Ball View Next Generation Switch Chip - Doubling the capacity Source: Alcatel Lucent
- 13. System OEM Perspective on 56Gb/s • Product flexibility – must drive worst case Channel I/O will see • VSR turns into MR or even LR(Lite) -> PAM4 • Transistor BW/Nyquist Rate ratio varies greatly between process technologies; 50GHZ power/performance is effected by process (CMOS, SiGe, etc.) • Can’t just look at channel characteristics, must be IC/Channel optimized • No errors after FEC (in large systems even 10^-18 BER have >1error/hr.; unacceptable) • Need Low BER before FEC • Broadband effects (transient behavior vs. pure steady state) • Eliminate as many broadband effects as possible • Broadband effects stress adaptation and reduce FEC efficiency. Source: Juniper Networks 12
- 14. ASIC used in various systems System MR Channel System Channels Suck out rules out 56G NRZ Source: Juniper Networks13
- 15. Orthogonal Backplane Traditional Backplane * Backplane Trace Full Power Serdes on IC capable of 35 dB channel Loss without need for retimers STRADA Whisper daughtercardTrace daughtercardTrace IC STRADA Whisper Traditional Backplane and Orthogonal LR SERDES POWER LR SERDES POWER Backplane Trace IC Source: TE Connectivity Power 56 Gbps Reach (PAM4) Traditional PCB & STRADA Whisper Connector 100% (LR Serdes) 1m 14
- 16. Cabled Backplane Shuffle Cabled Backplane * Full Power Serdes on Retimer capable of 35 dB channel STRADA Whisper Cable daughtercardTrace daughtercardTrace IC STRADA Whisper Cable Cable Backplanes: Margin/Thermal/Reach LR/SR SERDES POWER LR/SR SERDES POWER IC Source: TE Connectivity Power 56 Gbps Reach (PAM4) Traditional PCB & STRADA Whisper Connector 100% (LR Serdes) 1m STRADA Whisper Cable Backplane Connector 100% (LR Serdes) 3m Traditional PCB & STRADA Whisper Connector With Retimers 150% (VSR + AEC) 1.5m 15
- 17. Insertion Loss DAUGHTER CARD • Board Material = Megtron6 VLP • Trace length = 5” • Trace geometry = Stripline • Trace width = 6 mils • Differential trace spacing = 9 mils • PCB thickness = 110mils, 14 layers • Counterbored vias, 1 – 6mil stub • Test Points = 2.4mm (included in data) PCB BACKPLANE • Board Material = Megtron6 HVLP • Trace length = 30” • Trace geometry = Stripline • Trace width = 6 mils • Differential trace spacing = 9 mils • PCB thickness = 200 mils, 20 layers • Counterbored vias, 1 – 6mil stub • STRADA Whisper Vertical Header and Right Angled Receptacle CABLED BACKPLANE • TE-Madison TurboTwin 40G Cable • 30AWG, 1 meter [39.37”] • STRADA Whisper Cabled Header and Right Angled Receptacle 5 10 15 20 25 30 350 40 -80 -60 -40 -20 -100 0 freq, GHz 16.9dB @12.89GHz 30dB @12.89GHz Source: TE Connectivity 16
- 18. Mid Board Optics Switch Optical Backplane System ½ Power Serdes + E/O + O/E Optical Power. 100M Reach including 2 Optical connectors Optical BackplaneMBO MBOMXCMXC Optical Backplanes: Density/Reach Extension Source: TE Connectivity Power 56 Gbps Reach (PAM4) Traditional PCB & STRADA Whisper Connector 100% (LR Serdes) 1m STRADA Whisper Cable Backplane Connector 100% (LR Serdes) 3m Traditional PCB & STRADA Whisper Connector With Retimers 150% (VSR + AEC) 1.5m VCSEL Optical Backplane 150% (VSR + Optics) 100m 17
- 19. Mid Board Optics for I/O 18 Source: TE Connectivity Power 56 Gbps Reach (PAM4) Traditional PCB w/ Direct Attach Passive Cable 100% Reference 3m Traditional PCB w/ Pluggable VCSEL Optics 150% 100m Traditional PCB w/ Power Retimers and Dirct Attach Passive Cable 150% 5m Mid Board VCSEL Optics 150% 100m
- 20. 19 Summary 56G systems require a balancing of requirements: • connector/channel demands • semiconductor demands • equipment demands New processing techniques can enable new architectures Higher performance channels can enable new architectures Integrated optics can enable new architectures High performance systems based on 56Gb/s signaling rates are being enabled by the OIF‘s CEI-56G projects Come join the OIF! www.oiforum.com