Original DARLING TRANSISTOR ARRAY IC ULQ2003A 2003A 2003 SOP-16 New Texas Instrusments

7C
6C
5C
4C
3C
2C
1C
COM
7
6
5
4
3
2
1
7B
6B
5B
4B
3B
2B
1B
10
11
12
13
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9
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ULQ2003A-Q1, ULQ2004A-Q1
SGLS148E –DECEMBER 2002–REVISED DECEMBER 2015
ULQ200xA-Q1 High-Voltage High-Current Darlington Transistor Arrays
1 Features 3 Description
The ULQ200xA-Q1 devices are high-voltage high-1• Qualified for Automotive Applications
current Darlington transistor arrays. Each consists of
• ESD Protection Exceeds 200 V Using Machine seven npn Darlington pairs that feature high-voltage
Model (C = 200 pF, R = 0) outputs with common-cathode clamp diodes for
• 500-mA-Rated Collector Current (Single Output) switching inductive loads. The collector-current rating
of a single Darlington pair is 500 mA. The Darlington• High-Voltage Outputs: 50 V
pairs can be paralleled for higher current capability.
• Output Clamp Diodes
The ULQ2003A-Q1 has a 2.7-kΩ series base resistor• Inputs Compatible With Various Types of Logic
for each Darlington pair, for operation directly with
• Relay-Driver Applications TTL or 5-V CMOS devices. The ULQ2004A-Q1 has a
10.5-kΩ series base resistor to allow operation
2 Applications directly from CMOS devices that use supply voltages
of 6 V to 15 V. The required input current of the• Relay Drivers
ULQ2004A-Q1 is below that of the ULQ2003A-Q1.
• Stepper and DC Brushed Motor Drivers
• Lamp Drivers Device Information(1)
• Display Drivers (LED and Gas Discharge) PART NUMBER PACKAGE BODY SIZE (NOM)
• Line Drivers SOIC (16) 9.90 mm x 3.90 mm
ULQ2003A-Q1
TSSOP (16) 5.00 mm x 4.40 mm• Logic Buffers
ULQ2004A-Q1 SOIC (16) 9.90 mm x 3.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Block Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

SGLS148E –DECEMBER 2002–REVISED DECEMBER 2015 www.ti.com
Table of Contents
8.2 Functional Block Diagram ......................................... 91 Features.................................................................. 1
8.3 Feature Description................................................. 102 Applications ........................................................... 1
8.4 Device Functional Modes........................................ 103 Description ............................................................. 1
9 Application and Implementation ........................ 114 Revision History..................................................... 2
9.1 Application Information............................................ 11
5 Pin Configuration and Functions......................... 3
9.2 Typical Application .................................................. 11
6 Specifications......................................................... 4
9.3 System Examples ................................................... 14
6.1 Absolute Maximum Ratings ..................................... 4
10 Power Supply Recommendations ..................... 156.2 ESD Ratings.............................................................. 4
11 Layout................................................................... 156.3 Recommended Operating Conditions....................... 4
11.1 Layout Guidelines ................................................. 156.4 Thermal Information.................................................. 4
11.2 Layout Example .................................................... 156.5 Electrical Characteristics, ULQ2003AT and
ULQ2003AQ............................................................... 5 12 Device and Documentation Support ................. 16
6.6 Electrical Characteristics, ULQ2004AT..................... 5 12.1 Related Links ........................................................ 16
6.7 Switching Characteristics, ULQ2003A and 12.2 Community Resources.......................................... 16
ULQ2004A ................................................................. 6 12.3 Trademarks........................................................... 16
6.8 Dissipation Ratings ................................................... 6 12.4 Electrostatic Discharge Caution............................ 16
6.9 Typical Characteristics.............................................. 6 12.5 Glossary................................................................ 16
7 Parameter Measurement Information .................. 7 13 Mechanical, Packaging, and Orderable
8 Detailed Description .............................................. 9 Information ........................................................... 16
8.1 Overview ................................................................... 9
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (April 2010) to Revision E Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
2 Submit Documentation Feedback Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: ULQ2003A-Q1 ULQ2004A-Q1

1B 1 16
2B 2 15
3B 3 14
4B 4 13
5B 5 12
6B 6 11
7B 7 10
E 8 9
1C
2C
3C
4C
5C
6C
7C
COM
www.ti.com SGLS148E –DECEMBER 2002–REVISED DECEMBER 2015
5 Pin Configuration and Functions
D or PW Package
16-Pin SOIC or TSSOP
Top View
Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
1 1B
2 2B
3 3B
4 4B I Channel 1 through 7 Darlington base input
5 5B
6 6B
7 7B
8 E — Common emitter shared by all channels (typically tied to ground)
9 COM — Common cathode node for flyback diodes (required for inductive loads)
10 7C
11 6C
12 5C
13 4C O Channel 1 through 7 Darlington collector output
14 3C
15 2C
16 1C
Copyright © 2002–2015, Texas Instruments Incorporated Submit Documentation Feedback 3

6 Specifications
6.1 Absolute Maximum Ratings
at 25°C free-air temperature (unless otherwise noted)(1)
MIN MAX UNIT
VCE Collector-emitter voltage 50 V
Clamp diode reverse voltage(2)
50 V
VI Input voltage(2)
30 V
Peak collector current See Figure 16 500 mA
IOK Output clamp current 500 mA
Total emitter-terminal current –2.5 A
See Dissipation
PD Continuous total power dissipation
Ratings
ULQ200xAT –40 105
TA Operating free-air temperature °C
ULQ200xAQ –40 125
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the emitter/substrate terminal E, unless otherwise noted.
6.2 ESD Ratings
VALUE UNIT
Human-body model (HBM), per AEC Q100-002(1)
±2000Electrostatic
V(ESD) V
discharge Charged-device model (CDM), per AEC Q100-011 ±500
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCE Collector-emitter voltage 0 50 V
TJ Junction temperature –40 125 °C
6.4 Thermal Information
ULQ2003A-Q1,
ULQ2003A-Q1
ULQ2004A-Q1
THERMAL METRIC(1)
UNIT
D (SOIC) PW (TSSOP)
16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 73 108 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

6.5 Electrical Characteristics, ULQ2003AT and ULQ2003AQ
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IC = 200 mA 2.7
VCE = 2 V, see
VI(on) On-state input voltage IC = 250 mA 2.9 V
Figure 10
IC = 300 mA 3
ULQ2003AT 0.9 1.2
II = 250 μA,IC = 100 mA, see Figure 9
ULQ2003AQ 1 1.3
ULQ2003AT 1 1.4Collector-emitter
VCE(sat) II = 350 μA,IC = 200 mA, see Figure 9 V
saturation voltage ULQ2003AQ 1 1.5
ULQ2003AT 1.2 1.7
II = 500 μA,IC = 350 mA, see Figure 9
ULQ2003AQ 1.2 1.8
VCE = 50 V, TA = 25°C 100
ICEX Collector cutoff current II = 0, see μA
TA = 105°C, ULQ2003AT 165Figure 3
VF Clamp forward voltage IF = 350 mA, see Figure 8 1.7 2.2 V
II(off) Off-state input current VCE = 50 V, IC = 500 μA, see Figure 5 30 65 μA
II Input current VI = 3.85 V, see Figure 6 0.93 1.35 mA
IR Clamp reverse current VR = 50 V, TA = 25°C, see Figure 7 100 μA
Ci Input capacitance VI = 0, f = 1 MHz 15 25 pF
6.6 Electrical Characteristics, ULQ2004AT
IC = 125 mA 5
IC = 200 mA 6VCE = 2 V, see
VI(on) On-state input voltage V
Figure 10 IC = 275 mA 7
IC = 350 mA 8
II = 250 μA, IC = 100 mA, see Figure 9 0.9 1.1
Collector-emitter saturation
VCE(sat) II = 350 μA, IC = 200 mA, see Figure 9 1 1.3 V
voltage
II = 500 μA, IC = 350 mA, see Figure 9 1.2 1.6
TA = 25°C 50VCE = 50 V,
II = 0, See Figure 3 TA = 105°C
ICEX Collector cutoff current μA
II = 0 100VCE = 50 V, see
Figure 4 VI = 1 V 500
VF Clamp forward voltage IF = 350 mA, see Figure 8 1.7 2.1 V
II(off) Off-state input current VCE = 50 V, IC = 500 μA, see Figure 5 50 65 μA
VI = 5 V, see Figure 6 0.35 0.5
II Input current mA
VI = 12 V, , see Figure 6 1 1.45
TA = 25°C 50VR = 50 V, see
IR Clamp reverse current μA
Figure 7 TA = 105°C 100
Ci Input capacitance VI = 0, f = 1 MHz 15 25 pF

0
IC - Collector Current - mA
2.5
800
0
100 200 300 400 500 600 700
0.5
1
1.5
2
II = 350 µA
II = 500 µA
VCE(sat)-Collector-EmitterSaturationVoltage-VVCE(sat)
TA = 25°C
II = 250 µA
2
1.5
1
0.5
700600500400300200100
0
800
2.5
IC(tot) - Total Collector Current - mA
0
VCE(sat)-Collector-EmitterSaturationVoltage-VVCE(sat)
II = 250 µA
II = 350 µA
II = 500 µA
TA = 25°C
6.7 Switching Characteristics, ULQ2003A and ULQ2004A
tPLH Propagation delay time, low- to high-level output See Figure 11 1 10 μs
tPHL Propagation delay time, high- to low-level output See Figure 11 1 10 μs
VOH High-level output voltage after switching VS = 50 V, IO = 300 mA, See Figure 12 VS – 500 mV
6.8 Dissipation Ratings
DERATING
TA = 25°C
FACTOR TA = 85°C TA = 105°C TA = 125°C
PACKAGE POWER
ABOVE POWER RATING POWER RATING POWER RATING
RATING
TA = 25°C
D 950 mW 7.6 mW/°C 494 mW 342 mW 190 mW
6.9 Typical Characteristics
Figure 2. Collector-Emitter Saturation Voltage vs Total
Figure 1. Collector-Emitter Saturation Voltage vs Collector
Collector Current (Two Darlingtons in Parallel)
Current (One Darlington)

Open
VCE IC
VI(on)
Open
VCE ICII
hFE =
IC
II
Open VCE
ICII(off)
IF
VF
Open
VR
Open
IR
Open VCE
VI
ICEX
Open
Open
II(on)
VI
Open VCE
Open
ICEX
7 Parameter Measurement Information
Figure 3. ICEX Test Circuit
Figure 6. II Test Circuit
Figure 4. ICEX Test Circuit
Figure 7. IR Test Circuit
Figure 5. II(off) Test Circuit Figure 8. VF Test Circuit
A. II is fixed for measuring VCE(sat), variable for
measuring hFE. Figure 10. VI(on) Test Circuit
Figure 9. hFE, VCE(sat) Test Circuit
Figure 11. Propagation Delay-Time Waveforms

90% 90%
1.5 V 1.5 V
10% 10%
40 µs
≤10 ns≤5 ns
VIH
(see Note C)
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
200 W
A. The pulse generator has the following characteristics: PRR = 12.5 kHz, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
C. For testing the ULQ2003A, VIH = 3 V; for the ULQ2004A, VIH = 8 V.
Figure 12. Latch-Up Test Circuit and Voltage Waveforms

7C
6C
5C
4C
3C
2C
1C
COM
7
6
5
4
3
2
1
7B
6B
5B
4B
3B
2B
1B
10
11
12
13
14
15
16
9
8 Detailed Description
8.1 Overview
This standard device has proven ubiquity and versatility across a wide range of applications. This is due to
integration of 7 Darlington transistors of the device that are capable of sinking up to 500 mA and wide GPIO
range capability.
The ULQ200xA-Q1 devices comprise seven high-voltage, high-current NPN Darlington transistor pairs. All units
feature a common emitter and open collector outputs. To maximize their effectiveness, these units contain
suppression diodes for inductive loads. The ULNQ200xA-Q1 devices have a series base resistor to each
Darlington pair, thus allowing operation directly with TTL or CMOS operating at supply voltages of 5 V or 3.3 V.
The ULQ2003xA-Q1 device offers solutions to a great many interface needs, including solenoids, relays, lamps,
small motors, and LEDs. Applications requiring sink currents beyond the capability of a single output may be
accommodated by paralleling the outputs.
This device can operate over a wide temperature range (–40°C to 105°C for ULQ200xAT or –40°C to 125°C for
ULQ2003AQ).
8.2 Functional Block Diagram
Figure 13. Logic Diagram

ULQ2003A: R = 2.7 kB W
ULQ2004A: R = 10.5 kB W 7.2 kW 3 kW
RB
Functional Block Diagram (continued)
A. All resistor values shown are nominal.
B. The collector-emitter diode is a parasitic structure and should not be used to conduct current. If the collector(s) go
below ground an external Schottky diode should be added to clamp negative undershoots.
Figure 14. Schematics (Each Darlington Pair)
8.3 Feature Description
Each channel of the ULQ200xA-Q1 devices consist of Darlington connected NPN transistors. This connection
creates the effect of a single transistor with a very high-current gain (β2). This can be as high as 10,000 A/A at
certain currents. The very high β allows for high-output current drive with a very low input current, essentially
equating to operation with low GPIO voltages.
The GPIO voltage is converted to base current through the 2.7-kΩ or 10.5-kΩ resistor connected between the
input and base of the predriver Darlington NPN. The 7.2-kΩ and 3-kΩ resistors connected between the base and
emitter of each respective NPN act as pulldowns and suppress the amount of leakage that may occur from the
input.
The diodes connected between the output and COM pin is used to suppress the kick-back voltage from an
inductive load that is excited when the NPN drivers are turned off (stop sinking) and the stored energy in the
coils causes a reverse current to flow into the coil supply through the kick-back diode.
In normal operation the diodes on base and collector pins to emitter will be reversed biased. If these diodes are
forward biased, internal parasitic NPN transistors will draw (a nearly equal) current from other (nearby) device
pins.
8.4 Device Functional Modes
8.4.1 Inductive Load Drive
When the COM pin is tied to the coil supply voltage, ULQ200xA-Q1 devices are able to drive inductive loads and
suppress the kick-back voltage through the internal free-wheeling diodes.
8.4.2 Resistive Load Drive
When driving a resistive load, a pullup resistor is needed in order for the ULQ200xA-Q1 devices to sink current
and for there to be a logic high level. The COM pin can be left floating for these applications.

IN1
IN2
ULQ2003A-Q1
IN3
IN4
OUT1
OUT2
OUT3
OUT4
IN5
IN6
IN7
GND
OUT5
OUT6
OUT7
COM
3.3-V Logic
3.3-V Logic
3.3-V Logic
VSUP
VSUP
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Typically, the ULQ200xA-Q1 device drives a high-voltage or high-current (or both) peripheral from an MCU or
logic device that cannot tolerate these conditions. This design is a common application of ULQ200xA-Q1 device,
driving inductive loads. This includes motors, solenoids and relays. Figure 15 shows an example of driving
multiple inductive loads.
9.2 Typical Application
Figure 15. ULQ2003A-Q1 Device as Inductive Load Driver
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the input parameters.
Table 1. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
GPIO voltage 3.3 V or 5 V
Coil supply voltage 12 V to 48 V
Number of channels 7
Output current (RCOIL) 20 mA to 300 mA per channel
Duty cycle 100%

( )J(MAX) A
(MAX)
JA
T T
PD
-
=
q
N
D OLi Li
i 1
P V I
=
= ´å
9.2.2 Detailed Design Procedure
When using ULQ2003A-Q1 device in a coil driving application, determine the following:
• Input voltage range
• Temperature range
• Output and drive current
• Power dissipation
9.2.2.1 Drive Current
The coil voltage (VSUP), coil resistance (RCOIL), and low-level output voltage (VCE(SAT) or VOL) determine the coil
current.
ICOIL = (VSUP – VCE(SAT)) / RCOIL (1)
9.2.2.2 Low-Level Output Voltage
The low-level output voltage (VOL) is the same as VCE(SAT) and can be determined by, Figure 1 or Figure 2.
9.2.2.3 Power Dissipation and Temperature
The number of coils driven is dependent on the coil current and on-chip power dissipation. The number of coils
driven can be determined by Figure 16.
For a more accurate determination of number of coils possible, use Equation 2 to calculate ULQ200xA-Q1 device
on-chip power dissipation PD:
where
• N is the number of channels active together
• VOLi is the OUTi pin voltage for the load current ILi. This is the same as VCE(SAT) (2)
To ensure reliability of ULQ200xA-Q1 device and the system, the on-chip power dissipation must be lower that or
equal to the maximum allowable power dissipation (PD(MAX)) dictated by Equation 3.
where
• TJ(max) is the target maximum junction temperature
• TA is the operating ambient temperature
• RθJA is the package junction to ambient thermal resistance (3)
Limit the die junction temperature of the ULQ200xA-Q1 device to less than 125°C. The IC junction temperature is
directly proportional to the on-chip power dissipation.

0
Duty Cycle - %
600
100
0
10 20 30 40 50 60 70 80 90
100
200
300
400
500
TA = 70°C
N = Number of Outputs
Conducting Simultaneously
N = 6
N = 7
N = 5
N = 3
N = 2
N = 1
IC-MaximumCollectorCurrent-mACI
N = 4
9.2.3 Application Curve
Figure 16. D Package Maximum Collector Current vs Duty Cycle

VCC V
RP
ULQ2003A
1
2
3
4
5
6
9
10
11
12
13
14
15
16
8
TTL
Output
7
ULQ2003A
Lam
TestTTL
Output
VCC V
1
2
3
4
5
6
9
10
11
12
13
14
15
16
8
7
VDD VULQ2004A
1
2
3
4
5
6
9
10
11
12
13
14
15
16
8
CMOS
Output
7
9.3 System Examples
Figure 17. TTL to Load Figure 18. Buffer for Higher Current Loads
Figure 19. Use of Pullup Resistors to Increase Drive Current

1
2
3
4
8 VCOM
7
6
5
16
E 9
15
14
13
12
11
10
1B
2B
3B
4B
7B
6B
5B
1C
2C
3C
4C
7C
6C
5C
GND
10 Power Supply Recommendations
This device does not need a power supply. However, the COM pin is typically tied to the system power supply.
When this is the case, it is very important to ensure that the output voltage does not heavily exceed the COM pin
voltage. This discrepancy heavily forward biases the fly-back diodes and causes a large current to flow into
COM, potentially damaging the on-chip metal or over-heating the device.
11 Layout
11.1 Layout Guidelines
Thin traces can be used on the input due to the low-current logic that is typically used to drive the ULQ200xA-Q1
devices. Take care to separate the input channels as much as possible, as to eliminate crosstalk. TI
recommends thick traces for the output to drive whatever high currents that may be needed. Wire thickness can
be determined by the current density of the trace material and desired drive current.
Because all of the channels currents return to a common emitter, it is best to size that trace width to be very
wide. Some applications require up to 2.5 A.
11.2 Layout Example
Figure 20. Package Layout

12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
ULQ2003A-Q1 Click here Click here Click here Click here Click here
ULQ2004A-Q1 Click here Click here Click here Click here Click here
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
ULQ2003AQDRQ1 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br)
NIPDAU Level-1-260C-UNLIM -40 to 125 ULQ2003AQ
ULQ2003ATDG4Q1 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br)
NIPDAU Level-1-260C-UNLIM -40 to 105 ULQ2003AT
ULQ2003ATDQ1 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br)
ULQ2003ATDRG4Q1 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br)
ULQ2003ATDRQ1 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br)
ULQ2003ATPWRQ1 ACTIVE TSSOP PW 16 2500 Green (RoHS
& no Sb/Br)
NIPDAU Level-1-260C-UNLIM -40 to 105 U2003AT
ULQ2004ATDRG4Q1 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br)
ULQ2004ATDRQ1 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 2
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ULQ2003A-Q1, ULQ2004A-Q1 :
•Catalog: ULQ2003A, ULQ2004A
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product

TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
ULQ2003ATPWRQ1 TSSOP PW 16 2500 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Aug-2017
Pack Materials-Page 1

*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ULQ2003ATPWRQ1 TSSOP PW 16 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Aug-2017
Pack Materials-Page 2

Original DARLING TRANSISTOR ARRAY IC ULQ2003A 2003A 2003 SOP-16 New Texas Instrusments

www.ti.com
PACKAGE OUTLINE
C
14X 0.65
2X
4.55
16X
0.30
0.19
TYP
6.6
6.2
1.2 MAX
0.15
0.05
0.25
GAGE PLANE
-80
B
NOTE 4
4.5
4.3
A
NOTE 3
5.1
4.9
0.75
0.50
(0.15) TYP
TSSOP - 1.2 mm max heightPW0016A
SMALL OUTLINE PACKAGE
4220204/A 02/2017
1
8
9
16
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
SEATING
PLANE
A 20
DETAIL A
TYPICAL
SCALE 2.500

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EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
8 9
16
15.000
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
EXPOSED METALEXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED

www.ti.com
EXAMPLE STENCIL DESIGN
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
8 9
16

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Copyright © 2020, Texas Instruments Incorporated

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