Oth1

Practice Problems with Solutions 1

These practice problems are related to the following chapters:
Chapter 1: Digital Logic and Microprocessor Design
Chapter 2: Case Study in Computer Design
Chapter 6: Network Systems
Chapter 9: Programming Languages
Chapter 10: Operating Systems
Chapter 11: Software Reliability and Safety
In addition, there are circuit analysis problems that support Chapters 1 and 2.

CHAPTER 1 (DIGITAL LOGIC AND
MICROPROCESSOR DESIGN) AND CHAPTER 2
(CASE STUDY IN COMPUTER DESIGN)

Number Representation in Floating-Point Format

Problem 1
Given: S is a sign bit where 0 indicates positive 1 and 0 indicates negative;
exponent is a 7-bit excess 64 power of 2; mantissa is an 8-bit fraction.
Problem: A 16-bit word, N = 400016, represents what decimal numeric value?
Solution: 400016 = 0100 0000 0000 0000
Sign 0 = positive, mantissa = 0000 0000, excess 64 power of 2 exponent =
1000000 – 1000000 = 0

Computer, Network, Software, and Hardware Engineering with Applications, First Edition. Norman F.
Schneidewind.
© 2012 the Institute of Electrical and Electronics Engineers, Inc. Published 2012 by John Wiley &
Sons, Inc.

466

Practice Problems with Solutions 1 467

Byte 0 Byte 1

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Sign Excess 64 Exponent Normalized Mantissa

2(e–64) × 0.1ffffffff

8 bits in Normalized Mantissa: “1” in left-most bit position
Figure 1 Floating point format.

Answer: N = 0 (2)0 = 0.0
Mantissa Exponent
Problem 2
Given: The floating point format design shown in Figure 1.
Problem: Can the decimal number 111.875 be stored in this format? If not, what
decimal values can be stored?
Solution: 111.875 cannot be stored because the mantissa 0.875 requires more
than 8 bits. However, 118.75 can be stored because this mantissa 0.75
requires only 7 bits, as shown in the following number conversions:
0.87510 = 0.361116 = 0.110110 10112: 10 bits, 0.7510 = 0.41116 = 0.100 10112: 7 bits
3 6 11 4 11
These conversions are achieved by successively dividing the decimal number by 16,
recording the remainders, and assigning the remainders to the hexadecimal numbers
in reverse order.

Encoding

One-Hot Encoding
One-hot encoding is a type of data encoding in which an individual flip-flop is dedi-
cated to only one state of the data. Thus, only one flip-flop, which stores the data,
can be active, or hot, at a time.
Problem 3
Given: A central processing unit (CPU) is designed with one-hot encoding. This
CPU cycles through 16 states and produces 32 control signals (one for flip-
flop output high and one for output low, for each of 16 states).
Problem: How many flip-flops are required?
Answer: Sixteen are required, corresponding to each of the 16 states.

468 Computer, Network, Software, and Hardware Engineering with Applications

Table 1 Hamming Code Words

D6 D5 D4 D3 D2 D1 D0
I3 I2 I1 P2 I0 P1 P0
1 1 1 1 0 0 0
1 1 0 0 1 1 0
1 0 1 0 1 0 1

Error Detection and Correction

The Hamming Code is a type of error detection and correction code that uses parity
bits as a check for possible errors in the information bits. It is capable of detecting
two bits in error and correcting one.

D6 D5 D4 D3 D2 D1 D0 Data bit positions
I3 I2 I1 P2 I0 P1 P0 Code word

Parity bits (P) are located in data bit positions P0, P1, and P2.
Information bits (I3, I2, I1, I0) are located in the remaining bit positions.
Problem 4
Given: Hamming code words in Table 1. One of the code words has information
bits 11102.
Problem: What is the correct Hamming Code word?
Solution: Only the ﬁrst code word has the required information bits (in red).
Therefore, the code word is 11110002.

Parity Error Detection
In even parity error detection, if the number of one bits, including the parity bit, is
an even number, the data are assumed to be correct; otherwise, a one-bit error is
assumed. In odd parity error detection, if the number of one bits, including the parity
bit, is an odd number, the data are assumed to be correct; otherwise, a one-bit error
is assumed. Thus, parity error detection can detect one-bit errors but cannot correct
these errors. If a parity error is detected at the receiver, a negative acknowledgement
is sent to the transmitter to retransmit the message.
Problem 5
Problem: It is desired to use even parity error detection in a digital circuit, where P is
the parity bit. Which of the data below would generate even parity error signals?
P
0010 odd (error)
0100 odd (error)
0101 even (correct)
0111 odd (error)


Cyclic Redundancy Check (CRC)

This is a sophisticated error detection and correction process that uses mathematical
polynomials for detecting and correcting multiple errors.
A message of degree n is the polynomial M(x) is: xn + xn−1 + xn−2 + . . . + x0.
The sender and receiver must agree on a generator polynomial G(x) of degree
k ≤ n in advance of transmission.
Both the high and low bits of G(x) must be 1.
M(x) must be longer than G(x).
k zeros are appended to M(x), yielding the transmitted message T(x) = M(x) xk.
The remaining operations are shown in the following example:
Example:

M(x ) = x 2 + x + 1 = 111

Use G(x) = x + 1 = 11 because M(x) can be divided by G(x) (i.e., the degree of
G(x) = 1 ≤ degree of M(x) = 2).
k = degree 1, therefore append one zero to M(x), yielding the following trans-
mitted message:

T(x) = M(x)x k = x 3 + x 2 + x = 2 3 + 2 2 + 21 = 1410 = 111016.

Divide T(x) by G(x), using modulo 2 division, and record remainder R(x), using
modulo 2 division:

100
)
11 110 .
11
001
00
010
00
R(x ) = 10

Now, subtract remainder R(x) = 10 from M(x)xk = 1110, using Exclusive Or sub-
traction (modulo 2):

M(x )x k ⊕ R(x ) = 1110 ⊕ 10 = 1100.

At the receiver, divide (M(x)xk R(x)) by G(x) and check for zero remainder. If
this is the case, there is no error in transmission; otherwise, there are one or more
errors, so retransmit:


100
)
11 1100
11
000
00
00
Check: 12/3 = 4.
The remainder is zero, so there is no error in transmission.
Problem 6
Given: CRC polynomial: x16 + x12 + x5 + 1 = x16 + x12 + x5 + x0 = 216 + 212 + 25
+ 1 = 65536 + 4096 + 32 + 1
Problem: What is the hexadecimal equivalent of this CRC polynomial?
The solution is obtained by placing ones in the power of twos positions, cor-
responding to the decimal numbers as follows:

x16 + x12+ x5 + 1 = 1 0001 0000 0010 0001 = 1102116
65536 4096 32 1
Proof: x16 + x12 + x5 + 1 = 69,66510. Convert 1102116 to base 10:
(1*16 4 ) + (1*163 ) + (2*161 ) + (1*160 ) = 65, 536 + 4, 096 + 32 + 1 = 69, 665

Instruction Formats

Problem 7
Given: The instruction register below contains AB616 as the next instruction to
be executed. Assuming this is an add accumulator to operand at effective
address instruction, the instruction format is the following:
11 10 7 6 0
Op Code Address Instruction register

1 0101 011 0110

Indirect address indicator
Identify the op code bits:
Bolded bits are op code bits: AB616 = 1010 1011 0110 (hexadecimal converted
to binary)
Solution: Using indirect addressing as signiﬁed by bit 11 = 1: Op code bits = bits
10:7 = 0101: add accumulator + operand at effective address 011 0110
(address located at 011 0110).


Problem 8
Given: The above instruction format in Problem 7 of 12 bits per word.
Problem: What is the maximum memory size in bits?
Answer: There are 27 addresses, each of which is 12 bits long. Therefore,
memory size = 12 × 27 bits = 12 × 128 = 1536 bits.

Pipeline Systems

Number of clock cycles required in pipelined system = Number of clock cycles
required in conventional system – Number of overlapped clock cycles in pipelined
system = mn – (m – 1)(n – 1), where m is the number of instructions and n is the
number of clock cycles required by the first instruction. This is the case because for
the first instruction, there is no preceding instruction to overlap with. Therefore,
there are m – 1 overlapped instructions. Also, the last clock cycle of the m – 1 over-
lapped instructions are not overlapped with a clock cycle of the preceding instruc-
tions, yielding (m – 1)(n – 1) overlapped clock cycles in a pipeline system.
Problem 9
There are four instructions in a pipelined system. How many clock cycles are
required to execute the four instructions?
Solution: The first instruction requires n = 4 clock cycles and each of the remain-
ing (m – 1) instructions require only 1 clock cycle because these (m – 1) instruc-
tions are overlapped with the preceding instructions, yielding n + (m – 1) =
4 + 3 clock cycles.
Problem 10
What is the increase in speed of the pipelined system in Problem 9 versus a non-
pipelined system?
Solution: The speed ratio = Number of clock cycles required in conventional
system/Number of clock cycles required in a pipelined system = mn/
(m + n – 1) = 16/7 = 2.286. If m is large, the increase in speed approaches
the maximum speed of n clock cycles per instruction.
Problem 11
Pipeline throughput is defined as the number of instructions, m, per total clock cycle
time required to process m instructions = (m instructions)/((number of clock cycles
per instruction*time per clock cycle)) = (m)/(m + n – 1)T, where T is clock cycle
time per instruction. For a typical microprocessor with a clock speed of 10 MHz
(107 cycles per second), T = 1/107 seconds.
What is the throughput for a four-instruction pipeline?
Solution: m/((m + n – 1)T) = 4/((7)(1/107))) = (4)(107)/7 = 5.71 million instruc-
tions per second.
Problem 12
Pipeline efficiency is computed as: actual speed increase/maximum speed increase.


What is the efﬁciency for the pipeline in Problem 10?
Solution: (mn/(mn/m + n – 1))/n = 2.286/4 = 0.5715.
Problem 13
What governs the clock cycle frequency of a pipeline system?
Solution: The pipeline with the slowest processing time.
Problem 14
What is needed to maintain performance in a pipeline system, when needed resources
such as hardware are not available?
Solution: More resources can be employed, if available, or the pipeline can be
stalled (e.g., no instructions executed until needed hardware is available).
Problem 15
How many instructions can a nonpipeline computer execute at a time?
Solution: Only one instruction at a time.

Shifting and Comparators

Problem 16
What is the process and purpose of the arithmetic right shift?
Solution: Arithmetic right shifting is performed to divide a quantity by 2n and
round down (“0” inserted in least signiﬁcant bit [LSB] position), where n is
the number of bits shifted. The sign bit is preserved in the right shift.

Problem 17
What is the process and purpose of the arithmetic left shift?
Solution: Multiply a quantity by 2n. The sign bit is lost because the high order
data bit is shifted into the sign position.

Problem 18
What is the process and purpose of the right rotate logical shift and the left rotate
logical shift?
Solution: The right and left rotate logical shifts can be used, for example, to
identify whether database application A or B should be executed dependent
on a series of bits in a register (0 for application A and 1 for application B).
For each shift of one bit, A or B would be selected. See Figure 2 for details
of the four shifting operations, where for each operation, one bit is shifted.

Problem 19
How can a circuit be designed to analyze branch instruction logic in a program?
Solution: Figure 3 shows how a comparator and its accompanying shift control
logic can be designed to determine whether data originally in registers A and
B, and then transferred to busses A and B, have the relationships A = B,


Right Arithmetic Shift lost

0 0 0 0 1 0 1 1 + 11
divide by 2n and round down

0 0 0 0 0 1 0 1 +5

sign bit preserved
n = number of bits shifted
sign bit lost Left Arithmetic Shift

0 0 0 0 1 0 1 0 + 11
multiply by 2n

0 0 0 1 0 1 1 0 + 22

inserted
Right Rotate Logical Shift

0 0 0 0 1 0 1 1

1 0 0 0 0 1 0 1

Left Rotate Logical Shift

0 0 0 0 1 0 1 1

0 0 0 1 0 1 1 0

Figure 2 Shifting operations.

A B, or A B. Thus, in a program, branch 1 would be taken if A = B;
branch 2 would be taken if A B; and branch 3 would be taken if A B.
Problem 20
Figure 4 shows that the hexadecimal quantity 5A has experienced a rotated
left shift of 3 bit positions. What is the resultant quantity in hexadecimal and
decimal?
Solution: As the conversion operation in Figure 4 shows, the result is D2 in
hexadecimal and 210 decimal.

A Bus A=B
Comparator
B Bus AB
AB

B Register A Register
A Q1 A Q1

D Q4 D Q4 Shift
Control

ENB ENB

Figure 3 Comparator circuit.

5 A

Original
0 1 0 1 1 0 1 0

Rotate 3 Bit Positions Left
1 1 0 1 0 0 1 0

D 2

D216 (13 * 16) + 2 = 208 + 2 = 21010
Figure 4 Rotate left shift operation.

Outputs
___ ___ ___
A BC
___ ___
___ ___ ___ ___
A BC A B CP A BCP
___ ___ Odd Parity (P)
A B C
A ___ =1
A BC Generator ___ ___
3-to-8 ___ ___
ABC A B CP AB C P
B Decoder ___
ABC
___
C AB C
ABC ___ ___ ___ ___ ___ ___

Inputs A BCP ABC P
Odd Parity (P)
=0
Generator ___ ___ ___
23 (inputs) = 8 outputs ABCP ABC P
Figure 5 Decoder circuit.

474


Table 2 Decoder Circuit Parity Generation

A B C P
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0

Decoders

A decoder is a combinational circuit that selects one of n inputs and produces 2n
outputs, where n is the number of input bits, as shown in Figure 5.
Problem 21
Given: Decoder circuit in Figure 5, showing selected n inputs and 2n outputs,
with an odd parity generator that signifies no error, if the number of output
bits, including the parity bit, is odd.
Problem: How many outputs are required to address the inputs A, B, C in the
decoder circuit?
Solution: Figure 5 shows that when there are three inputs to the decoder, eight
outputs are required. In addition, Table 2 shows the parity that is required to
ensure no error for the various input combinations.

Flip-Flop Circuits

J-K flip-flop next state output Q(t + 1) is a function of inputs J and K, and present
state flip-flop outputs Q(t) and Q(t ):

Q(t + 1) = JQ(t ) + KQ(t )

Problem 22
Given: Figure 6 shows a J-K flip-flop circuit that includes six gates. The current
flip-flop state Q1Q2Q3 = 100.
Problem:
(a) Identify the types of gates.
Solution: EXCLUSIVE OR: Gates 1 and 3; NAND: Gates 2, 4, and 6; EXCLU-
SIVE OR: Gate 5.


Gate 2
Gate 1
A ____ ___ ___
AB = A + B
_______ ___ ___

A A +B = A B
B
B
Q2 (t + 1)
Q1 (t + 1) J2 Q2
J1 Q1
__________ __________
Gate 3 ___ Q1 (t +1) Q 2 (t + 1)
K1 Q1 K2 ___

C Q2

______ ___ ___ Gate 4
D C+D = C D
Q3 (t + 1)
J3 Q3
____ ___ ___
__________
CD = C + D Q3 (t +1)
Gate 5 ___
E ___ ___ K3 Q3
E F+ E F

F Gate 6
___ ___
E F

Figure 6 J-K flip-flop circuit.

Problem:
(b) Determine the output of each gate.
Solution: See Figure 6.
Problem:
(c) Determine the next state of the flip-flop outputs.
Solution:

Q1 (t + 1) = J1 Q1 (t ) + K1Q(t ) = (AB)(0) + (C + D)(1) = C + D
Q 2 (t + 1) = J 2 Q 2 (t ) + K 2 Q 2 (t ) = (A + B)(1) + (CD)(0) = A + B
Q 3 (t + 1) = J 3 Q 3 (t ) + K 3 Q3 (t ) = (EF + EF )(1) + (E + F )(0) = EF + EF

Multiplexers

The multiplexer circuit in Figure 7 produces a single output Y for four inputs, x0,
x1, x2, and x3, depending on the values of the selector bits, s0, s1, using an OR output
function.
Problem 23
Develop the output functions for the multiplexer circuit in Figure 7.
Solution: Figure 7 shows the output function.


Multiplexer Circuit
Selector
___
s0
s0
Input ___ ___
x0
s 0 s1 x 0
Selector ___

s1
s1
___
s 0 s1x1
Output
x1
___ ___ ___ ___ ___
s0 s1 x 2 Y = s0 s1 x 0 + s 0 s1x1 + s 0 s1 x 2 + s 0s1x 3
Input
x2

s0s1x3

Input
x3
Demultiplexer Circuit

Selector Outputs
s0 ___ ___
Y0 = s 0 s1 x
Input
x
Selector
s1

___
Y1 = s 0 s1x

___
Y2 = s 0 s1 x

Y3 = s0s1x

Figure 7 Multiplexer and demultiplexer circuits.

Demultiplexers

A demultiplexer causes an input x to be transferred to one of 2n output lines, where
n is the number of select inputs in Figure 7.
Problem 24
Develop the output functions for the demultiplexer circuit in Figure 7.
Solution: Figure 7 shows the output functions.
Timing Relationships
Problem 25
Given: Timing relationships pertaining to D ﬂip-ﬂops in Figure 8.
Problem: What is the timing diagram for input signals A and M and what is the
value of the output?


A
Input A
D Q AB
D Q

5 Mhz B

10 Mhz Clock

Input B 10 Mhz

10 Mhz Clock

Input A
5 Mhz

10 Mhz
Input B

5 Mhz

Output AB
Figure 8 Timing relationships.

Solution: Figure 8 shows that by virtue of ANDing inputs A and B, the
output = AB. The timing diagram shows that output AB has a frequency of
5 MHz governed by the durations of the 10 MHz clock when both inputs A
and B are positive.

Programmable Logic Array (PLA)

A PLA consists of programmable AND and OR gates. It can be programmed to
implement a Boolean sum of product terms.
Problem 26
Draw a logic diagram showing how the PLA should be designed to implement the
functions Z 2 = AB + BC, Z1 = AB + AC, and Z 0 = AC + BC.
Solution: The design is shown in Figure 9.


Internal Structure of PLA

A
AND Gate
Inputs B Array
C

Z2
OR Gate Z1 Outputs
Array
Z0

___
A
A

___
B
B

___
C AND Array
C
___ ___ OR Array
AB

___ ___
Z2 = A B + BC
___ ___
AC

___ ___
BC Z1 = A B + AC

AC

___ ___
Z0 = A C + BC

Figure 9 Programmable logic array.

State Machine Diagrams

As Figure 10 shows, state transition diagrams are useful for tracking state transitions
in a digital system. For example, in Figure 10, state transitions are triggered by switch
openings and closings, which cause transitions from present states to next states.


State Transition Condition
SW = 0 SW = 0

SW = 1
Switch State 0 State 1

SW = 1 SW = 1
SW = 0

SW = 1
SW = 0
State 3 State 2

SW: switch = 0, closed, switch = 1 open
Figure 10 Switch state diagram. SW, switch. SW = 0, closed; SW = 1, open.

Table 3 Switch State Transition Table

Present switch condition Present state State transition condition Next state

SW = 0 0 SW = 0 0
SW = 0 0 SW = 1 1
SW = 1 1 SW = 0 1
SW = 0 1 SW = 1 2
SW = 1 2 SW = 1 2
SW = 1 2 SW = 0 3
SW = 0 3 SW = 0 3
SW = 0 3 SW = 1 0

Problem 27
Develop the state transition table corresponding to Figure 10.
Solution: See Table 3.

Edge-Triggered D Flip-Flop Circuit

The output state Q(t + 1) of a D flip-flop is governed by the falling edge of the clock
pulse in Figure 11: Q(t + 1) = D on the falling edge.
Problem 28
Given the characteristic of the D flip-flop, draw the timing diagram for the circuit
in Figure 11.


M Q1 (t + 1) = M N Q2 (t + 1) = N
D1 Q (t) = 0 D2 Q2(t) = 0
1

__________ ___
_________ ___ ______ Q 2 (t +1) = N
___
Q1 (t + 1) = M Q 2 (t) = 1
Q1 (t) = 1

Clock

Clock

Q1 (t + 1) = M Triggered on falling edge

_________ ___
Q1 (t + 1) = M

Q2 (t + 1) = N

__________ ___
Q 2 (t +1) = N

Figure 11 Edge-triggered flip-flop circuit.

State Machine Design

The design of state machines involves identifying states, state transitions, and the
sequences of state transitions, where a sequence is the order in which transitions
occur.
Problem 29
For the elevator example in Figure 12, identify the correct sequence of state
transitions.
Solution: As seen in Figure 12 and based on the logic of elevator operations,
the correct sequence is: (current floor (Nc) → request floor (Nr) → destina-
tion floor (Nd)) or (request floor (Nr) → destination floor (Nd)).
Problem 30
In Figure 12, what are the next states for current state 3 and what are the correspond-
ing state transitions?
Solution: Referring to Figure 12, the next state 3 is caused by elevator staying
at Nd1; the next state 4 is caused by elevator going to Nr2.


Elevator stays at Nc1

START Elevator at Nr1
go to Nr1
Elevator at Nc1
State 1 State 2
go to Nd1
Elevator stays at Nd1
go to Nr2
go to Nd3 Elevator at Nd1
State 3

Elevator at Nd3 State 5 go to Nr2
State 4
go to Nd3
Elevator at Nr2

Elevator stays at Nd3 Elevator stays at Nr2
FINISH
Figure 12 State machine example. Nc, current floor; Nr, request floor; Nd, destination floor.
Numbers designate specific floor.

Problem 31
In Figure 12, give an example of an illegal state transition.
Solution: State 2 → State 4 is illegal because it would be illogical to transition
from one request floor to another request floor without first going to a des-
tination floor.

CHAPTER 9 (PROGRAMMING LANGUAGES) AND
CHAPTER 10 (OPERATING SYSTEMS)

Queue Data Structure

One approach for managing data and instructions is the queue that uses a first-in,
first-out discipline. An application is the processing by a microprocessor, on a non-
priority basis, of a stream of inputs.
Problem 32
For an input of KJIHGFEDCBA, what is the output order for a first-in, first-out
discipline?
Solution: Figure 13 shows the output ordering of the input data.

Stack Data Structure

Another one of the important software design approaches is to use the push-down
stack, which is particularly valuable when interrupts occur and it is necessary to
service the interrupts and later return to the main program. The stack facilitates this
process by pushing the contents of the program counter and special registers onto a


KJIHGFEDCBA
First-in, first-out

K J I H G F E D C B A

Inputs
Computer
Queue Outputs

Queue Processing

Inputs

ABCDEFGHIJK A
B Outputs
Push down data on stack Computer
C
Last-in, first-out
D
E
F
G
H
I
J
K

Stack
Stack Processing
Figure 13 Queue and stack processing.

memory area called the stack. The stack operates on a last-in, ﬁrst-out basis, meaning
that the register contents that were last pushed are on the top of the stack, for
example, the program counter, so that the program is pointing to the address of the
next instruction to be executed.
Problem 33
For an input of ABCDEFGHIJK, what is the output order for a last-in, ﬁrst-out
discipline?
Solution: Figure 13 shows the output ordering of the input data.

Instructions Designed to Perform Functions

Instruction sequences can be designed to perform certain functions such as generat-
ing a square wave in a register, using a set of binary bits to represent the output (i.e.,
square wave), or generating a Fibonacci number sequence.
Problem 34
Show how a square wave can be generated, using an accumulator, input register A,
and output register B.
Solution: See Figure 14 for the result.


Clear
Accumulator

0 0 0 0 0 0 0 0 Accumulator

NOT
Accumulator

1 1 1 1 1 1 1 1

Logical Right Shift
Accumulator 2 Bits

0 0 1 1 1 1 1 1

0 0 0 0 0 0 1 1 Input Register A

Subtract Register A from Accumulator

0 0 1 1 1 1 0 0 Accumulator

Transfer Accumulator to Register B

0 0 1 1 1 1 0 0 Output Register B

Output Square Wave

Figure 14 Square wave generation.

Problem 35
Produce a program to compute Fibonacci numbers, where a Fibonacci number is
defined as the sum of the previous two numbers, for example, 1, 1, 2, 3, 5, 8, and 13.
Solution: Table 4 shows the program.

Software Specifications

Problem 36
What must software specifications contain to be complete?
Solution: There must be details of expected inputs and outputs, details of pro-
cessing requirements, and details of design requirements.


Table 4 Fibonacci Number Program

Command Description

i=0 Set first Fibonacci number index
n(i), n(i + 1) = 1 Set first two Fibonacci numbers = 1
While (i N) do Functions F and C Keep inputting and computing while i N
Fibonacci numbers
Function F (input n(i)) Input Fibonacci number = n(i)
Function C (n(i) + n(i + 1)) Compute Fibonacci number
Function C (n(i) + n(i + 1)) → output Output Fibonacci number
i=i+1 Increment Fibonacci number index
Return (While) Continue with Functions F and C

Passenger 1
Use Case
1. Request up elevator
2. Request floor 8

3. Queue passenger 1 request if queue 0; if queue =0, go to floor 8
7. Door opens

Elevator
System
4. Request down elevator
5. Request floor 1

8. Door opens Collaborative Diagram
6. Queue passenger 2 request if queue 0; if queue = 0, go to floor 1

Use Case Passenger Class Elevator Class
Passenger 1 Object Floor 1 Object
Passenger 2
Passenger 2 Object Floor 8 Object
Class Diagram
Figure 15 Object-oriented conceptual model.

Problem 37
The object-oriented design process involves specifying a conceptual model, which
consists of actors, uses cases, classes, objects comprising a class, and operations.
With this definition in mind, draw the design process for an elevator example.
Solution: The object-oriented design process is shown in Figure 15.


Passenger Floor Input
Elevator Request
Module

Floor Requests

Elevator
System
Module

Floor Requests Parameters
(floor locations)
Queue
Analysis
Module

Floor Travel Operations
(travel direction
floor locations)

Floor
Module

Outputs (arrive at desired floors)
Figure 16 Structured design diagram.

Structure Chart

Problem 38
For a structure chart, we need to know: (1) all the modules in the chart, (2) all the
data items in the chart, (3) the organization of the modules, and (4) all the com-
munications among modules.
Using this concept, design a structure chart for the elevator system depicted in
Figure 15.
Solution: The structure chart design is shown in Figure 16.

CHAPTER 11: SOFTWARE RELIABILITY AND SAFETY

Quality Assurance

Integration Testing
Integration testing can be accomplished either in a top-down or bottom-up fashion.
In bottom-up testing, drivers are required for modules at a higher level to call


modules at a lower level, and test cases are required for doing integrated testing
between modules at higher and lower levels. A disadvantage of bottom-up testing is
that the most important modules—those at the top level—are not tested first. On the
other hand, top-down testing is more complex. For this type of testing, stubs are
required that simulate the lower level module data and instructions, which have not
yet been tested, for the benefit of higher level modules.
Problem 39
Design top-down and bottom-up testing schemes for modules A, B, C, D, and E.
Solution: The testing schemes are shown in Figure 17. These types of tests assist
in the verification process that is aimed at assuring that the testing schemes
are faithful to the software design. In addition, these tests are augmented by
inspections, which are a peer review process for examining code to help
assure its correctness.

Array and Matrices
Arrays are one-dimensional data structures with values and indices that point to the
values, such as the adjacency list in Figure 18. Matrices are two-dimensional data
structures that have two sets of indices, one to point to values in one of the dimen-
sions, and another set to point to values in the second dimension. An adjacency list
can be used for this purpose.
Some problems involving arrays and matrices are concerned with efficient
processing when the matrix is sparse (i.e., many zero elements in matrix). In this
case, an adjacency list (pointers to nonzero elements) combined with a linked list
can be used. For an n × n matrix with zero elements, the number of nonzero elements
that would make the link list superior to a matrix can be computed.
Problem 40
Portray the two data structure alternatives, described above, and compute the storage
requirement for the two alternatives.
Solution: Figure 18 shows the logic of the alternatives and the computation of
the competing storage requirements.
Problem 41
Using the result obtained in Problem 39, compute the number of zero entries Z and
the number of nonzero entries N.
Solution:
Matrix storage requirement (matrix plus pointers): 32n2 + 32n
Link list storage requirement (linked list plus pointers): 32n + 64(n2 – Z)
32 n 2 + 32 n = 32 n + 64(n 2 − Z), 64 Z = 32 n 2,
zero entries Z = 0.5n2, N = n2 – 0.5 n2 = 0.5 n2
In other words, for this problem, the number of nonzero entries equals the
number of zero entries. If Z were larger, the linked list would require less storage
than the matrix.


Test Cases for Test
Modules A, B, A,B,C,D, Module A
C, D, E, F, G E,F, G
Driver for Module D
Driver for Module C Test Cases for
Driver for Module B
Modules D, G

Test Cases for Test
Test Test C
Modules B, E, M odul e B M od u l e C D, G M o du l e D
B, E, F
F

Driver for Module F
Driver for Module G
Driver fo Module E

Test G Module G
Test E Module E Test F Module F

Bottom-Up Testing

Test Case for
Module A
Test A Module A

Stub for Testing A with D
Stub for Testing A with B
Stub for Testing A with C

Test Test Test
Module B Module C M o du l e D
A, B A, C A, D

Stub for Testing A, B, E Stub for Testing A, C, F Stub for Testing A, D, G

Test Test Test
Module E Module F Module G
A, B, E A, C, F A, D, G

Stub for Testing A, C, F

Stub for Testing A, D, G
Stub for Testing A, B, E
Test
A,B,C, D,
E,F,G

Top-Down Testing

Figure 17 Integrated testing designs.


n × n matrix (32-bit elements) adjacency list (pointers to nonzero elements)
linked list (64-bit elements)

nonzero element 1
1
32-bit pointer only nonzero elements
32-bit pointer
0 zero element
n2 – Z nonzero elements

32(n2 + n) bits storage requirement 32n + 64(n2 – Z) bits storage
requirement

n entries
array
Figure 18 Array and matrix data structure design. Z, number of zero elements.

Nested Program Logic
The number of paths (i.e. number of program executions or number of calls) in a
nested program can be determined by drawing a ﬂow chart, as shown in Figure 19.

Problem 42
Based on Figure 19, what is the formula for computing the number of paths?

CHAPTER 6: NETWORK SYSTEMS

Network Diameter

The network diameter is the maximum of the distances between all possible pairs
of nodes (e.g., computers) of a graph of a network, without backtracking (i.e., revisit-
ing a node on a path). This concept is used for identifying the maximum distance
data would have to travel in a network. The appropriate bandwidth would be pro-
grammed to meet this requirement.

Problem 43
Given: Figure 20 showing network connections.
Determine the network diameter.
Solution: The various paths, links, and maximum number of links are shown in
Table 5, based on the network topology in Figure 20, yielding diameter = 4
links (A → E → B → C → D).


i=0
j=0

For i = 1 to
ni

For j = 1 to
nj

Compute
Function
A(i)

Compute
Function
B(j)

i=i+1

j=j+1

Number of Paths = ni, nj
Figure 19 Flow chart problem.


Paths:
A, B
A, E, B
Link A → B Link B → C
A, B, C Node A Node B Node C
A, E, B, C
A, E, D, C Link A → E
A, B, C, D
A, E, B, C , D Link B δ E Link D → C
A, E, D Link C → D
Link E → B
A, E
A, B, C, D, E
A, B, E Link E → D
Node E Node D
B, C
B, E Link D → E
B, C, D, E
B, E, D
B, C, D
C, D
C, D, E
C, D, E, B
D, E
D, E, B
D, E, B, C
E, B
E, B, C
E, B, C, D
E, D
Figure 20 Network connectivity.

Problem 44
What series of instruction functions will generate a square wave with a 50% duty
cycle to control the output of data on a network? Show the instructions and their
functions and the results of the instruction functions executions.
Solution: Table 6 shows the instruction functions and Table 7 shows the results
of the instruction functions executions.

Analog-to-Digital Conversion to Support Network
Operations

Problem 45
Given: Analog-to-digital converter network support circuit diagram in Figure
21.
What address is used to access network Channel B of the converter?
Solution: The circuit diagram shows how the address bits (01000000) are con-
ﬁgured to support the access of network Channel B at address 4016.


Table 5 Network Connectivity

Path Links Number of links

A→B A→B 1
A→E→B A → E, E → B 2
A→B→C A → B, B → C 2
A→E→B→C A → E, E → B, B → C 3
A→E→D→C A → E, E → D, D → C 3
A→B→C→D A → B, B → C, C → D 3
A→E→B→C→D A → E, E → B, B → C, C → D 4
A→E→D A → E, E → D 2
A→E A→E 1
A→B→C→D→E A → B, B → C, C → D, D → E 4
A→B→E A → B, B → E 2
B→C B→C 1
B→E B→E 1
B→C→D→E B → C, C → D, D → E 3
B→E→D B → E, E → D 2
B→C→D B → C, C → D 2
C→D C→D 1
C→D→E C → D, D → E 2
C→D→E→B C → D, D → E, E → B 3
D→E D→E 1
D→E→B D → E, E → B 2
D→E→B→C D → E, E → B, B → C 3
E→B E→B 1
E→B→C E → B, B → C 2
E→B→C→D E → B, B → C, C → D 3
E→D E→D 1

Hubs versus Switches

Problem 46
Figure 22 demonstrates that compared with hubs, switches increase bandwidth
(no collisions) and security (memory of switches provides security checking). Why
is this the case?
Solution: Because collisions are possible using hubs but not possible using
switches.

Connection Hijacking

Transmission Control Protocol (TCP) session hijacking occurs when a hacker
takes over a TCP session during a session between two computers. Since most


Table 6 Instruction Functions

Instruction Function

CLR (clear accumulator) 0 → ACC
IN B (transfer “1” from input device to 1→B
register B)
ADD (add register B = 1 to accumulator) ACC = ACC + B
SHR (shift accumulator logical right 4 bits) ACC [7:4] → ACC [3:0], 0 → ACC [7:4]
SHL (shift accumulator logical lift 2 bits) ACC [7:2] ← ACC [5:0], ACC [1:0] ← 0
OUT (out put accumulator to register C) ACC → C

Table 7 Square Wave Instruction Function Execution Results

Instruction Instruction result Square wave result

CLR (clear accumulator) 0 → ACC
IN B (transfer “1” from 1→B
input device to
register B)
ADD (add register ACC = ACC + B
B = 1 to accumulator)
SHR (shift accumulator ACC [7:0] → ACC [3:0],
logical right 4 bits) 0 → ACC [7:4]
SHL (shift accumulator ACC [7:2] ← ACC [5:0],
logical lift 2 bits) ACC [1:0] ← 0
OUT (out put ACC → C
accumulator to
register C)

2n = 8, n = 3
Analog-to-digital converter
Address: A11,...,A0 3 to 8 decoder
A11 = 0 Address
S0
A10 = 1 D0 B0 = 0
S1
A9 = 0 D1 B1 = 0 Channel A
Computer S2 D2 = 1
D2 B2 = 0
Select
D3 Select B3 = 0
Generated address = 4016
D4 B4 = 0
D5 B5 = 0 Channel B
D6 B6 = 1

D7 B7 = 0
___
A / B select = 0
A8
Figure 21 Analog-to-digital converter circuit.


Collisions possible
Hub Router Hub

Computer E Computer F Computer A Computer C

Computer H Computer D
Server Computer B
Computer G
Router
Computer G Switch Computer C
Switch

Computer H Computer D

Computer A
Computer E
Computer B
Computer F

Server
Collisions not possible
Increase in bandwidth
Security improved because switch has memory for checking validity of data
Figure 22 Hubs versus switches.

authentications only occur at the start of a TCP session, this allows the hacker to
gain access to a computer. A popular hacking method uses source-routed Internet
Protocol (IP) packets. Source-routed packets identify the source address in the
packet. A hacker at node A listens for packets originating at nodes B or C. If such
trafﬁc passes through node A, it allows the hacker to participate in a conversation
between B and C. This is known as a “man-in-the-middle attack.” A common com-
ponent of such an attack is to execute a denial-of-service (DoS) attack against nodes
B and C.
Problem 47
Draw an Internet diagram depicting the connectivity that would permit the security
breaches described above.
Solution: Figure 23 shows the Internet vulnerabilities that would allow security
problems to occur.


Hacker
A

Source Routed Source Routed
IP Packets IP Packets
B C
TCP TCP
IP TCP Session IP
Data Link Data Link
Physical Physical

Ethernet Internet
Ethernet
Router
HEWL ET T
PACK ARD
Router
HEWL ETT
P ACKA RD

Figure 23 Internet connections.

RS 232 C Data Transmission

Coding efficiency is defined as the (number of data bits)/total number of bits (data
plus control).
Problem 48
Referencing the figure below, what is the coding efficiency?
Solution: As can be seen in the figure, there are 8 data bits out of a total of 11
bits. Therefore, coding efficiency = 8/11 = 73%.

2 stop bits 8 data bits start bit

Topology and Hardware

Various combinations of network topology and hardware are shown in Figure 24.
The main characteristic of 10 Base T Ethernet is that each computer is individually
connected to a hub. The hub has no storage; therefore, data cannot be buffered.
This scheme does have an advantage over the bus because, with each computer
having its own connection to the hub, collisions of data on the network are avoided.
Because the bus is shared by many devices, collisions on the connected Ethernets
are unavoidable. However, the bus is the traditional way to connect Ethernets
because this type of connection is highly standardized and economical. A later
version of Ethernet uses switches to direct traffic. This configuration avoids
collisions.


10 Base T

No collisions: dedicated
connections

Hub

Ethernet Light traffic Ethernet

Heavy traffic Bridge Heavy traffic

No collisions: dedicated
connections
Heavy traffic Heavy traffic Heavy traffic

Ethernet
No collisions: dedicated Ethernet
connections
Switched Ethernet

Switch

Collisions possible: no dedicated connections

Ethernet Ethernet

Repeater Bus Repeater

Figure 24 Network connectivity alternatives.

The most rudimentary connectivity device is the repeater. Its function is to
repeat a signal, necessitated by the fact that signals can lose strength in traversing
a network. The bridge has storage and routing capability that allows it to transfer
traffic from one network to another. The primary application of the bridge is where
most of the traffic is within the connected networks, with occasional traffic between
networks.


Problem 49
In Figure 24, indicate whether collisions will or will not occur for the various con-
nection methods.
Solution: See annotations on Figure 24.

Adjacency Matrix in Network Topology

Deﬁnition: An adjacency matrix is a means of representing which vertices of a
network topology graph are adjacent (i.e., directly connected by edges).
Problem 50
Given: Graph of vertices Vi below.
What is the adjacency matrix of vertices Vi and edges ei?

V1 e1 V2

e4 e5 e2

V4 e3 V3

Solution: Using the above deﬁnition, the adjacency matrix is shown in Table 8,
where “1” indicates a connection:

Data Compression

Data compression is used to economize on data transmission or computation by
eliminating bits that are not required in an application. For example, rather than use
the hexadecimal format for the input number 16 in a computation, the binary repre-
sentation is used. Thus, rather than 8 bits in hexadecimal, 5 bits in binary are used
in the computation.

Table 8 Adjacency Matrix for Vertices Vi and Edges ei

V1 V2 V3 V4

V1 0 1(e1) 0 1(e4)
V2 1(e1) 0 1(e2) 1(e5)
V3 0 1(e2) 0 1(e3)
V4 1(e4) 1(e5) 1(e3) 0


Using data transmission to illustrate the decompression technique, the time required
to transmit x bits of data in the noncompressed mode = x/Bn, where Bn is the bandwidth
in bits per second (bps) for uncompressed data. With a compression factor r ≥ 1, data
will be compressed by x/r. The time that it takes to compress and decompress x bits of
data is x/Bc, where Bc is the rate of compression/decompression. Thus, the time to com-
press, transmit, and decompress x bits of data is (x/Bc) + ((x/r)/Bn). Then, compassion/
decompression is beneﬁcial if the (time to compress, transmit, and decompress x bits of
data) (time required to transmit x bits of data in the noncompressed mode):
(x/Bc ) + ((x/r ) /Bn ) (x/Bn ), which is equivalent to Bc ((r/ ( r −1)Bn ).
1

Problem 51
What is the value of the above inequality for r = 2?
Solution: Bc 2 Bn (rate of compression/decompression (2 bandwidth in bps
for uncompressed data)).

Network Channel Capacity

Deﬁnitions
C: Channel capacity (bps) (Shannon’s theorem)
BW: Bandwidth (hertz, Hz, or megahertz, MHz)
S: Signal power (watts)
N: Noise power (watts)
No: Noise spectral density (watts/Hz or MHz)
P0: Power in system 0 (watts)
P1: Power in system 1 (watts)
G: Gain or loss between P0 and P1 or between S and N (decibels)

⎛ ⎛ S ⎞⎞
C = BW ⎜ log2 ⎜ 1 + ⎟ ⎟
⎝ ⎝ N ⎠⎠

Shannon Limit

C = 1.44(S/N 0 )
⎛P ⎞
G = 10 log10 ⎜ 1 ⎟
⎝ P0 ⎠

P1 = (10)G / 10 P0
S / N = (10)G / 10
Problem 52
Given: Network channel capacity C = 22.368 bps, signal power S = 14 watts,
noise power N = 2 watts.


What is the required bandwidth BW of the network channel?
Solution:

C 22.368 22.368 22.368
BW = = = = = 7.456 Hz
⎛ 1 + S ⎞ log ⎛ 1 + 14 ⎞ log2 (8)
log2 ⎜
3
⎝ N⎟ ⎠ 2⎜
⎝ 2⎠
⎟

Problem 53
Given: A microwave link is used to transmit binary data and has the following
specifications: transmission bandwidth BW = 24 MHz, received signal-to-
noise ratio = G = 20 dB.
According to Shannon’s theorem, what is the network channel capacity C in mega-
bits per second?
Solution:

⎛ ⎛ S ⎞⎞
C = BW ⎜ log2 ⎜ 1 + ⎟ ⎟ , S / N = (10)G / 10 = (10)20 / 10 = 100
⎝ ⎝ N⎠⎠
C = 24(log 2 (1 + 100)) = 24 MHz × (log10 (101) / log10 (2))
= 2.004 / 0.3010 = 159.80 Mbit / s

Computer Circuit Analysis

Bode Plot and Amplifiers
A Bode plot relates the absolute value of the transfer function (|output/input|) = |V2/
V1| in Figure 25 to ω = 2πf, where f = signal frequency, for example, an audio circuit
that amplifies sound in a laptop computer.
Problem 54
Given: Amplifier diagram in Figure 25.
Problem: Identify the transfer function. Plot the transfer function versus ω.
Solution: Figure 25 shows the computation of the transfer function, according
to the above definition. In addition, the figure shows the Bode plot, whose
shape is governed by the fact that V2/V1 = 1/ωCR is an inverse function of
ω = 2πf. Thus, V2/V1 will continually decrease with f, and the 0 dB point
corresponds to ωc = 1/RC, where V2/V1 = 1.

Operational Amplifier

This is a direct-current circuit amplifier that can be used to, for example, boost the
signal derived from a sensor to a value that can be used in computer processing.
Problem 55
This problem, portrayed in Figure 26, involves determining the operational amplifier
output voltage, Vo, given the temperature sensor input voltage Vs and the various


1
C Z2 =
Z1 = R jωC
+

Amplifier
I + | V2 | IZ2 1
V1 I = =
| V1 | IZ1 ωCR
V2
_
| V2 | 1 V
= 1 for ωc = = 2
_ | V1 | CR V1

V2
V1
| V2 |
=1
| V1 |
0 dB

ωc ω
Bode plot
Figure 25 Ampliﬁer diagram and Bode plot.

Rs R1

Temperature
sensor
3000 ohms
2000 ohms
Vs I2
I1

Operational
amplifier

Vo
I3
R2

1000 ohms Computer processing
of Vo

Figure 26 Operational ampliﬁer circuit.

resistor values. Develop equations for impedance of total circuit, voltages, and cur-
rents, using Figure 26 as a guide.
Solution:
Impedance of total circuit, Z1, comprised of series and parallel resistance
circuits:


⎛ RR ⎞
Z1 = (R s ) + ⎜ 1 2 ⎟ ,
⎝ R1 + R 2 ⎠

then, the current I1 is computed as:

⎡ RR ⎤
I1 = Vs / ⎢( R s ) + 1 2 ⎥ .
⎣ R1 + R 2 ⎦

The current I2 is computed by dividing the voltage across it by its resistance:

Vs − Vo
I2 = ,
R1

additionally, I3 = I1 – I2, thus:

⎛ V − Vo ⎞
I3 = I1 − ⎜ s
⎝ R1 ⎟
.
⎠

The output voltage Vo is across the resistor R3 in Figure 26:

⎡ V − Vo ⎤
Vo = I3 R 2 = ⎢ I1 − s R 2,
⎣ R1 ⎥⎦

then substituting I1 in this equation produces:

⎡ ⎛ R R ⎞ ⎛ V − Vo ⎞ ⎤
Vo = Vs / ⎢( R s ) + ⎜ 1 2 ⎟ − ⎜ s
⎝ R1 + R 2 ⎠ ⎝ R1 ⎟ ⎥ 2
R.
⎣ ⎠⎦

The ampliﬁcation factor, Vo/Vs, in Figure 26, is computed, using the foregoing equa-
tion, as follows:

( R1 + R 2 ) R1 R2
Vo / Vs = −
(R1 − R 2 )[(R s )(R1 + R 2 ) + R1 R 2 ] (R1 − R 2 )
(3000 + 1000)* 3000
0 1000
= −
(3000 − 1000)[(2000)(3000 + 1000) + 3000 * 1000] (3000 − 1000)
12, 000, 000
= − 0.5000
(2000)[(2000)(4000) + 3, 000, 000]
12, 000, 000
= − 0.5 = 0.5454 − 0.5000 = 0.0454.
22, 000, 000

The interpretation of this result is that 1°C measured by the temperature sensor cor-
responds to Vs = 1 V on input, increased by the operational ampliﬁer to 0.0454 V
on output.


____ ____
D1(t) = X1 (t) Q1(t + 1) = X1 (t) D2(t) = X2(t) Q2 (t + 1) = X2(t)
____
Q1(t) = X1 (t) Q2(t) = X1(t)
________

_____
Q1 (t +1)= X1(t) ___ ____
Q1 (t) = X1(t) Q 2 (t) = X1 (t) ___ ____
Q 2 (t +1) = X 2 (t)

CLK

800 Hz motors generate 400 Hz flip-flop signals
X1(t)

X2(t)

Figure 27 Motor circuit.

Table 9 D Flip-Flop Truth Table

D1 (t ) = Q1 (t ) = Q1 (t + 1) Q1 (t + 1) D2(t) = Q2(t) = Q2(t + 1) Q 2 (t + 1)
X1(t) X2(t) X1 (t ) X1 (t ) = X1 (t ) = X1 (t ) X2(t) X1(t) = X2(t) = X 2 (t )

0 0 1 1 1 0 0 0 0 1
0 1 1 1 1 0 1 0 1 0
1 0 0 0 0 1 0 1 0 1
1 1 0 0 0 1 1 1 1 0

Problem 56
It is required to determine the clock frequency in Figure 27, given that the output
frequency for the motors is 400 Hz.
Solution: Using the truth table in Table 9, it can be seen that the ﬂip-ﬂop next
state outputs Q1 (t + 1) and Q2 (t + 1), which are connected to the motors,
change state only when the motor variables change (X1 = 0 → 1 and
X2 = 1 → 0), indicated by the bolded items, requiring two clock pulses.
Therefore, the input clock frequency = 800 Hz, as shown in Figure 27.

Shifting Circuits

Problem 57
Given: Arithmetic right shifting circuit in Figure 28, where the initial value of
D2D1D0 = 001.


Right shift

0 0 1 Initial state

D2 D1 D0

D2 = D1 XOR D0

Figure 28 Right shift operation.

Table 10 Shifting Circuit Truth Table
Operation D2 D1 D0 D2 = D1 + D0
Initial state 0 0 1
D2 = D1 + D0 1 0 1 1
Right shift 0 (insert 0) 1 0
D2 = D1 + D0 1 1 0 1
Right shift 0 (insert 0) 1 1
D2 = D1 + D0 0 1 1 0
Right shift, repeated 0 (insert 0) 0 1
state, with Initial state

How many nonrepeating states are required for the counter to complete its cycle?
Solution:
First, notice the XOR (Exclusive OR) logical property: D2 = D1 D0 (D2 = 0,
if D1 and D0 are the same, and D2 = 1, if D1 and D0 are different). Then, referencing
the truth table in Table 10, you can see that the circuit transitions through seven
states when the initial state is repeated at the seventh state.

Oth1

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