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OVERCOMING KEY CHALLENGES OF TODAY'S COMPLEX SOC: PERFORMANCE OPTIMIZATION AND VERIFICATION QUALITY

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Pankaj Singh

The document discusses the challenges and strategies for optimizing performance and verification in complex system-on-chip (SoC) designs, focusing on power management, energy efficiency, and verification methodologies. Key topics include the need for holistic verification approaches, the alignment of hardware and software development schedules, and emerging techniques such as skin temperature-aware power management and battery boost. The authors emphasize the importance of reusing existing verification environments and navigating the evolving landscape of EDA tools and methodologies.

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OVERCOMING KEY CHALLENGES OF TODAY'S COMPLEX SOC: PERFORMANCE OPTIMIZATION AND VERIFICATION QUALITY PANKAJ SINGH, ASHISH JAIN, NARENDRA KAMAT
2| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | OUTLINE POWER MANAGEMENT FOR IMPROVED ENERGY EFFICIENCY AND VERIFICATION CHALLENGES SKIN TEMPERATURE AWARE POWER MANAGEMENT BATTERY BOOST PERFORMANCE ANALYSIS ENVIRONMENT REUSE VERIFICATION ENVIRONMENT SOC VERIFICATION UVM METHODOLOGY & WHAT NEXT. CHALLENGES/GAPS: HW-SW DEBUG, VIRTUAL PROTOTYPE MODEL. EMULATION CONFIGURATION OPTIONS. Power Mgmt for Energy Efficiency & Verification Challenges Performance Analysis Verification Environment SoC Verification Challenges
POWER MANAGEMENT FOR IMPROVED ENERGY EFFICIENCY AND VERIFICATION CHALLENGES Power Mgmt. for Energy Efficiency & Verification Challenges Performance Analysis Verification Environment SoC Verification Challenges: UVM, HW-SW Debug, VP, Emulation
| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 4 POWER MANAGEMENT UNIT * Physical monitors on the chip/platform, or digital estimators based on activity, other parameters Power Monitors Current Monitors Temperature Monitors Monitors* Filters & Comparators > < = Platform Constraints CPU Graphics NorthBridge/ Memory Interface Multimedia APU Power Controllers Operating points for different APU Entities APU activity, power, thermal inputs PLATFORM INFRASTRUCTURE CONSTRAINTS Platform Component Constraint Cooling solution/Heat sink Heat dissipation ability to maintain die & system temperature AC Brick Power/Current carrying capability Battery pack Power/Current carrying capability Voltage Regulators/FETs on the board Current carrying capability, thermals
| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 5 MUCH MORE CONFIGURABILITY AND FLEXIBILITY APU Power/ Thermal Profile APU Power/ Thermal Profile Platform Power and Thermal Profile Old Paradigm: Adjust platform design to fit the APU’s power/thermal profile APU Power/ Thermal Profile Platform Power and Thermal Profile Platform Power and Thermal Profile New Reality/Challenge: Configure APU to fit the platform’s power/thermal profile
| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 6 DYNAMIC CONFIGURABILITY 2-in-1 Convertibles: Clamshell versus tablet/slate mode Docked versus Undocked Modes System BIOS Platform Events Docked/Undocked, Tablet/Clamshell Mode Changes Power Management Unit Frequency/ Power Limits To match the Config Requirements Parameters Config 1 (Docked) Config 2 (Undocked) Config 3 (…) TDP Limit 18W 12W 15W Surface Temp Limit 50C 42C 45C … … … …
| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 7 SKIN TEMPERATURE AWARE POWER MANAGEMENT Without STAPM With STAPM Without STAPM With STAPM
| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 8 BATTERY BOOST = Increased efficiency Energy use drops While Performance increases Based on 3DMark11 (Performance preset) on 15W quad-code Kabini (KB 15w4c) and 15W quad-code Beema (BM 15w4c) . Pre-production engineering samples of APUs used with 2x8GB DDR3 1866 RAM, 1280x720 display panel, Windows 8.0 and unreleased reference driver
| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 9 VERIFICATION CHALLENGES  Complex interaction among various hardware components and software components require a multi-level verification approach  Software readiness as important and critical for time-to-market as a robust and verified hardware design  Verification environment not only needs to model SOC components but System/Platform components as well IP level verification of basic blocks like the activity monitors SOC level verification of the accumulator and controller logic APU FIRMWARE BIOS DRIVER Software validation using a behavioral level model of the hardware HW-SW cosim and/or Emulation for verification of interfaces between hardware components and software modules
| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 10 VERIFICATION CHALLENGES  Typically software readiness and hardware schedules are mis-aligned ‒ Software development delayed with respect to hardware development to bank on the time between design tapeout and silicon arrival ‒ Puts any software-hardware co-verification at great risk ‒ Alignment of software and hardware schedules a ‘must-have’ requirement for successful execution of current generation power management architecture IP Level Verification SOC Verification HW/SW Co-verification/Emulation Software (BIOS, Driver, Firmware) Verification
PERFORMANCE ANALYSIS ENVIRONMENT Power Mgmt. for Energy Efficiency & Verification Challenges Performance Analysis Verification Environment SoC Verification Challenges: UVM, HW-SW Debug, VP, Emulation
| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 12 SOC PERFORMANCE  Trends: ‒ Chip industry: Lot more disparate client IPs on one chip… ‒ Platform/software use cases: Big Data, HPC, more displays, higher resolution…  Memory is the bottleneck ‒ Interconnect performance is critical to maximize potential of engine IPs  Each client has different general characteristics ‒ CPU: Latency sensitive for single-threaded performance; latency-under- load ‒ GFX: Massively parallel workloads; huge appetite for memory bandwidth ‒ Display and Real-time clients: Burst traffic, with demanding QoS requirements Visual Computing HPC Big Data Evolutionary design System-on- Chip Reuse New Class of Applications: Large Data Sets, Massively Parallel New Class of Constraints: IP Reuse, Large Complex SOCs Memory Subsystem (Interconnect) Performance Applications demand high-performance memory access Larger no# clients demand high performance memory access
| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 13 PERFORMANCE VALIDATION FOR INTERCONNECT IP  Ensure that performance metrics of interest meet the product goals  Metrics: ‒ Peak bandwidth ‒ DRAM utilization efficiency ‒ Unloaded latency for different clients ‒ Loaded latency curve  Use RTL simulation Related approach is to use an abstract performance model.
| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 14 BANDWIDTH MEASUREMENT AT INTERFACE Inbound Data • Record number of bytes moved Outbound Data • Record number of bytes moved LATENCY MEASUREMENT AT INTERFACE Inbound Request • Save tag/timestamp Outbound Response • Match tag • Delta with saved timestamp • Record latency
| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 15 INTERCONNECT IP Interconnect CPU0 CPU1 IO GPU DRAM Chn 1 DRAM Chn 0 Interface points for primary performance measurements - Need low development/maintenance cost - Interfaces not necessarily identical Key challenges - Reuse existing functional verification code - Leverage industry-standard UVM framework - Software engineering approach Approach DESIGN PARAMETERS
| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 16 TRACKER CLASS Simple/minimal code Two types: Bandwidth[B.W] & Latency Data structures to track the selected metric[B.W and latency] One tracker per metric per interface Scoreboard instantiates tracker objects, and invokes track method when transactions are observed
| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 17 PERFORMANCE SCOREBOARDS AT EACH INTERFACE Interconnect CPU0 CPU1 IO GPU DRAM Chn 1 DRAM Chn 0 SB SB SB SB SCOREBOARD FUNCTIONS Callbacks registered with verification monitors for all data transactions (UVM: analysis ports) Master (instantiate) tracker objects When callback received, invoke track method on all trackers.
| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 18 END OF SIMULATION Top-level performance environment module queries each scoreboard for metrics Each scoreboard queries each instantiated tracker for metrics Bottom-up rollup of data, formatted and printed in a file for analysis. Env CPU0 Scoreboard BW Tracker Latency Tracker CPU1 Scoreboard BW Tracker Latency Tracker GPU Scoreboard BW Tracker Latency Tracker IO Scoreboard BW Tracker Latency Tracker
| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 19 ADVANTAGES Minimal new code (low development/maintenance costs) Leverages existing verification testbench infrastructure Exploits recurring measurement patterns Code portable from IP-level to SOC-level UVM (standard) compliant
SOC VERIFICATION CHALLENGES Power Mgmt. for Energy Efficiency & Verification Challenges Performance Analysis Verification Environment SoC Verification Challenges: UVM, HW-SW Debug, VP, Emulation
| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 21 VERIFICATION CHALLENGE : INCREASED COMPLEXITY, INCREASE IN CORES AND REDUCED TIME TO MARKET Baseline Design Design Complexity Power Management Firmware Software Baseline Design Design Complexity Power Management Firmware Software Complexity Time Reduced Design Cycle Increased Complexity Design Cycle 0 5 10 15 20 25 0 20 40 60 80 100 120 140 2006 2011 2014 IPs (left axis) Average IP and Processor Core trends in advanced SoCs Source: Caspi, HVC 2013 IP Cores Embedded Processor Cores Ref: [3]
| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 22 UVM UVM 1.2 Testbench UVM Methodology – A big leap in Verification. What Next? reusable Source : uvm cookbook
| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 23 HW-SW DEBUG  SoC verification involves lot of embedded software  The number of heterogeneous cores are growing ‒ Need for the debug process capability of simultaneously viewing multiple cores both from a HW perspective as well as from programmers point of view  SoC debug need a simultaneous view of both hardware and software ‒ RTL and gate level, including HDL source code, waveform, schematic, assertion, testbench, transaction and power-aware debug ‒ Programmer's view of both C/C++ and assembly code as well as memory, register and breakpoint windows ‒ No standard tool or accepted methodology exist. The debug tool released this year by EDA company’s could evolve and fill the HW-SW gap.
| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 24 VIRTUAL PROTOTYPE MODEL - GAPS  RTL and VP are developed in two parallel streams  VP model used for Architecture exploration, SW development, Reference model for verification. However gaps exist in developing good quality of VP model ‒ Largely the firmware code is applied to verify the VP – may not cover entire VP . No randomization used. ‒ Coverage still largely eludes the VP verification. Tools available in market do not address the coverage topic in a straight forward way especially toggle coverage  Therefore, determining “Are we Done? “ for VP verification poses big gaps
| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 25 EMULATION: WHEN TO USE WHICH CONFIGURATION? Characteristics In-circuit Emulation Embedded Target Emulation Hybrid Virtual/Emulation Why • Connecting real hardware to your design • Real peripheral device testing • Real-world traffic • Enables Save/Restore • Easily re-locatable • Additional debug monitoring • Enables Save/Restore • Easily re-locatable • Capacity savings • Highest performance • Improved software debug When to use • When testing in real environment with real devices is important • When CPU validation is a higher priority • When highest model accuracy is required • When getting deep into workloads is important • When CPU validation is a higher priority • When capacity is available • Need to run large software workloads • When CPU validation is a lower priority • Fast initial bring-up of OS Who • Platform engineering teams • Design teams • Product engineering teams • Platform engineering teams • Design teams • Software teams • GFX driver developers • Platform engineering teams • Design teams Reference: [3] cdnlive ’14 . Alex Starr, Brian Fisk
| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 26 SUMMARY  EFFICIENT POWER MANAGEMENT TECHNIQUES SUCH AS STAPM AND BATTERY BOOST FOR IMPROVED ENERGY EFFICIENCY [PERFORMANCE/WATT]  DEVELOPING PERFORMANCE ANALYSIS ENVIRONMENT BY REUSING EXISTING VERIFICATION ENVIRONMENT  HOLISTIC VIEW OF SOC VERIFICATION : EVOLUTION OF UVM METHDOLOGY, UVM 1.2 AND CHALLENGES WITH MULTI LANGUAGE SUPPORT/AMS SUPPORT. EDA INDUSTRY/TOOL CHALLENGES WITH HW-SW DEBUG, VP MODEL VERIFICATION. H/W ASSISTED SIMULATION ACCELERATION, CHOOSING EMULATION CONFIGURATION FOR YOUR DESIGN. Power Mgmt for Energy Efficiency & Verification Challenges Performance Analysis Verification Environment SoC Verification Challenges
| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 27 THANKYOU
| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 28 REFERENCES 1. Applying AMD's "Kaveri" APU for Heterogeneous Computing. Hot Chips 26 - Palo Alto, CA. Bouvier Dan, Sander Ben 2. UVM CookBook 3. Complementing In-circuit Emulation with Virtualization for Improved Efficiency, Debug Productivity, and Performance. CDNLIVE SI VALLEY 2014. Alex Starr, Brian Fisk 4. Harry Foster, Mentor Graphics. DAC’14
| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 29 DISCLAIMER & ATTRIBUTION The information presented in this document is for informational purposes only and may contain technical inaccuracies, omissions and typographical errors. The information contained herein is subject to change and may be rendered inaccurate for many reasons, including but not limited to product and roadmap changes, component and motherboard version changes, new model and/or product releases, product differences between differing manufacturers, software changes, BIOS flashes, firmware upgrades, or the like. AMD assumes no obligation to update or otherwise correct or revise this information. However, AMD reserves the right to revise this information and to make changes from time to time to the content hereof without obligation of AMD to notify any person of such revisions or changes. AMD MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE CONTENTS HEREOF AND ASSUMES NO RESPONSIBILITY FOR ANY INACCURACIES, ERRORS OR OMISSIONS THAT MAY APPEAR IN THIS INFORMATION. AMD SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. IN NO EVENT WILL AMD BE LIABLE TO ANY PERSON FOR ANY DIRECT, INDIRECT, SPECIAL OR OTHER CONSEQUENTIAL DAMAGES ARISING FROM THE USE OF ANY INFORMATION CONTAINED HEREIN, EVEN IF AMD IS EXPRESSLY ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. ATTRIBUTION © 2014 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD Arrow logo and combinations thereof are trademarks of Advanced Micro Devices, Inc. in the United States and/or other jurisdictions. Other names are for informational purposes only and may be trademarks of their respective owners.

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OVERCOMING KEY CHALLENGES OF TODAY'S COMPLEX SOC: PERFORMANCE OPTIMIZATION AND VERIFICATION QUALITY

  • 1. OVERCOMING KEY CHALLENGES OF TODAY'S COMPLEX SOC: PERFORMANCE OPTIMIZATION AND VERIFICATION QUALITY PANKAJ SINGH, ASHISH JAIN, NARENDRA KAMAT
  • 2. 2| The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | OUTLINE POWER MANAGEMENT FOR IMPROVED ENERGY EFFICIENCY AND VERIFICATION CHALLENGES SKIN TEMPERATURE AWARE POWER MANAGEMENT BATTERY BOOST PERFORMANCE ANALYSIS ENVIRONMENT REUSE VERIFICATION ENVIRONMENT SOC VERIFICATION UVM METHODOLOGY & WHAT NEXT. CHALLENGES/GAPS: HW-SW DEBUG, VIRTUAL PROTOTYPE MODEL. EMULATION CONFIGURATION OPTIONS. Power Mgmt for Energy Efficiency & Verification Challenges Performance Analysis Verification Environment SoC Verification Challenges
  • 3. POWER MANAGEMENT FOR IMPROVED ENERGY EFFICIENCY AND VERIFICATION CHALLENGES Power Mgmt. for Energy Efficiency & Verification Challenges Performance Analysis Verification Environment SoC Verification Challenges: UVM, HW-SW Debug, VP, Emulation
  • 4. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 4 POWER MANAGEMENT UNIT * Physical monitors on the chip/platform, or digital estimators based on activity, other parameters Power Monitors Current Monitors Temperature Monitors Monitors* Filters & Comparators > < = Platform Constraints CPU Graphics NorthBridge/ Memory Interface Multimedia APU Power Controllers Operating points for different APU Entities APU activity, power, thermal inputs PLATFORM INFRASTRUCTURE CONSTRAINTS Platform Component Constraint Cooling solution/Heat sink Heat dissipation ability to maintain die & system temperature AC Brick Power/Current carrying capability Battery pack Power/Current carrying capability Voltage Regulators/FETs on the board Current carrying capability, thermals
  • 5. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 5 MUCH MORE CONFIGURABILITY AND FLEXIBILITY APU Power/ Thermal Profile APU Power/ Thermal Profile Platform Power and Thermal Profile Old Paradigm: Adjust platform design to fit the APU’s power/thermal profile APU Power/ Thermal Profile Platform Power and Thermal Profile Platform Power and Thermal Profile New Reality/Challenge: Configure APU to fit the platform’s power/thermal profile
  • 6. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 6 DYNAMIC CONFIGURABILITY 2-in-1 Convertibles: Clamshell versus tablet/slate mode Docked versus Undocked Modes System BIOS Platform Events Docked/Undocked, Tablet/Clamshell Mode Changes Power Management Unit Frequency/ Power Limits To match the Config Requirements Parameters Config 1 (Docked) Config 2 (Undocked) Config 3 (…) TDP Limit 18W 12W 15W Surface Temp Limit 50C 42C 45C … … … …
  • 7. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 7 SKIN TEMPERATURE AWARE POWER MANAGEMENT Without STAPM With STAPM Without STAPM With STAPM
  • 8. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 8 BATTERY BOOST = Increased efficiency Energy use drops While Performance increases Based on 3DMark11 (Performance preset) on 15W quad-code Kabini (KB 15w4c) and 15W quad-code Beema (BM 15w4c) . Pre-production engineering samples of APUs used with 2x8GB DDR3 1866 RAM, 1280x720 display panel, Windows 8.0 and unreleased reference driver
  • 9. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 9 VERIFICATION CHALLENGES  Complex interaction among various hardware components and software components require a multi-level verification approach  Software readiness as important and critical for time-to-market as a robust and verified hardware design  Verification environment not only needs to model SOC components but System/Platform components as well IP level verification of basic blocks like the activity monitors SOC level verification of the accumulator and controller logic APU FIRMWARE BIOS DRIVER Software validation using a behavioral level model of the hardware HW-SW cosim and/or Emulation for verification of interfaces between hardware components and software modules
  • 10. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 10 VERIFICATION CHALLENGES  Typically software readiness and hardware schedules are mis-aligned ‒ Software development delayed with respect to hardware development to bank on the time between design tapeout and silicon arrival ‒ Puts any software-hardware co-verification at great risk ‒ Alignment of software and hardware schedules a ‘must-have’ requirement for successful execution of current generation power management architecture IP Level Verification SOC Verification HW/SW Co-verification/Emulation Software (BIOS, Driver, Firmware) Verification
  • 11. PERFORMANCE ANALYSIS ENVIRONMENT Power Mgmt. for Energy Efficiency & Verification Challenges Performance Analysis Verification Environment SoC Verification Challenges: UVM, HW-SW Debug, VP, Emulation
  • 12. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 12 SOC PERFORMANCE  Trends: ‒ Chip industry: Lot more disparate client IPs on one chip… ‒ Platform/software use cases: Big Data, HPC, more displays, higher resolution…  Memory is the bottleneck ‒ Interconnect performance is critical to maximize potential of engine IPs  Each client has different general characteristics ‒ CPU: Latency sensitive for single-threaded performance; latency-under- load ‒ GFX: Massively parallel workloads; huge appetite for memory bandwidth ‒ Display and Real-time clients: Burst traffic, with demanding QoS requirements Visual Computing HPC Big Data Evolutionary design System-on- Chip Reuse New Class of Applications: Large Data Sets, Massively Parallel New Class of Constraints: IP Reuse, Large Complex SOCs Memory Subsystem (Interconnect) Performance Applications demand high-performance memory access Larger no# clients demand high performance memory access
  • 13. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 13 PERFORMANCE VALIDATION FOR INTERCONNECT IP  Ensure that performance metrics of interest meet the product goals  Metrics: ‒ Peak bandwidth ‒ DRAM utilization efficiency ‒ Unloaded latency for different clients ‒ Loaded latency curve  Use RTL simulation Related approach is to use an abstract performance model.
  • 14. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 14 BANDWIDTH MEASUREMENT AT INTERFACE Inbound Data • Record number of bytes moved Outbound Data • Record number of bytes moved LATENCY MEASUREMENT AT INTERFACE Inbound Request • Save tag/timestamp Outbound Response • Match tag • Delta with saved timestamp • Record latency
  • 15. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 15 INTERCONNECT IP Interconnect CPU0 CPU1 IO GPU DRAM Chn 1 DRAM Chn 0 Interface points for primary performance measurements - Need low development/maintenance cost - Interfaces not necessarily identical Key challenges - Reuse existing functional verification code - Leverage industry-standard UVM framework - Software engineering approach Approach DESIGN PARAMETERS
  • 16. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 16 TRACKER CLASS Simple/minimal code Two types: Bandwidth[B.W] & Latency Data structures to track the selected metric[B.W and latency] One tracker per metric per interface Scoreboard instantiates tracker objects, and invokes track method when transactions are observed
  • 17. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 17 PERFORMANCE SCOREBOARDS AT EACH INTERFACE Interconnect CPU0 CPU1 IO GPU DRAM Chn 1 DRAM Chn 0 SB SB SB SB SCOREBOARD FUNCTIONS Callbacks registered with verification monitors for all data transactions (UVM: analysis ports) Master (instantiate) tracker objects When callback received, invoke track method on all trackers.
  • 18. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 18 END OF SIMULATION Top-level performance environment module queries each scoreboard for metrics Each scoreboard queries each instantiated tracker for metrics Bottom-up rollup of data, formatted and printed in a file for analysis. Env CPU0 Scoreboard BW Tracker Latency Tracker CPU1 Scoreboard BW Tracker Latency Tracker GPU Scoreboard BW Tracker Latency Tracker IO Scoreboard BW Tracker Latency Tracker
  • 19. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 19 ADVANTAGES Minimal new code (low development/maintenance costs) Leverages existing verification testbench infrastructure Exploits recurring measurement patterns Code portable from IP-level to SOC-level UVM (standard) compliant
  • 20. SOC VERIFICATION CHALLENGES Power Mgmt. for Energy Efficiency & Verification Challenges Performance Analysis Verification Environment SoC Verification Challenges: UVM, HW-SW Debug, VP, Emulation
  • 21. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 21 VERIFICATION CHALLENGE : INCREASED COMPLEXITY, INCREASE IN CORES AND REDUCED TIME TO MARKET Baseline Design Design Complexity Power Management Firmware Software Baseline Design Design Complexity Power Management Firmware Software Complexity Time Reduced Design Cycle Increased Complexity Design Cycle 0 5 10 15 20 25 0 20 40 60 80 100 120 140 2006 2011 2014 IPs (left axis) Average IP and Processor Core trends in advanced SoCs Source: Caspi, HVC 2013 IP Cores Embedded Processor Cores Ref: [3]
  • 22. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 22 UVM UVM 1.2 Testbench UVM Methodology – A big leap in Verification. What Next? reusable Source : uvm cookbook
  • 23. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 23 HW-SW DEBUG  SoC verification involves lot of embedded software  The number of heterogeneous cores are growing ‒ Need for the debug process capability of simultaneously viewing multiple cores both from a HW perspective as well as from programmers point of view  SoC debug need a simultaneous view of both hardware and software ‒ RTL and gate level, including HDL source code, waveform, schematic, assertion, testbench, transaction and power-aware debug ‒ Programmer's view of both C/C++ and assembly code as well as memory, register and breakpoint windows ‒ No standard tool or accepted methodology exist. The debug tool released this year by EDA company’s could evolve and fill the HW-SW gap.
  • 24. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 24 VIRTUAL PROTOTYPE MODEL - GAPS  RTL and VP are developed in two parallel streams  VP model used for Architecture exploration, SW development, Reference model for verification. However gaps exist in developing good quality of VP model ‒ Largely the firmware code is applied to verify the VP – may not cover entire VP . No randomization used. ‒ Coverage still largely eludes the VP verification. Tools available in market do not address the coverage topic in a straight forward way especially toggle coverage  Therefore, determining “Are we Done? “ for VP verification poses big gaps
  • 25. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 25 EMULATION: WHEN TO USE WHICH CONFIGURATION? Characteristics In-circuit Emulation Embedded Target Emulation Hybrid Virtual/Emulation Why • Connecting real hardware to your design • Real peripheral device testing • Real-world traffic • Enables Save/Restore • Easily re-locatable • Additional debug monitoring • Enables Save/Restore • Easily re-locatable • Capacity savings • Highest performance • Improved software debug When to use • When testing in real environment with real devices is important • When CPU validation is a higher priority • When highest model accuracy is required • When getting deep into workloads is important • When CPU validation is a higher priority • When capacity is available • Need to run large software workloads • When CPU validation is a lower priority • Fast initial bring-up of OS Who • Platform engineering teams • Design teams • Product engineering teams • Platform engineering teams • Design teams • Software teams • GFX driver developers • Platform engineering teams • Design teams Reference: [3] cdnlive ’14 . Alex Starr, Brian Fisk
  • 26. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 26 SUMMARY  EFFICIENT POWER MANAGEMENT TECHNIQUES SUCH AS STAPM AND BATTERY BOOST FOR IMPROVED ENERGY EFFICIENCY [PERFORMANCE/WATT]  DEVELOPING PERFORMANCE ANALYSIS ENVIRONMENT BY REUSING EXISTING VERIFICATION ENVIRONMENT  HOLISTIC VIEW OF SOC VERIFICATION : EVOLUTION OF UVM METHDOLOGY, UVM 1.2 AND CHALLENGES WITH MULTI LANGUAGE SUPPORT/AMS SUPPORT. EDA INDUSTRY/TOOL CHALLENGES WITH HW-SW DEBUG, VP MODEL VERIFICATION. H/W ASSISTED SIMULATION ACCELERATION, CHOOSING EMULATION CONFIGURATION FOR YOUR DESIGN. Power Mgmt for Energy Efficiency & Verification Challenges Performance Analysis Verification Environment SoC Verification Challenges
  • 27. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 27 THANKYOU
  • 28. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 28 REFERENCES 1. Applying AMD's "Kaveri" APU for Heterogeneous Computing. Hot Chips 26 - Palo Alto, CA. Bouvier Dan, Sander Ben 2. UVM CookBook 3. Complementing In-circuit Emulation with Virtualization for Improved Efficiency, Debug Productivity, and Performance. CDNLIVE SI VALLEY 2014. Alex Starr, Brian Fisk 4. Harry Foster, Mentor Graphics. DAC’14
  • 29. | The 12th International System-on-Chip Conference, Nov. 22-23, 2014 | OCTOBER 31, 2014 | 29 DISCLAIMER & ATTRIBUTION The information presented in this document is for informational purposes only and may contain technical inaccuracies, omissions and typographical errors. The information contained herein is subject to change and may be rendered inaccurate for many reasons, including but not limited to product and roadmap changes, component and motherboard version changes, new model and/or product releases, product differences between differing manufacturers, software changes, BIOS flashes, firmware upgrades, or the like. AMD assumes no obligation to update or otherwise correct or revise this information. However, AMD reserves the right to revise this information and to make changes from time to time to the content hereof without obligation of AMD to notify any person of such revisions or changes. AMD MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE CONTENTS HEREOF AND ASSUMES NO RESPONSIBILITY FOR ANY INACCURACIES, ERRORS OR OMISSIONS THAT MAY APPEAR IN THIS INFORMATION. AMD SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. IN NO EVENT WILL AMD BE LIABLE TO ANY PERSON FOR ANY DIRECT, INDIRECT, SPECIAL OR OTHER CONSEQUENTIAL DAMAGES ARISING FROM THE USE OF ANY INFORMATION CONTAINED HEREIN, EVEN IF AMD IS EXPRESSLY ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. ATTRIBUTION © 2014 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD Arrow logo and combinations thereof are trademarks of Advanced Micro Devices, Inc. in the United States and/or other jurisdictions. Other names are for informational purposes only and may be trademarks of their respective owners.