physical_address segmentation.pdf

8086 Microprocessor
 A 40pin, +5V supply, VLSI Chip launched by Intel in 1978
 Other family members of 8086:
8088, 80186, 80286, 80386, 80486, Pentium
 A 16-bit microprocessor with
• 16-bit Data Bus
• 20-bit Address Bus
 Generates 20-bit address by multiplexing Address-Data
(AD0-AD15) and Address-Status (A15-A16/S3-S6) buses
 Can access up to 220
=1 MB memory (00000H - FFFFFH)
 Clock input frequency: 5MHz-10MHz
 Can operate in two modes- Minimum and Maximum
 can support up to 64K I/O ports

8086 Internal Architecture
 8086 architecture has two blocks or units:
-Bus Interface Unit (BIU): handles read/write operations from/to Memory/IO
-Execution Unit (EU): Decoding/Execution and Control
 It employs asynchronous parallel processing (or pipelining)
in which both units operate at the same time & thus in
contrast to 8085 it performs instruction fetching & execution
simultaneously to speed up the process
Fetching
Decoding
&
Execution
8086 MPU
Bus Interface
Unit (BIU)
Execution Unit
(EU)

BIU/EU
 The 8086 CPU logic has been partitioned into two functional units
namely BIU & EU
 The major reason for this separation is to increase the processing
speed of the processor
 BIU contains Instruction queue, Segment registers, Instruction
pointer, Address adder
 BIU performs all external transactions (bus operations) such as
instruction fetching, reading/writing operands from/to memory and
I/O devices. It also calculates 20-bit physical addresses
 BIU pre-fetches instruction bytes (upto 6) in a FIFO register called
instruction queue
 EU contains Control circuitry, Instruction decoder, ALU, Pointer &
Index register and Flag register
 EU decodes & executes instructions from instruction queue. Control
unit in EU generates various control signals
 While EU is executing instructions, BIU keeps on fetching instruction
(but upto a max. of 6) in the queue. This parallel processing of both
units is called pipelining which speeds up the overall process

AH AL
BH BL
CH CL
DH DL
STACK POINTER (SP)
BASE POINTER (BP)
SOURCE INDEX (SI)
DESTINATION INDEX (DI)
EXTRA SEGMENT (ES)
CODE SEGMENT (CS)
STACK SEGMENT (SS)
DATA SEGMENT (DS)
INSTRUCTION POINTER (IP)
CONTROL
SYSTEM
6 5 4 3 2 1
ARITHMETIC
LOGIC UNIT
FLAGS
Instruction Queue
OPERANDS
∑
Memory
Interface
EU
BIU
Instruction
Decoder
AX
BX
CX
DX
FIFO

8086 REGISTER ORGANIZATION
ES
CS
SS
DS
IP
AH
BH
CH
DH
AL
BL
CL
DL
SP
BP
SI
DI
FLAGS
AX
BX
CX
DX
Extra Segment
Code Segment
Stack Segment
Data Segment
Instruction Pointer
Accumulator
Base Register
Count Register
Data Register
Stack Pointer
Base Pointer
Source Index
Destination Index
Type Register
size
Name of the
Register
General
purpose
registers
16 bit AX, BX, CX, DX
8 bit AL, AH, BL, BH,
CL, CH, DL, DH
Pointer
registers
16 bit SP, BP
Indexed
registers
16 bit SI, DI
Instruction
Pointer
16 bit IP
Segment
registers
16 bit CS, DS, SS, ES
Flags 16 bit Flag register

General Purpose Registers
8086 has 8 general purpose registers which:
 Can be individually used for storing 8-bit data
 Two registers can be combined to store 16-bit data
 Valid register pairs are: AX, BX, CX, DX
 AX is also called Accumulator having some special features
 BX, also called Base Register is the only general purpose
register which can also be used in based-addressing mode
 CX is also used as a default Counter Register in some
instructions (SHIFT, ROTATE & LOOP)
Acc. AH AL AX
Base BH BL BX
Counter CH CL CX
Data DH DL DX
 DX or Data Register is also
used by default to store upper
16-bit data in division and
multiplication operations

Register Name of the Register Special Function
AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic operations
AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic operations
BX Base register Used to hold base value in base addressing mode to access
memory data
CX Count Register Used to hold the count value in SHIFT, ROTATE and LOOP
instructions
DX Data Register Used to hold data for multiplication and division operations
SP Stack Pointer Used to hold the offset address of top stack memory location
BP Base Pointer Used to hold the offset or base value in based addressing
mode to access data from stack memory
SI Source Index Used to hold index value of source operand (data) for string
instructions
DI Data Index Used to hold the index value of destination operand (data) for
string operations

U U U U OF DF IF TF SF ZF U AF U PF U CF
Flag Register
1. CF CARRY FLAG
Conditional Flags
(Compatible with 8085, except OF):
Set/Reset by ALU on the basis
of results of arithmetic
operations
2. PF PARITY FLAG
3. AF AUXILIARY CARRY
4. ZF ZERO FLAG
5. SF SIGN FLAG
6. OF OVERFLOW FLAG
7. TF TRAP FLAG Control Flags:
Flag register is a 16-bit register with 9 active flags

10
8086 Flag
Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF
Carry Flag
This flag is set, when there is a
carry out of MSB in case of
addition or a borrow in case of
subtraction.
Parity Flag
This flag is set to 1, if the lower byte of
the result contains even number of
1’s ; for odd number of 1’s set to zero.
Auxiliary Carry Flag
This is set, if there is a carry from the lowest
nibble, i.e, bit three during addition, or
borrow for the lowest nibble, i.e, bit three,
during subtraction.
Zero Flag
This flag is set, if the result of the
computation or comparison
performed by an instruction is zero
Sign Flag
This flag is set, when the result
of any computation is negative
Tarp Flag
If this flag is set, the processor
enters the single step execution
mode by generating internal
interrupts after the execution of
each instruction
Interrupt Flag
Causes the 8086 to recognize external
mask interrupts; clearing IF disables these
interrupts.
Direction Flag
This is used by string manipulation instructions. If this flag bit is ‘0’, the
string is processed beginning from the lowest address to the highest
address, i.e., auto incrementing mode. Otherwise, the string is
processed from the highest address towards the lowest address, i.e.,
auto incrementing mode.
Over flow Flag
This flag is set, if an overflow occurs, i.e, if the result of a signed operation
is large enough to accommodate in a destination register. The result is of
more than 7-bits in size in case of 8-bit signed operation and more than 15-
bits in size in case of 16-bit sign operations, then the overflow will be set.

Memory Segmentation in 8086
 8086 has a 20-bit address bus & thus can address a maximum of
1MB of memory
 But 8086 has 16-bit registers which can hold only 16-bit addresses
 Solution is to divide 1MB memory in 64KB segments (total sixteen)
as they can be accessed by using 16-bit addresses. However, only 4
segments are accessible by 8086 at a time. These 4 segments are:
• Code segment: Used for storing the codes or instructions
• Stack segment: Used as a stack
• Data segment: Used for storing data
• Extra segment: Used for storing in-excess data
 Address of a segment is of 20-bits, however, within a segment a
memory location can be specified or accessed using a 16-bit
address called effective address or offset
Advantages of Memory Segmentation:
 Allows the memory capacity to be 1MB although actual addresses to
be handled are of 16-bit size
 Allows the placing of code, data and stack portions of the same
program in different parts (segments) of the memory, for data and
code protection.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Memory
00000H
FFFFFH
1MB
Address
Range
64KB Memory
Segment
Only 4 such segments can be
addressed (active) at a time
4
5
6
7

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Memory
00000H
FFFFFH
1MB
Address
Range
Code Segment
Stack Segment
Data & Extra
Segments
• Segments may or may not be
consecutive
• Segments can also be contiguous
(adjacent), disjointed or overlapping

1
Code Segment
3
4
Data Segment
Extra Segment
7
8
9
10
11
12
13
14
15
Stack Segment
Memory
00000H
FFFFFH
1MB
Address
Range
Starting
Addresses
of
Segments
1000 0H
4000 0H
5000 0H
F000 0H
CSR
DSR
ESR
SSR
We can take any value
of starting address of a
segments but it must be
divisible by 16 and
lowest 4 bits (lowest
hex digit) must be 0
Segment registers
(CSR, DSR, SSR &
ESR) hold upper
16-bits of 20-bits
starting address
of segments
SEGMENT REGISTERS

Instruction Pointer
 Instruction Pointer (IP) is a 16-bit register that identifies the
location of the next instruction to be fetched from the code
segment
 It contains the offset or effective address of the next instruction
instead of its physical address
 IP and CS are both 16-bit registers, but a 20-bit address is
needed to access memory
 The offset in IP is combined with the starting address of CS
(contained by CSR) to generate 20-bit physical address of the
next instruction
 The offset or effective address (EA) is a 16-bit address which
points to a memory location within a segment
 Every time an instruction is fetched from memory, 8086 updates
IP by incrementing it by two (instead of one as in 8085)
because it reads two bytes at a time

 The 20-bit physical address is generated by adding 16-bit contents of a
segment register with an 16-bit offset value (also called Effective Address)
which is stored in a corresponding default register (either in IP, BX, SI, DI,
BP or SP. Different segments have different default register for offset, for
example IP is default offset register for Code Segment)
 BIU always appends 4 zeros automatically to the 16-bit address of a segment
register (to make it 20-bit) because it knows the starting address of a
segment always ends with 4 zeros
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Physical Address Generation in 8086
CS DS ES SS
IP BX
DI
SI
DI
Default Registers Assigned to store
offset values for different segments
BP
Actual address for
memory
Upper 16bit of starting
address of a segment 20-bits 16-bits
Points to a memory
location within a
segment
SP

 Offset is derived from the combination of
pointer registers, index registers the
Instruction Pointer, and immediate values
(called displacement)
0000
+
Segment address
Offset
Memory address
 Examples
3 4 8 A 0
4 2 1 4
3 8 A B 4
CS
IP +
Instruction
(code)
address
5 0 0 0 0
F F E 0
5 F F E 0
SS
SP +
Stac
k
addr
ess
1 2 3 4 0
0 0 2 2
1 2 3 6 2
DS
DI +
Data
addr
ess
Physical Address Calculation

1
Data
Segment
3
4
Code
Segment
Extra
Segment
7
8
9
10
11
12
13
14
15
Stack
Segment
Memory
00000H
FFFFFH
1MB
Address
Range
348A0H
4214 H
38AB4 H
CS
IP
Physical Address
Start of Code Segment
(348A0H)
Code Byte at 38AB4H
IP = 4214H
+
Example of Physical Address Generation for Code Segment

Memory
Segment Register
Offset
Physical Address
+
DS:
SI
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
Data is fetched with respect to the DS register which contains starting
or base address
The effective address (EA) or offset is in SI (default register for DS)
The EA depends on the addressing mode
DS:EA
0H
0FFFFFH
Example of Physical Address Generation for Data Segment

Memory
Segment Register
Offset
Physical Address
+
SS:
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment register.
The stack grows toward decreasing memory locations.
The SP points to the last or top item on the stack.
The offset is given by the SP register.
SS:SP
0H
0FFFFFH
Example of Physical Address Generation for Stack Segment

Pin Diagram of Intel 8086
This set of
pins works in
two modes
For Maximum Mode
For Minimum Mode

AD0 – AD15 (Bi-directional)
These lines are multiplexed
bi-directional address/data
bus.
During T1, they carry lower
order 16-bit address.
In the remaining clock
cycles, they carry 16-bit
data.
AD0-AD7 carry lower order
byte of data.
AD8-AD15 carry higher order
byte of data.

A19/S6, A18/S5, A17/S4, A16/S3
(Unidirectional)
 These lines are multiplexed
unidirectional address and
status bus.
 During T1, they carry higher
order 4-bit address.
 In the remaining clock cycles,
they carry status signals.

BHE / S7 (Output)
BHE stands for Bus High
Enable.
BHE signal is used to
indicate the transfer of data
over higher order data bus
(D8 – D15).
It is multiplexed with status
pin S7.

RD (Read) (Output)
It is a read signal used
for read operation.
It is an output signal.
It is an active low
signal.

READY (Input)
This is an acknowledgement
signal from slower I/O
devices or memory.
It is an active high signal.
When high, it indicates that
the device is ready to transfer
data.
When low, then
microprocessor is in wait
state.

RESET(Input)
It is a system reset.
When high, microprocessor
enters into reset state and
terminates the current
activity.
It must be active for at least
four clock cycles to reset
the microprocessor.

INTR (Input)
It is an interrupt request
signal.
It is active high.
It is level triggered.

NMI (Input)
It is a non-maskable
interrupt signal.
It is an active high.
It is an edge triggered
interrupt.

TEST (Input)
It can be used to test the
status of math co-processor
(8087)
The BUSY pin of 8087 is
connected to this pin of
8086.
If low, execution continues
else microprocessor is in
wait state.

CLK (Input)
This clock input provides
the basic timing for
processor operation.
The range of frequency of
different versions is 5 MHz,
8 MHz and 10 MHz.

VCC and VSS (Input)
VCC is power supply signal.
+5V DC is supplied
through this pin.
VSS is ground signal.

MN / MX (Input)
8086 works in two modes:
• Minimum Mode
• Maximum Mode
If MN/MX is high, it works
in minimum mode.
If MN/MX is low, it works in
maximum mode.

Pins 24 to 31 issue two
different sets of signals.
One set of signals is
issued when CPU
operates in minimum
mode.
Other set of signals is
issued when CPU
operates in maximum
mode.

Pin Description for Minimum
Mode

INTA (Output)
This is an interrupt
acknowledge signal.
When microprocessor
receives INTR signal, it
acknowledges the interrupt
by generating this signal.
It is an active low signal.

ALE (Output)
This is an Address Latch
Enable signal.
It indicates that valid
address is available on bus
AD0 – AD15.
It is an active high signal
and remains high during T1
state.
It is connected to enable pin
of latch 8282.

DEN (Output)
This is a Data Enable signal.
This signal is used to enable
the transceiver 8286.
Transceiver is used to
separate the data from the
address/data bus.

DT / R (Output)
This is a Data
Transmit/Receive signal.
It decides the direction of
data flow through the
transceiver.
When it is high, data is
transmitted out.
When it is low, data is
received in.

M / IO (Output)
This signal is issued by the
microprocessor to
distinguish memory
access from I/O access.
When it is high, memory is
accessed.
When it is low, I/O devices
are accessed.

WR (Output)
It is a Write signal.
It is used to write data in
memory or output device
depending on the status of
M/IO signal.

HOLD (Input)
When DMA controller
needs to use address/data
bus, it sends a request to
the CPU through this pin.
When microprocessor
receives HOLD signal, it
issues HLDA signal to the
DMA controller.

HLDA (Output)
It is a Hold Acknowledge
signal.
It is issued after receiving
the HOLD signal.

Pin Description for Maximum
Mode

QS1 and QS0 (Output)
These pins provide the
status of instruction queue.
QS1 QS0 Status
0 0 No operation
0 1 1st
byte of opcode from queue
1 0 Empty queue
1 1 Subsequent byte from queue

S0, S1, S2 (Output)
These status signals
indicate the operation being
done by the microprocessor.
This information is required
by the Bus Controller 8288.
Bus controller 8288
generates all memory and
I/O control signals.

S2 S1 S0 Status
0 0 0 Interrupt Acknowledge
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode Fetch
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 Passive
S0, S1, S2 (Output)

LOCK (Output)
 This signal indicates that other
processors should not ask CPU
to relinquish the system bus.
 When it goes low, all interrupts
are masked and HOLD request
is not granted.
 This pin is activated by using
LOCK prefix on any instruction.

RQ/GT1 and RQ/GT0 (Bi-directional)
 These are Request/Grant pins.
 Other processors request the
CPU through these lines to
release the system bus.
 After receiving the request,
CPU sends acknowledge signal
on the same lines.
 RQ/GT0 has higher priority than
RQ/GT1.

8086 Minimum Mode
 In the minimum mode of 8086, MN/MX pin is connected
to logic 1 (+5V )
 There is a single processor (8086) in this mode
 All the control signals are given out by the
microprocessor chip itself.
 Other supporting components in the system are latches,
transreceiver, clock generator, memory and I/O devices.
 Requires less (or minimum) hardware (than maximum
mode) & thus less costly but can not be used in large
multiprocessor systems

51
Octal
transceiver
No extra
processor
except 8086
is used

8086 Maximum Mode
 In the maximum mode, the 8086 is operated by connecting MN/MX
pin to ground (logic 0).
 In the maximum mode, there may be more than one processor in
the system (e.g. math co-processor 8087)
 A bus controller (8288) is also used in this mode which is connected
to 8086 by using status signals S2,S1,S0. Some of the control
signals in this mode are generated by 8288 instead of 8086
 8288 derives (regenerates) various control signals like ALE, DEN,
DT/R, Memory read/write (MRDC, MWTC), I/O read/write (IORC,
IOWC), AMWC & AIOWC by using information at status signals
S2,S1,S0 supplied by 8086
 Other supporting components in the system are same as in
minimum mode (latches, transreceiver, clock generator, memory
and I/O devices)
 This mode is costly due to greater hardware but is useful in large
multiprocessor systems

54
Derived
control
signals
Octal
transceiver

CLK
M/IO
ALE
ADDR/
DATA
ADDR/
STATUS
RD
DT/R
DEN
T1 T2 T3 TW T4
A15-
A0
A19-
A16
RESERVED
FOR DATA
VALID
D15-
D0
MEMORY ACCESS TIME
READ BUS
CYCLE IN 8086

CLK
M/IO
ALE
ADDR/
DATA
ADDR/
STATUS
DT/R
DEN
T1 T2 T3 TW T4
A15-
A0
A19-
A16
DATA OUT (D15-D0)
WR
WRITE BUS
CYCLE IN 8086

8086 MEMORY ORGANIZATION
 8086 supports 220
= 1,048,576 bytes (1Mbytes) of memory over the
address range 0000016 to FFFFF16(00000H to FFFFFH)
 Two consecutive bytes can be accessed as one word (16-bits)
 The lower-addressed byte is the least significant byte of the word, and
the higher-addressed byte is its most significant byte
 Address of lower byte of word is called address of the full word
 Memory space of 1MB is divided into two chips (called banks) of
512KB each having even & odd addresses
 This is done because most memories are ‘byte-oriented’ (1 byte
read/write at a time), but as 8086 is capable to read/write 16-bit (2
bytes) at a time, we need to use two chips for 16-bit word operations
 Two banks have alternate addresses because 16-bit words are stored
in consecutive locations & at the same time 8086 must access both
banks simultaneously for 16-bit operations
 If we had used only 1 chip of 1MB, 8086 could read only 1 byte at a
time & thus would need two operations (bus cycles) for every 16-bit
word operation. Thus process would have been slower.

physical_address segmentation.pdf

8086 MEMORY ORGANIZATION
(Also called BLE)

BYTE/WORD TRANFER IN 8086
A, B = any assumed
memory location address in
even, odd banks. Brackets
indicate contents of
location & not address

BYTE/WORD TRANFER IN 8086
A word stored at an even-address boundary (00000H, 00002H, 00004H etc) is said to be
an aligned word while a word stored at an odd address boundary (00001H, 00003H,
00005H etc) is called misaligned word. A misaligned word requires two read
operations (or bus cycles) & thus double time
Misaligned
word
Aligned
word

8086 INTERRUPTS
Three types of interrupts sources are there in 8086:
1. An external signal applied to NMI or INTR input pin
(Hardware interrupt)
2. Execution of INTn (n=00H-FFH) instruction
(Software interrupt)
3.Interrupt caused by some error condition produced
in 8086 instruction execution process.
(Divide by zero, overflow errors etc)
Sources of Interrupts in
8086:

8086 Interrupts
8086 Interrupts
Software Interrupts
INT n
Software Interrupts
INT n
Hardware
Interrupts
Hardware
Interrupts
Maskable
Interrupt
(INTR)
Maskable
Interrupt
(INTR)
Nonmaskable
Interrupt
(NMI)
Nonmaskable
Interrupt
(NMI)
The programmer
can choose to mask
specific interrupts
and re-enable them
later
The programmer
can choose to mask
specific interrupts
and re-enable them
later
The programmer cannot
control when a non
maskable interrupt is served
The programmer cannot
control when a non
maskable interrupt is served
The processor has to stop
the main program to execute
the NMI Service Routine.
The processor has to stop
the main program to execute
the NMI Service Routine.
256 Types of
software Interrupts
INT 00 to INT FF
256 Types of
software Interrupts
INT 00 to INT FF

1. Pushes the content of the flag register onto the stack to preserve the status of
IF and TF flags, by decrementing the stack pointer (SP) by 2
2. Disables the INTR interrupt by clearing IF in the flag register
3. Resets TF in the flag register, to disable the single step or trap interrupt
4. Pushes the content of the code segment (CS) register onto the stack by
decrementing SP by 2
5. Pushes the content of the instruction pointer (IP) onto the stack by
decrementing SP by 2
6. Performs an indirect far jump to the start of the interrupt service routine
(ISR) corresponding to the received interrupt.
If an interrupt has been requested, the 8086 Microprocessor processes it by
performing the following series of steps:
8086 Interrupt Processing Steps

Steps involved in processing an interrupt instruction by
the processor
Jumps to the Interrupt Vector Table
Takes the CS and IP in the Vector Table
Pushes the existing CS and IP on the Stack
Executes the Interrupt instruction
Loads the new CS and IP
Jumps to the ISR
Comes back and continues the Main Program
Executes ISR

Interrupt
Push flags register
Clear IF and TF
Push CS and IP
Load CS and IP
Pop IP and CS
Pop flags register
Interrupt Service
Routine (ISR)
Interrupt program
:
:
:
:
:
:
IRET
Main Program
Processing of an Interrupt by the 8086

RESET as a
Non-
Maskable
Interrupt
NMI pin connected to Ground : No interrupt

Non-Maskable Interrupt activated
by RESET button in 8086
(due to high on NMI pin)
RESET
BUTTON

CS
IP
Type 01H Interrupt
(Trap or Single step)
Type 02H Interrupt (NMI)
Type 03H Interrupt (Break Point)
Type 04H Interrupt (Over Flow)
Type 20H Interrupt (Available)
Type 21H Interrupt (Available)
Type 1FH Interrupt (Reserved)
Type FFH Interrupt (Available)
Type 05H Interrupt (Reserved)
Type 00H Interrupt
(Divide by Zero)
Dedicated Interrupts
(05)
Reserved Interrupts
(27)
Available Interrupts
(224)
CS
IP
003FFH
00084H
00080H
0007CH
00014H
00010H
0000CH
00008H
0004FH
0003FH
00002H
00001H
00000H
003FCH
Interrupt
Vector
Table
(IVT)

Given a vector, where is the ISR address stored in memory ?
Offset = Type number X 4
Example:- INT 02H
Offset = 02 x 4 = 08
= 00008H
Type 0 or
INT 00 Interrupt
00000H 00001H
00002H 00003H
2 bytes
2 bytes
CS
IP
CS LSB MSB
CS LSB CS MSB
IP LSB IP MSB

256 Interrupts of 8086 are Divided into
3 Groups
1. Type 00 to Type 04 interrupts-
These are used for fixed operations and hence are called
dedicated interrupts
2. Type 05 to Type 31 interrupts
Not used by 8086,reserved for higher processors like 80286
80386 etc.
3. Type 32 to Type 255 interrupts
Available for user, called user defined interrupts. These can be
either H/W interrupts and activated through INTR line or can
be S/W interrupts.

Type – 0 :- Divide by Zero Error Interrupt
Quotient is large, cant be fit in AL/AX or divide by zero
Type –1:- Single step or Trap Interrupt
Used for executing the program in single step mode by setting
trap flag.
Type – 2:- Non-Maskable Interrupt
This interrupt is used for executing ISR of NMI pin (positive
edge signal), NMI can’t be masked by S/W.
Type – 3:- One-byte INT instruction interrupt
Used for providing break points in the program
Type – 4 Over flow Interrupt
Used to handle any overflow error after signed arithmetic.

An example of an interrupt generated
due to overflow error in an 8086 system

8086 Addressing Modes
1. Register Addressing
2. Immediate Addressing
3. Direct Addressing
4. Register Indirect Addressing
5. Based Addressing
6. Indexed Addressing
7. Based Index Addressing
8. String Addressing
9. Direct I/O port Addressing
10. Indirect I/O port Addressing
11. Relative Addressing
12. Implied Addressing
The instruction will specify the name of the register which
holds the data to be operated by the instruction.
Example:
MOV CL, DH
The content of 8-bit register DH is moved to another 8-bit
register CL
(CL) ← (DH)

5. Based Addressing
In immediate addressing mode, an 8-bit or 16-bit data is
specified as part of the instruction
Example:
MOV DL, 08H
The 8-bit data (08H) given in the instruction is moved to DL
(DL) ← 08H
MOV AX, 0A9FH
The 16-bit data (0A9FH) given in the instruction is moved to
AX register
(AX) ← 0A9FH

5. Based Addressing
Here, the effective address of the memory location at
which the data operand is stored is given in the
instruction.
The effective address is just a 16-bit number written
directly in the instruction.
Example:
MOV BX, [1354H]
MOV BL, [0400H]
The square brackets around the 1354H denotes the
contents of the memory location. When executed, this
instruction will copy the contents of the memory location
into BX register.
This addressing mode is called direct because the
displacement of the operand from the segment base is
specified directly in the instruction.

5. Based Addressing
In Register indirect addressing, name of the register which
holds the effective address (EA) will be specified in the
instruction.
Registers used to hold EA are any of the following
registers:
BX, BP, DI and SI.
Content of the DS register is used for base address
calculation.
Example:
MOV CX, [BX]
Note : Register/ memory
enclosed in brackets refer to
content of register/ memory

5. Based Addressing
In Based Addressing, BX or BP is used to hold the base
value for effective address and a signed 8-bit or unsigned
16-bit displacement will be specified in the instruction.
When BX holds the base value of EA, 20-bit physical
address is calculated from BX and DS.
When BP holds the base value of EA, BP and SS is used.
Example:
MOV AX, [BX + 08H]

5. Based Addressing
SI or DI register is used to hold an index value for memory
data and a signed 8-bit or unsigned 16-bit displacement will
be specified in the instruction.
Displacement is added to the index value in SI or DI
register to obtain the EA.
In case of 8-bit displacement, it is sign extended to 16-bit
before adding to the base value.
Example:
MOV CX, [SI + 0A2H]

5. Based Addressing
In Based Index Addressing, the effective address is
computed from the sum of a base register (BX or BP), an
index register (SI or DI) and a displacement.
Example:
MOV DX, [BX + SI + 0AH]

5. Based Addressing
Employed in string operations to operate on string data.
The effective address (EA) of source data is stored in SI
register and the EA of destination is stored in DI register.
Segment register for calculating base address of
source data is DS and that of the destination data is ES
Example: MOVS BYTE
Operations:
Calculation of source memory location:
EA = (SI) BA = (DS) x 1610 MA = BA + EA
Calculation of destination memory location:
EAE = (DI) BAE = (ES) x 1610 MAE = BAE + EAE
(MAE) ← (MA)
If DF = 1, then (SI) ← (SI) – 1 and (DI) = (DI) - 1
If DF = 0, then (SI) ← (SI) +1 and (DI) = (DI) + 1
Note : Effective address of the
Extra segment register

5. Based Addressing
These addressing modes are used to access data from
standard I/O mapped devices or ports.
In direct port addressing mode, an 8-bit port address is
directly specified in the instruction.
Example: IN AL, [09H]
Operations: PORTaddr = 09H
(AL) ← (PORT)
Content of port with address 09H is
moved to AL register
In indirect port addressing mode, the instruction will
specify the name of the register which holds the port
address. In 8086, the 16-bit port address is stored in the
DX register.
Example: OUT [DX], AX
Operations: PORTaddr = (DX)
(PORT) ← (AX)
Content of AX is moved to port
whose address is specified by DX
register.

5. Based Addressing
In this addressing mode, the effective address of a
program instruction is specified relative to Instruction
Pointer (IP) by an 8-bit signed displacement.
Example: JZ 0AH
Operations:
000AH ← 0AH (sign extend)
If ZF = 1, then
EA = (IP) + 000AH
BA = (CS) x 1610
MA = BA + EA
If ZF = 1, then the program control jumps to new
address calculated above.
If ZF = 0, then next instruction of the program is
executed.

5. Based Addressing
Instructions using this mode have no operands. The
instruction itself will specify the data to be operated by
the instruction.
Example: CLC
This clears the carry flag to zero.

Interfacing I/O and peripheral devices
I/O devices
⇒ For communication between microprocessor and
outside world
⇒ Keyboards, CRT displays, Printers, Compact Discs
etc.
⇒
⇒ Data transfer types
Microprocessor
Microprocessor I/ O devices
I/ O devices
Ports / Buffer IC’s
(interface circuitry)
Ports / Buffer IC’s
(interface circuitry)
Programmed I/ O
Data transfer is accomplished
through an I/O port
controlled by software
Interrupt driven I/ O
I/O device interrupts the
processor and initiate data
transfer
Direct memory access
Data transfer is achieved by
bypassing the microprocessor
Memory mapped
I/O mapped

Memory mapped I/O vs I/O mapped I/O
Memory mapping I/O mapping
20 bit address are provided for I/O devices 8-bit or 16-bit addresses are provided for
I/O devices
The I/O ports or peripherals can be treated
like memory locations and so all
instructions related to memory can be
used for data transmission between I/O
device and processor
Only IN and OUT instructions can be used
for data transfer between I/O device and
processor
Data can be moved from any register to
ports and vice versa
Data transfer takes place only between
accumulator and ports
When memory mapping is used for I/O
devices, full memory address space
cannot be used for addressing memory.
⇒ Useful only for small systems where
memory requirement is less
Full memory space can be used for
addressing memory.
⇒ Suitable for systems which require large
memory capacity

physical_address segmentation.pdf

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