![2. Address Bus:
Address Bus[A8 – A15]
These pins carry the higher order of address bus.
The address is sent from microprocessor to
memory.
It carries the most significant 8-bit of memory
I/O address.](https://image.slidesharecdn.com/5-200630105818/85/PINDIAGRAM-OF-8085-MICROPROCESSOR-4-320.jpg)
PINDIAGRAM OF 8085 MICROPROCESSOR
- 1. 8085 PIN DIAGRAM PRESENTED BY, Mrs.B.RAMA PRABHA, ASSISTANT PROFESSOR, DEPARTMENT OF COMPUTER SCIENCE, K.C.S.KASI NADAR COLLEGE OF ARTS & SCIENCE. 1
- 2. 8085 Pin Diagram | Functional Pin Diagram of 8085 Microprocessor 2 The signals of 8085 Pin Diagram can be classified into seven groups according to their functions. 1.Power supply and frequency signals. 2.Address bus. 3.Control and status signals. 4.Interrupt signals. 5.Serial I/O signals. 6.DMA signals. 7.Reset signals.
- 3. 1. Power Supply and Frequency Signals: Vcc : It requires a single +5 V power supply. Vss : Ground reference. X1 and X2 : A tuned circuit like LC, RC or crystal is connected at these two The internal clock generator divides oscillator frequency by 2, therefore, to operate a system at 3 MHz, the crystal of tuned circuit must have a frequency of 6 MHz. CLK OUT : This signal is used as a system clock for other devices. Its frequency is half the oscillator frequency.
- 4. 2. Address Bus: Address Bus[A8 – A15] These pins carry the higher order of address bus. The address is sent from microprocessor to memory. It carries the most significant 8-bit of memory I/O address.
- 5. 3.MULTIPLEXED ADDRESS / DATA BUS The signal lines AD7-AD0 are bidirectional: they serve a dual purpose. They are used as the low order address bus as well as the data bus. In executing an instruction, during the earlier part of the cycle, these lines are used as the low-order address bus. During the later part of the cycle, these lines are used as the data bus. (This is also known as multiplexing the bus.) However, the low-order address bus can be separated from these signals by using a latch
- 6. 3. Control and Status Signals: This group of signals includes two control signals (RD and WR), three status signals (IO/M,S1, and S0) to identify the nature of the operation, and one special signal (ALE) to indicate the beginning of the operation. These signals are as follows: ALE — Address Latch Enable This is positive going pulse generated every time the 8085 begins an operation (machine cycle); it indicates that the bits on AD7-AD0 are address bits. This is used primarily to latch the low-order address from the multiplexed bus and generate a separate set of eight address lines, A7-A0.
- 7. 3. Control and Status Signals: RD— Read This read control signal (active low). This signal indicates that the selected I/O or memory device is to be read and data are available on the data bus. WR— Write: This is a write control signal (active low). This signal indicates that the data on the data bus are to be written into a selected memory device or I/O location.
- 8. 3. Control and Status Signals: IO/M This is status signal used to differentiate between I/O and memory operations. When it is high, it indicates an I/O operation; when it is low, it indicates a memory operation. This signal combines with RD and WR to generate I/O and memory control signals. S1 and S0: These status signals, similar to IO/M, can identify various operations, but they are rarely used in small systems.
- 9. 3. Control and Status Signals: READY It is used by the microprocessor to sense whether a peripheral is ready or not for data transfer. If not, the processor waits. It is used to synchronize slower peripherals to the microprocessor. This signal is used to delay the microprocessor Read or Write cycles until a slow-responding peripheral is ready to send or accept data. When this signal goes low, the microprocessor waits for an integral number of clock cycles until it goes high.
- 10. 4. Interrupt Signals: TRAP TRAP is usually used for power failure and emergency shutoff. RST 7.5 It is a maskable interrupt. It has the second highest priority. RST 6.5 It is a maskable interrupt. It has the third highest priority. RST 5.5 It is a maskable interrupt. It has the fourth highest priority. INTR It is a general purpose interrupt. It is a maskable interrupt. It has the lowest priority. INTA It is an interrupt acknowledgment signal.
- 11. 5. Serial I/O Signals: A) SID (Serial I/P Data) : This input signal is used to accept serial data bit by bit from the external device. B) SOD (Serial O/P Data) : This is an output signal which enables the transmission of serial data bit by bit to the external device.
- 12. 6. DMA Signal: A) HOLD : This signal indicates that another master is requesting for the use of address bus, data bus and control bus. B) HLDA : This active high signal is used to acknowledge HOLD request.
- 13. 7. Reset Signals: A) RESET IN : A low on this pin • Sets the program counter to zero (0000H). • Resets the interrupt enable and HLDA flip-flops. • Tri-states the data bus, address bus and control bus. (Note : Only during RESET is active). Affects the contents of processor’s internal registers randomly.
- 14. 7. Reset Signals: B) RESET OUT : This active high signal indicates that processor is being reset. This signal is synchronized to the processor clock and it can be used to reset other devices connected in the system.
- 15. THANK YOU