PLL_tutorial_slides.pdf

Copyright, Dennis Fischette,
2009
1
First Time, Every Time –
Practical Tips for Phase-
Locked Loop Design
Dennis Fischette
Email: pll@delroy.com
Website: http://www.delroy.com

2009
2
Outline
• Introduction
• Basic Feedback Loop Theory
• Jitter and Phase Noise
• Common Circuit Implementations
• Circuit Verification
• Design for Test

2009
3
Introduction

2009
4
How Are PLL‟s Used?
• Frequency Synthesis (e.g. generating a 1 GHz clock from a
100 MHz reference in a CPU)
• Skew Cancellation (e.g. phase-aligning an internal clock to
the I/O clock) (May use a DLL instead)

2009
5
How Are PLL‟s Used?
• Extracting a clock from a random data stream (e.g. serial-
link clock-data recovery)
• Reference Clean-Up (e.g. low-pass filter source-synchronous
clock in high-speed I/O)
• Frequency Synthesis is the focus of this course.
• Design Priority? Frequency and/or phase accuracy?

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6
What is a PLL?
• Negative feedback control system where fout tracks fin and rising edges of
input clock align to rising edges of output clock
• Mathematical model of frequency synthesizer
   
t
f
t
V in
in 
2
sin
    
t
Nf
t
V in
out 
2
sin

fout
fin
       
dt
t
d
t
f
dt
t
f
t
f


f
2
1
2 

 
Phase-
Locked
Loop
in
out
in
out Nf
f
N 

 f
f
• When phase-locked,
• Phase = ∫ frequency

2009
7
Charge-Pump PLL Block Diagram
• Sampled-system (phase-error is input variable)
• Phase error is corrected by changing frequency (f(t) = ∫ f(t) dt)
• Resistor provides means to separate correction of frequency error
from correction of phase error
ClkOut
Phase-
Freq
Detector
Charge
Pump
Feedback
Div
VCO
RefClk Level-
Shifter
FbClk
GoFaster
GoSlower
VCO
Vctl
C1 C2

PLL Circuit Diagram
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8

PLL Circuit Diagram
• Observations
– Under-damped PLL - ringing
– Effect of cycle slips on Vctl
– Net integrating cap voltage Vc1 lags control voltage Vctl
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9

2009
10
Components in a Nutshell
• Phase-Frequency Detector (PFD): outputs digital pulse
whose width is proportional to sampled phase error
• Charge Pump (CP): converts digital error pulse to analog
error current
• Loop Filter (LPF): integrates (and low-pass filters in
continuous time) the error current to generate VCO control voltage
• VCO: low-swing oscillator with frequency proportional to control
voltage
• Level Shifter (LS): amplifies VCO levels to full-swing
• Feedback Divider (FBDIV): divides VCO clock to generate
FBCLK clock for phase comparison w/reference

2009
11
PLL Feedback Loop Theory

2009
12
What Does PLL Bandwidth Mean?
• PLL acts as a low-pass filter with respect to the reference
modulation. High-frequency reference jitter is rejected
• Low-frequency reference modulation (e.g., spread-spectrum
clocking) is passed to the VCO clock
• PLL acts as a high-pass filter with respect to VCO jitter
• “Bandwidth” is the modulation frequency at which the PLL
begins to lose lock with the changing reference (-3dB)
log(frequency)
BW
Fout
Fref
lower BW
rejects
ref noise
log(frequency)
BW
Fout
Fvco higher BW
rejects
VCO noise

2009
13
Closed-Loop PLL Transfer Function
• Transfer function describes how PLL responds to “excess”
reference phase. i.e. RefClk phase modulation
• Analyze PLL feedback in frequency-domain
– Phase is state variable, not frequency
– “s” is the reference modulation frequency, not reference
oscillation frequency
– Assumes continuous-time (not sampled) behavior
• ffb = (fref - ffb) * G(s) where G(s) == open-loop gain
• H(s) = ffb/fref = G(s)/(1+G(s))

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Open-Loop PLL Gain
• G(s) = (Kvco/s)IcpF(s)*e-sTd/M
– where ferr
• Kvco = VCO gain in Hz/V
• Icp = charge pump current in Amps
• F(s) = loop filter transfer function in Volt/Amp
• M = feedback divisor
• Td = delay in feedback-loop (e.g. FBDIV, Tpfd/2)

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15
PLL Components in Frequency
Domain
PFD
Icp/2pi
VCO
Vctl
C1 C2
1/N
Kvco/s
FBDIV
Charge
Pump
sub
s*( (c1+c2)+(s*rc1*c2)
(1+s*rc1)
Vctl(s) / Icp(s) =
fvco
fref
ffb
ferr

2009
16
Closed-loop PLL Transfer Function
• H(s) = n
2 (1+ s/z) / (s2+2sn + n
2)
– where
• n = undamped natural frequency (rad/s)
• z = stabilizing zero = 1 /RC1 (rad/s)
•  = damping factor
– 2nd-order (two poles p1,p2 and one zero)
– 2nd-order ignores C2 cap and feedback delays
• If < 1, complex poles lead to damped oscillation
– Real  exponential decay(n) , Imag  oscillation (n)
• If  > 1, z and p1 cancel: BW(-3dB) ~ 2n
– Acts like single-pole system

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What is a “Zero”?
• The “Zero” in the numerator of the closed-loop
transfer function is the frequency in radians/s
where the gain of the integral and proportional
paths are equal.
• Classic loop: z = 1 /RC1 (rad/s)
• Concept can be applied to loop filters that do not
contain a resistor.

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Natural Frequency
• Related to bandwidth
– n = (2 * BW) / sqrt( 1+22+sqrt( (1+22)2+1 ) )
• Undamped Natural Frequency:
– n = sqrt(Kvco*Icp/( M*C1)) in rad/sec
– where
• Kvco = VCO gain in Hz/V
• Icp = charge pump current in Amps
• M = feedback divisor
• C1 = large LPF capacitor
– For stability: n/2 < ~1/15 reference frequency
• Typical value: 500 kHz < n/2 < 10MHz

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Damping Factor
• Related to stability
• Damping Factor:  = Rlpf * C1 * n /2
– Dimensionless, Usually ~0.45 <  < ~2
– Lower end of range for low period jitter
– Higher end of range for accurate ref phase tracking
– Rlpf provides means to set stability independent of bandwidth

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Open-Loop Transfer Function
• 20*log(Gain) vs. log(Modulation Frequency)
• 2 poles @ origin, 1 zero @ wz, 1 pole @wp
log(wmod)
Open-Loop
Gain
(dB)
-40dB/dec
-20dB/dec
-40dB/dec
wz wc wp
wn
wz = 1/RC1
wp = 1/RC2
wc = crossover frequency
wn = natural frequency

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Stability and Phase Margin
• Phase margin determines stability as in other feedback loops 180 - phase of
open-loop transfer function at crossover frequency
• fm (degrees) = (180/)*(atan(c*RC1)–atan(c*RC2)-c*Tdly)
– c == crossover frequency
• frequency where open-loop gain G(s) = 0dB
– For stability: 1/RC1 (zero) < c < 1/RC2 (parasitic pole)
– Typical Range: 1.2*n < c < 2.5*n
• Phase margin (fm) ~ 100 *  (for  < 0.5)
– Usually 45° < PM < 70°

2009
22
Aliasing in a Sampled Loop
• Sampling nature of PFD  frequency-domain aliasing
– Can‟t low-pass filter ref noise before PFD sampling – unlike A/D‟s
– Need z-domain analysis for accurate PLL modeling – analogous to
sample-and-hold
• Phase of modulation with respect to ref affects aliasing
– e.g. ref modulation at ½ * fref. No jitter if sampled at 0°,180°, max at
90°,270°
• Modulation at frequencies > Nyquist (fref/2) appears at other frequencies
– e.g. fref=100MHz  ref modulation at 99MHz looks just like 1MHz ref
modulation to the PLL
– continuous-time model says that PLL should reject more 99MHz noise
than 1 MHz noise
frequency
fREFCLK
fBW
Fout
Fin

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23
PLL Response to Reference
Modulation

2009
24
Phase Tracking vs. Damping
• Phase Tracking vs. Damping
• Closed-loop Transfer Function (ffb/fref)
• Phase Tracking  think “accumulated” period jitter or phase
error
• Peaking at low and high damping factors  bad
• Peaking at high damping due to smoothing capacitor pole
(1/RC2) and/or under-sampling (Gardner)
• Peaking very sensitive to parasitic pole (1/RC2) at high R
• Min peaking w/damping ~ 1.0 - 1.5 if C2 ~ 5% * C1
• Typical peaking: 1 – 3 dB (CPU high-end, IO low-end)
• For lower peaking, damping > 2 and C2 small
• Simulation Condition (following slides): C2 = 6.7% * C1

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Closed-loop Transfer Function

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Phase Response to Ref Step
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27

2009
28
Time-Domain Phase Response to
Reference Step
• Transient Simulation Conditions (behavioral model):
– step reference phase by 2 radians. Observe phase overshoot
– C2 = 10% * C1 (high end of C2 range requires lower )
• Less ringing and overshoot as   1
• Severe under-damping  slow ringing and overshoot
• Severe over-damping  fast ringing and overshoot
• Ringing at high damping due to smoothing pole (large RC2)
and/or low over-sampling

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• From Gardner “Phaselock Techniques, 3rd Ed.” (p. 102) –
ignores parasitic poles and over-sampling rate
•  < 1
Terr = Tstep * [(cos( sqrt(1-2)*nt ) - (/sqrt(1-2)*sin(
sqrt(1-2)*nt )] * e-nt
•  = 1
Terr = Tstep * (1-nt) * e-nt
•  > 1
Terr = Tstep * [(cosh( sqrt(2 -1)*nt) - (/sqrt(2 -
1)*sinh( sqrt(2 - 1)*nt )] * e-nt
Time-Domain Phase Response to
Reference Step

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2009
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Frequency Response to Ref Step

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Freq Overshoot from Ref Step

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34
PLL Circuits
• Phase-Frequency Detector
• Charge-Pump
• Loop Filter
• Voltage-Controlled Oscillator
• Level-Shifter
• Feedback Divider
• Voltage Regulator

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Phase-Frequency
Detector(PFD)

2009
36
PFD Block Diagram
• Edge-triggered
– Input duty-cycle doesn‟t matter
• Frequency correction takes precedence over phase correction – no
harmonic locking – 3 state operation
• Output pulse-widths proportional to phase error
• Reset delay to provide minWidth on output pulses to avoid “dead-zone”
• Symmetric NAND used to balance equalize delays from both inputs
• PFD fails as Treset approaches Tref  limit cycles
– Challenge for Gb/sec IO links
– Pulsed-flop designs can be faster
GoFaster
D
CK
Q
DFF
DLY
GoSlower
Ref
Vdd
Vdd
FB
D
CK
Q
DFF
Q
CK
D
R
R

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Example: PFD
Ref
FbClk
GoFaster
GoSlower
Vctl
Cycle Slip

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Frequency Lock Detector
• Sample PFD GoFaster signal with rising RefClk
• Sample PFD GoSlower signal with rising Fbclk
• If either sampled signal is TRUE, then PFD detected two consecutive
RefClk‟s or FbClk‟s  cycle slip and loss of frequency lock
• May apply “sticky bit” to result to capture temporary loss of lock
• Sample GoFaster/GoSlower with falling edges of RefClk/Fbclk to detect 180
degrees phase error
GoFaster
D
CK
Q
DFF
DLY
GoSlower
Ref
Vdd
Vdd
FB
D
CK
Q
DFF
Q
CK
D
R
R
CK
D Q
DFF
CK
D Q
DFF
Cycle Slip Slow
Cycle Slip Fast
PFD

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Charge Pump(CP)

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Charge-Pump Wish List
• Equal UP/DOWN currents over entire control voltage range -
reduce static phase error
• Minimize mismatch caused by finite current sources gds and
Vt mismatches
– Vt ~ 1 / sqrt(W*L)
– long L in current sources for higher rout
– Stacked (a.k.a. common) gates in Isources reduce mismatch
– use replica-bias CP and feedback amplifier to balance Iup/Idown
– beware of mismatch between two CP cells
– increase in CP‟s phase noise due to finite BW of this feedback?
• Minimal coupling to control voltage during switching and
leakage when off - reduce jitter and phase drift
• Insensitive to power-supply noise and process variations –
loop stability

2009
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Charge-Pump Wish List
• Minimize coupling caused by “clock feedthrough” (Cgd) and
charge-injection – big problem
– ½ sized dummy switches to reduce charge-injection
• Qinj ~ ½ *Cox*(W*L)*(Vgs-Vt)
– Small (and/or limited swing) switches to reduce clock feed-
through – watch for leakage with limited-swing
– Balance timing and slew rates of Up/Down inputs
• Reduce PFD pulse-width to minimize device noise while still
avoiding dead-zone (< 100 ps possible in 65nm) – noise is
band-pass filtered by PLL
• Typical Icp: 5µA (mismatch)< Icp < 300 µA (headroom)

2009
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Charge Pump: const I with amp
• Amp keeps Vds of current sources constant (Young ‟92), sinking
“waste” current when UP and/or DOWN off
– Voffset (off)  need high-gain amp
– Voffset (on)= Icp/gm  often Iamp > 3-5X Icp to reduce offset
– Both PMOS and NMOS input pairs needed for wide input range
Up
Down
Down
Vctl
Vbn
Vbp
+
-
Up_n
Down_n
Up
VirtVctl
Add cap to VirtVctl for volt. stability
Amp Ibias should track Icp

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Charge Pump: replica-feedback
• Replica-bias CP and additional amp used to set bias Vbp, forcing
Iup=Idn at low freq
– Start-up may be needed. Stability a concern
Vbn
Vpb
Vpb
Vctl
Down
Up
Vctl (or Vc1)
Vprb
Vprb
Vfb
To LPF
Main CP w/o
“Waste”
Current Path
Replica CP w/
Feedback
Amp

Charge-Pump Switching
• Panel1:
Vctl and
VirtVctl
• Panel2:
Idn drain
• Panel3:
Iup drain
• Panel4:
Up/Down
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44
Up
Down
Down
Vctl
Vbn
Vbp
+
-
Up_n
Down_n
Up
VirtVctl
Add cap to VirtVctl for volt. stability
Amp Ibias should track Icp

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Spectral Analysis of VCO Clock
• 5GHz VCO clock with 200MHz reference clock
5.0
4.7 5.3
0
-20
-40
-60
-80
Relative
Power
(dB)
Frequency (GHz)
-54.8dBc
reference
spur
0.2GHz

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46
Static Phase Error
• Causes: CP Up/Dn mismatch and/or control voltage leakage
– Jitter @ Tref (reference spurs) – leakage more serious
• In lock, net control voltage currents must integrate to zero
– Mismatch example: if UP current is 2 larger, then DOWN
current source must be on 2 as long to compensate and so
feedback clock must lead reference for DOWN to be on longer
– Terr = Tdn - Tup = Treset * (Iup/Idn – 1)
– Medium-narrow reset pulse  generally lower static error
– Leakage example: if Tref = 10ns, Ileak = 0.1uA, Icp = 10uA
– Terr = Tref * Ileak / Icp = 100ps
• Typical static phase error < 100ps

Static Phase Error
• “Green” – Up/Down Mismatch, “Red” – Leakage
• 100 ps static phase error in both cases
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2009
48
Bandgap-based Ibias
• Ib ~ Vref / R
• Vref generated from PVT-insensitive bandgap reference
• Con: feedback loop may oscillate
– capacitor added to improve stability
– resistor in series w/cap provides stabilizing zero (not shown)
• Pro: VDD-independent, mostly Temp independent
• Pro: Icp*Rlpf = constant  less PVT-sensitive loop dynamics
Ibias
Vref
Vfb
-
+ m2
m1

2009
49
Low-Pass Loop Filter (LPF)
Vctl
C1 C2

2009
50
Loop Filter Basics
• Simplest and most commonly-used loop filter is continuous-time,
passive filter (1 R, 2 C‟s) – affects stability and bandwidth
• Integrates low-frequency phase errors onto C1 cap to set avg. freq
• Resistor provides a means of isolating phase correction from
frequency correction – Icp*Rlpf for stability but R adds thermal noise
that is band-pass filtered by PLL
• C2 cap filters high-freq noise spurs caused by sampling but adds
parasitic pole at 1/RC2
• Other options include digital(FSM-based) filter, sampled-time filter
(see Maneatis, Maxim) , and continuous-time active filter
• Differential designs can reduce sensitivity to VDD and substrate
noise and often area by 2. Requires common-mode feedback loop

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Loop Filter Resistor
• Resistance may be programmable using switches
• Parasitic switch resistance varies with control voltage
– Usually lowest at Vctl extremes if CMOS transmission gate
– Large Rswitch variation vs. Vctl if NMOS or PMOS only
– Usually Rswitch < 5-10% of Rlpf
• Minimize gate leakage and noise coupling from switches
– Coupling less of a problem if using voltage regulators
• Typical values: 500Ω < Rlpf < 50k
• Poly, Diffusion, Nwell R‟s most common
• MOSFET R‟s sometimes used if R placed “below” C1 cap
– Constant Vgs needed

2009
52
Integrating Cap Configuration
• Integrating cap (C1) may be placed “above” or “below” loop filter
resistor
• Parasitic “bottom” capacitance for C1 “above” configuration
• Variable resistance if switches used in programmable resistor for
C1 “below” configuration

2009
53
Loop Filter Capacitors
• Reference capacitor to same supply as VCO V-to-I reference 
makes power supply noise common mode
• Gate Leakage in MOSFET caps can be a HUGE problem
– Exponential Ileak vs. V: Ileak~Vgate
4 (approximate)
– Weak temperature dependence
– Ileak vs. tox  ~2-3 per Angström
– Use metal caps (2-10X larger) or thick-gate (IO) oxide caps to
minimize leakage
– If MOSFET caps, accumulation mode preferred – flatter Cgate vs. V
• Ileak causes large refclk spurs (jitter) and static phase error
• Typical values:
– 5pF < C1 < 200 pF
– 1% (low phase error) < C2/C1 < 10% (low period jitter)
– Smaller C1 caps are becoming more common w/ higher reference
frequencies and metal cap usage

2009
54
Depletion-Mode MOSFET Cgate vs. V
Vgate
inversion
depletion
1.0
1.3
1.0
0.0
Simulated
C
gate
0.5

2009
55
Feed-Forward Zero: eliminate R
• Resistor in classic LPF provides an instantaneous IR on the control voltage
causing the VCO V2I to generate a current bump on the oscillator input
• Alternative: eliminate R  Add parallel CP path into V2I.
– requires parasitic cap (C2 not shown) to the proportional loop to reduce
reference spurs
– see Maneatis ‟96 for continuous time or ‟03 for sampled loop filter
• Reduces LPF phase noise? Commonly used in low phase-noise I/O apps.
CP1
Vintegral
Virtual Vctl
CP2
“Res”
Vproportional
V2I
RO
IVCO

2009
56
Dual-Loop Charge-Pump Mismatch
• Iup/Idown ratios in proportional and integral charge-pumps
are partly uncorrelated due to random device mismatch
• Net charge from integral CP must integrate to zero for stable
frequency – determines static phase error alone
• Net charge from proportional CP causes frequency kick
every PFD cycle (Kvco*I*R) caused by static error and its
own Iup/Idown mismatch
• Upshot: control voltage adjusts up or down from ideal level
to achieve correct average frequency but fVCO varies within
PFD cycle (phase wander)– need well-matched CP‟s to avoid
this effect

2009
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Dual-Loop Charge-Pump Mismatch
• Static error in integral charge-pump period jitter and
phase wander
RefClk
FbClk
GoFaster
GoSlower
Ideal Vctl Actual Vctl

2009
58
Sample-Reset Loop Filters
• Single charge-pump for Iint and Iprop – Zero ~ sqrt(C1/C2)
– e.g. Maneatis (JSSC ‟03)
• Two charge-pumps to allow for reset (discharge) delay
• Spreads phase correction over Tref – can reduce ref spurs
• Mismatch between CP‟s  significant VCO phase modulation at fref/2

2009
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Voltage-Controlled Oscillator
(VCO)

2009
60
• Ring-oscillator (RO)
– Wide frequency range
– Easy to design, integrate, and model
– Easy to generate multi-phase outputs
– Small area but high power for low jitter
– Low Q – higher jitter
• LC-tank
– Narrow frequency range
– Need field-solver tools to model inductor and accurate varactor
model
– Hard to generate multi-phase outputs
– Large area but low power
– High Q – lower jitter

2009
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Single-Sideband Phase Noise Plot
• Open-loop VCO
1/f^3
1/f^2
flicker
region
therma
l region
1/f corner
frequency
log (offset frequency)
SSB
Phase
Noise
(dBc/Hz)

2009
62
Open-Loop VCO Phase Noise
• Measured vs. offset frequency (f) from carrier
• Spectral Density of Phase Fluctuations (Sf(f))
– Sf(f)= 2L(f)
• L(f) is Single-Sideband Phase Noise (dBc/Hz)
– Analogous to Power(sideband)/Power(carrier)
• Sf(f) ~ 1 / f2
– thermal region, mid-to-high freq
• Sf(f) ~ 1 / f3
– flicker region, low freq
– Flicker noise mostly filtered by high BW PLL

2009
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VCO Phase Noise - Leeson
• L(f) = 10 log (FkT/A)*(1/8QL
2)*(fosc/f)2]
– F is the device noise factor at operating power level A
– k is Boltzmann's constant, 1.38e-23 J/K
– T is temperature (K)
– A is oscillator output power (W)
– QL is loaded Q (dimensionless)
– fosc is the oscillator carrier frequency
– f is the frequency offset from the carrier
• Valid:
– For offsets greater than the 1/f flicker corner frequency
– the noise factor at the operating power level is known
– the device operation is linear
– Q includes the effects of component losses, device loading and buffer
loading
• Source: Analog Devices: AnalogDialogue

2009
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Open-loop  Closed-Loop Phase
Noise
• Goal: determine how much open-loop VCO phase noise remains
after applying PLL feedback loop
• Method: multiply VCO‟s open-loop single-sideband phase noise by
square of PLL‟s “error function” <1- H(s)> where H(s) is closed-
loop transfer function
1/f^2
closed-loop jitter peaking
region
Modulation Frequency
Output
Phase
/
Open-loop
VCO
Phase
Error Function = 1- H(s)

2009
65
VCO Noise Tracking: Phase Error
vs. Bandwidth
• For random VCO noise (i.e. thermal):
• lower BW  more accumulated phase error
• Why? More jittery VCO cycles before feedback loop
can correct:
where Jrms = open-loop VCO RMS period jitter
n
vco
period
RMS
error J


f 
 ,

2009
66
PLL Suppression of VCO Noise
• PLL acts like a high-pass filter in allowing VCO noise to reach
output
• Need noise-immune and low-intrinsic noise VCO to minimize
jitter
– Feedback loop cannot react quickly.
– Tradeoff between tuning range & noise sensitivity
• Power-supply noise is usually largest source of VCO
deterministic jitter(DJ) if no voltage regulator. Otherwise,
largest jitter source is device noise (RJ).
• VCO power-supply sensitivity should be at least 10-20 less
than inverter

2009
67
PLL Suppression of VCO Noise
• For RO: high power, fast edges, large swing  lower device
noise and lower random jitter (RJ)
– Jrms (open-loop period) ~sqrt(kT/2NC) / (fvco*Vswing)
• where N=#of stages, C=cap/stage
• Match rise/fall times, inter-stage delays to minimize phase
noise (lowers ISF)
• RMS random jitter (kT) < 0.02% - 0.2% VCO period
(typical)

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RO VCO Gain
• Typical VCO gain: Kvco ~ 1-3 * fmax. May vary w/PVT by > 2
– need frequency range: >2 to allow for PVT
– desire constant gain over most of usable control voltage range
– use digital calibration to reduce : Kvco variation
VCO
frequency
Control Voltage
Usable Vctl
Range

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Achieving Low RO VCO Gain
• Goal: low gain and wide frequency range allows for low PLL BW
and/or can help filter charge-pump and resistor noise
• Make VCO frequency a function of TWO control paths
– Fast-path: low Kvco – connect to normal loop filter path
– Slow-path: high Kvco – connect to secondary control path with low BW
(<< 1/10 PLL BW) – requires stable refclk frequency
• Loop dynamics are determined mostly by fast-path – model in H(s)
• Slow-path RC filter added to normal loop filter
– Can connect Rslow to C1 cap instead of C2 cap.
– Add unity-gain buffer if Vslow leakage is high
– Increases lock time w/o additional logic and switches
– Techniques to reduce lock-time can cause instability

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• Barkhausen criteria for sustained oscillation
– loop gain must exceed 1, loop phase must equal 360°
– more RO delay stages  easier to initiate oscillation
– gain(DC) > 2 for 3 stages, gain > sqrt(2) for 4 stages

2009
71
VCO w/current-starved
inverters(CSI)
• RO VCO usually consists of two circuits
– bias generator (e.g. Vctl to Ictl)
– voltage or current controlled ring oscillator (RO)
• Usually odd # of stages (usually 5+). Even # ok if differential RO
• Feedback INV  usually weaker by > ~3-4
• Tune frequency by adjusting “VDD” of inverters – changes delay
• “Vdd” for inverters is regulated output of VCO V2I
weak
weak
weak

2009
72
Generic V-to-I for CSI RO
• Bias circuit for current-starved inverter-based RO. Start-up necessary.
• Feedback amplifier provides good low-freq power-supply rejection
• Caps to Vdd and Vss provide good high-freq rejection but add parasitic
poles  e.g., p1 = 1/(Rro*Cvro), p2 = 1/(Ramp*Ccomp)
• Programmable mirror-ratio (M) allows for programmable Kvco, wider
frequency range, and lower phase noise
• Dual-control path: fast/slow LPF or feed-forward zero LPF
• Adding source-degeneration resistors to current sources may reduce
device noise
• Stability – disturb ckt w/narrow transient pulse – FFT(delta function) 
white noise. Hard to model RO impedance in AC stability sims

2009
73
V2I for CSI RO (V. von Kaenel (JSCC ‟96)
• Bias circuit for current-starved inverter-based ring oscillator
• Feedback  amp provides good low-freq power-supply rejection
• Caps to Vdd and Vss provide good high-freq rejection but add
parasitic poles  e.g., p = 1/(Rro*Cn)
• Start-up necessary. Stability a concern
Ivco
Vctl
_
+ m1 m2
Vfb
m3
Cp
Cn
Rfb
Rro
model of
CSI RO
model of V2I

2009
74
Diff-Amp VCO w/Replica-Bias V2I
• Vswing = Vctl (Maneatis ‟96)
• Amp provides DC power-supply rejection
• Stable, but getting high BW and good PSRR tricky
• Start-up necessary
+
-
Vfb
Vbn
m1 m2
m5
m3 m4
m6 m7
Vctl
Vctl
Dummy delay cell
+
-
+
-
3-stage RO
Vctl
Vbn
+
-
+
- +
-
+
-
Cn

2009
75
VCO w/Feed-Forward Path
• RO delay stage may receive inputs from multiple prior stages (e.g. N-1 and
N-2)
– allows N-stage VCO to oscillate at speeds otherwise attainable only by
reducing # of stages
– easier to implement with differential signals
– extra care must be taken to ensure that RO will safely oscillate
+
-
+
-
+
-
S
F
+
-
+
-
+
-
S
F
+
-
+
-
+
-
S
F
+
-
+
-
+
-
S
F
S= slow path F = fast path

2009
76
Quadrature Output Clocks
• Quadrature clocks (0°, 90°, 180°, 270°)
– requires 4 delay stages or
– divide “differential” VCO outputs by 2, then delay one set of
divided outputs by ½ Tvco to generate quadratures. Allows any
# of delay stages
div_0
D
CK
Q
DFF
QB
div_180
D
CK
Q
DFF
QB
vco
vco_x
div_90
div_270

2009
77
LC VCO
• Pros
– Low jitter / phase noise performance
– If L & C are modeled correctly, frequency prediction is good
• Cons
– Limited tuning range
– Area (inductor)
– Inductor is a not supported at many companies
– Accurate varactor model is challenging
• Key design considerations
– Keeping noise sources quiet
– Varactor choices
– Tuning range vs. noise performance
– Oscillation amplitude control

LC VCO Schematic
2009
78
tail bias (analog)
fine-tuning control (analog)
differential
inductor
coarse-tuning control (digital){
varactor
for coarse
frequency
tuning
MCAP-AC for
coupling tank
oscillation to
output buffer
CMOS
output levels
output
buffer
varactor
for fine
frequency
tuning
RP LP CP
Iin
P
P
P
C
L
1


Two back-to-back inverting
stages with LC filtering to
amplify noise only at resonant
frequency & kill DC gain to
prevent latching

LC VCO
2009
79
R
s
C
s Ls
Cpa
1
Rp1//C
p1
Rp2//C
p2
Cpa
2

2009
80
LC VCO Design Concerns
• Thermal noise of parasitics tuning L & C parasitics
• Device noise of cross-coupled –gm devices (mostly thermal
noise)
• 1/f noise of tail (upconverted to fundamental via mixer
action)
• L needs to add dummy fingers to pass metal density rules
• Fingers oriented orthogonally to inductor turns to minimize
parasitic eddy currents from magnetic coupling
• Fingers staggered between Mn & Mn+1 to reduce CMP
topography
• Need symmetry in inductor underpass connections
• Need to account for high-frequency effects (proximity/skin
effects, dielectric loss, etc.) in inductor

Setting LC VCO Tailbias
2009
81
• Tail biasing sets oscillator current
• Need enough current to create enough gm in cross-coupled
devices to overcome resistive losses in tank in order to start
up initial oscillation and sustain oscillation
• Can set with static control or local amplitude-control loop
• Ramp tailbias down, i.e., slowly kill oscillator gain & check
when oscillations die out (defined when peak swing falls below
0.1V)

2009
82
LC VCO Temperature Effects
Metal TCR affects oscillation frequency when inductor Q is
limited
RL
L
RC
C









 2
2
2
1
L
R
L L
 







 2
2
2
1
C
R
C
C

LC
R
L
C
R
L
C
LC
C
L
res
1
1
1
1
2
2







2009
83
VCO Level-Shifter
• Differential-pair without tail current
• Need sufficient gain at low VCO frequency – use low-Vt NMOS
• Use NMOS input pair if VCO swing referenced to VSS for better
power-supply rejection – often low Vt for wider input range
• For best duty-cycle, use two instances of level-shifter (swap
inputs), and couple complementary outputs with weak inverters
• Typical duty cycle: 50 ± 3% with random mismatch
in
z
m1a m2a
ip
m3a m4a
ip
zn
m1b
m2b
in
m3b
m4b
weak INV
weak INV

2009
84
AC-Coupled VCO Level-Shifter
• Can‟t pass low-frequency clock due to AC-coupling
• Caps decouple VCO common-mode from level-shifter input
common-mode
• Large resistors bias input inverters at trip-point w/o attenuating
gain
• Parasitic capacitance at input of first inverters attenuates AC
signal
• Typical duty cycle: 50 ± 3% with random mismatch

2009
85
Feedback Divider

2009
86
Feedback Divider (FBDIV)
• Typical Implementation: programmable, synchronous digital counter
• Max FBDIV frequency should be greater than max VCO frequency to avoid
“run-away” - beware of Synthesized, Placed & Routed designs
• Counter output may glitch  re-sample with VCO output to clean up glitch,
reduce latency and phase noise
• Loop Phase Margin Degradation ~ c*Tfbdly
– usually insignificant (a few degrees)
• Divider may be internal to PLL or after clock tree to cancel clock tree skew
• May provide additional output signals used to deterministically synchronize
tester controls to VCO clock and/or walk signals between various on-chip
clock domains

2009
87
Fractional-N Dividers
• Divide VCO clock by non-integer value to allow for finer
frequency resolution
• Dual modulus: N, N+1
– Vary divisor from N to N+1 at various rates, duty-cycles
to achieve intermediate value
– Requires delta-sigma modulation to reduce/re-shape
noise spurs (move to higher frequency)
– PLL feedback loop filters high-frequency spurs
• Complementary Approach: multi-phase VCO outputs
– e.g. 8 or 10 output phases
– Feedback clock period can be adjusted by less than one
VCO clock
– More power, lower fmax for multi-phase VCO

2009
88
Voltage Regulator
• Provides stable, PVT-insensitive, clean power-supply for PLL
– lower jitter, phase noise
– more stable loop dynamics, VCO range, etc.
– aim for > 30dB PSRR, definitely > 20dB
• Uses bandgap reference to set voltage and bias current
levels
• Two voltage regulators sometimes used
– High VDD for charge-pump (analog) and lower VDD for VCO
– “Quiet” for analog (CP, VCO bias) and “Dirty” for digital (PFD,
FBDIV)

2009
89
Voltage Regulator
• Requires higher power-supply (e.g., 1.8V  1.2V)
• Wastes current
– higher VDDA and bandgap/regulator over-head (0.5-3mA).
– aim for current overhead < 20%. <5% is achievable in some
apps
• Regulator area (inc. bandgap) is small compared to
decoupling cap area
– Area (MOSFETs, Rpoly, diodes) ~ 70 x 70 µm2 (65nm)
– Area (DECAPs) ~ 125µm x 125um for 100pF (65nm)
– Typical cap ~ 30-300pF
• Vt-mismatch in bandgap amplifier input pair dominates
overall regulator mismatch
– 3mV offset at amp ~20mV variation at output
– Goal < 25mV 1-s variation from device mismatch
– Goal < ±5mV PVT variation (due mostly to diodes)

2009
90
Voltage Regulator
• Hard to stabilize over wide Iload and Cload ranges
• NMOS source-follower output stage
– Requires more headroom
– Faster response and easier to stabilize
• PMOS common-source output stage
– Can handle larger current loads  larger Vgs

2009
91
Digital PLL‟s

2009
92
What is a Digital PLL?
• Replace charge-pump (time error-to-charge) with
TimeError-to-Digital Converter
• Replace loop filter with discrete-time digital filter (usually 2nd
or 3rd order sigma-delta)
• Replace voltage-controlled VCO with digital-control (vary cap
load, interpolation, etc.)
• Are analog components “allowed”? Voltage regulator?
Analog current-steering DAC for VCO?
• Sampled-system modeled in the Z-domain

2009
93
Why a Digital PLL?
• Replaces process and noise-sensitive analog circuits with
digital equivalents – advances on work with digital DLL‟s
• Increases PLL design portability and testability
• Takes advantage of area scaling with nm devices
• Greater flexibility in loop bandwidth – don‟t need huge
capacitors for low BW
• Increases ability to test and observe. e.g. open-loop, disturb
loop
• Fast behavioral simulation
• “Good-enough” for frequency synthesis applications
• ISSCC presentations: TI(„04) and IBM („07)

2009
94
Why NOT a Digital PLL?
• Often not “good enough” for phase-tracking applications
• VCO frequency has finite frequency resolution (e.g. 10-14
bits). May use coarse DAC if high-frequency dithering
available
• VCO has limited range – requires range control and/or
calibration
• VCO may have poor noise rejection if purely digital
frequency control and no voltage regulator (usually analog)

2009
95
Why NOT a Digital PLL?
• Need high-frequency over-sampling clock for sigma-delta
loop filter – VCO? Refclk? Start-up problem?
• TimeError-to-Digital Converter is hard – poor resolution,
high power – usually < 5 bits
– Bang-bang is an alternative (IBM)
– FbDiv internal state contains phase error information
• Digital filter generates large noise spurs, possibly inducing
jitter, and dissipates more power than passive loop filter
– Requires delta-sigma modulation to reduce spurs
• Generating proportional correction can be tricky

2009
96
Phase Noise to Jitter

2009
97
Phase Noise and Timing Jitter
• Phase Noise (frequency domain)  Jitter (time domain)
• Noise is frequency-dependent with random & deterministic
components
• VCO and loop filter resistor often largest sources of noise
time
f
   
 
t
t
f
t
V n
out
out f
 
 2
sin
Frequency Domain
Time Domain
phase
noise
jitter
vs.
vs.
PLL Output
fout fout

2009
98
Timing Jitter: Eye Diagram
• Example of timing jitter in serial link.
• Overlay scope traces of several bits on top of each other
timing jitter

2009
99
Jitter Definitions
• Phase Jitter (sec)
– deviation of VCO output edges from ideal placement in time.
– specified over a time interval or frequency range.
– important for I/O apps (e.g. PCI-Express < ±1.5ps RMS)
– measure with spectrum analyzer or scope with jitter package
• Period Jitter (sec)
– deviation of VCO period from ideal period
– derivative of Phase Jitter with respect to time
– peak-to-peak period jitter (Jpp) is max VCO period – min VCO period
– most important for CPU-like apps
– e.g. 10-20ps for 2GHz CPU clock
– easily measured on scope – self-triggered infinite-persistence or jitter
package
• Cycle-to-Cycle Jitter (sec)
– change in VCO period from cycle N to cycle N+1
– derivative of Period Jitter with respect to time
– not important for CPU-like apps

2009
100
Jitter Definitions
• TIE (sec)
– time difference between total of N-consecutive actual VCO cycles and
N ideal cycles
– easily measured on oscilloscope with jitter package – self-triggered
measurement
– TIE – “time-interval error”

2009
101
Noise Sources
• Major internal PLL Noise Sources
– VCO oscillator(mostly thermal) – very significant
– VCO bias (flicker and thermal) – very significant
– Loop filter resistor (thermal)
– Charge-pump (flicker (1/f) and thermal)
– Flicker Noise
• Vn
2 (V2/Hz) = Kf / (Cox*W*L* f)
• Kf ~ 10e-24 – PMOS often lower than NMOS
– Thermal Noise
• In
2 (Amp2/Hz) = 4kT*gm*g
g ~ 2/3 for older CMOS technologies, much higher in deep
submicron
• PLL feedback loop
– Low-pass filters ref and charge-pump noise
– Band-pass filters loop-filter resistor noise
– High-pass filters VCO noise (1-H(s))

2009
102
Converting Phase Noise to Jitter
• RMS Phase Jitter
• S(f) 2*L(f) where L(f) is single-sideband phase noise
– To convert to dBc/Hz, use 10log10(L(f))
• Easily measured using spectrum analyzer – low noise floor
• Ideal reference is measurement trigger
• Integration range depends on application (e.g. PCIe: fmin= 1.5MHz)
– usually stop integration at f0/2 to avoid capturing carrier and
harmonics
– e.g., 5ps from 1MHz to f0/2 with BW=15MHz and 2.5GHz clock (SOI
bad for phase jitter)
 df
f
S
f
J
vco
phase 
 f

2
1

2009
103
Converting Phase Noise to Jitter
• RMS Period Jitter
• Spectrum analyzer can‟t do this integral. Post-process
phase noise
– e.g., Jper~300fs w/2.5GHz clock
• Usually dominated by VCO bias and VCO?
• Spectrum analyzer usually has lower noise floor than
scope (scope floor ~800fs @ 40Gsample/sec)
  df
f
f
f
L
f
J
vco
vco
period 







 


2
sin
8
2
1

2009
104
Converting Phase Noise to TIE
• Time-Interval Error (TIE)
• “Tau” is time interval over which phase drift is measured
• Spectrum analyzer can‟t do this integral. Post-process
phase noise
• JTIE (Tau)= sqrt(2) * Jphase where Tau=1/fstart and fstart is
the starting frequency for both integrations
   df
f
f
L
f
J
vco
TIE 


2
sin
8
2
1



2009
105
Circuit Verification

2009
106
PLL Floorplan
RO
RO
LS
VRO CAP
VCO V2I + BiasCkt
VCO
Bias
Comp
Cap
PFD
Charge Pump
VCO
Post-
Div
FbDiv
Bypass
Mux
+
Buffers
Control Logic
+
Test Logic
Bandgap
Ref
Voltage
Regulator
LPF C2 MetCap
LPF C1 MetCap
VDD
Decap
"Quiet" Regulated VDD
Decap
"Quiet" Regulated VDD
Decap
VDDreg

2009
107
Noise Isolation
• Check extracted netlist for coupling of switching signals onto
sensitive analog signals (e.g. REFCLK  Vctl)
• Check that LPF metal caps are present and well-connected
to correct power supplies
• Check that VSS of LPF metal caps and VSS of VCO bias
circuits are well-connected and at same potential
• Check that correct shields for sensitive signals are in place
and well-tied to correct power supplies

2009
108
Noise Isolation
• Account for parasitic capacitance to substrate in “NWELL”
decaps, diodes, and well/diffusion resistors
• Add guard rings as applicable
• Buffer control signals and programmable inputs locally
before use
– avoids problem where VSS of control signal doesn‟t
match local VSS where signal is used
– filters coupling/glitches on long routes

2009
109
Signal EM / ESD
• Inspect wires that conduct DC current and wires that drive
large switching output loads for EM violations (e.g. charge-
pump bias, output clocks)
• Check that signal ESD and/or power supply clamps are well-
connected to power supplies (< 1-2 Ω)
– extract power grids and ESD
– simulate for voltage peaks and diodes wired-backward

2009
110
Power-Grid IR
• Aim for avg IR drops < 5mV over entire PLL, less within and
between related analog blocks
• Decoupling capacitors surround large, switching buffers to
reduce IR drops and are well-connected to grid
• Check for isolated power domain islands
• Plan power domains and level-shifter placement up-front

2009
111
Switching Signals
• Match differential signals – total capacitance and coupling
(e.g. up, up_x, dn, dn_x, clk, clk_x)
– try to match total capacitance < 1-2%
• Maintain fanout (incl. Wires) < ~6 on high-speed paths, <
~10 on DC paths (e.g. encode/decoders)
– reduces crow-bar current and noise glitches
• Setup/Hold checks in PFD, Feedback Divider, and Post-VCO
divider. Needs lots of margin for FBDIV to account for
overshoot, aging, etc.
– strive for FBDIV faster than VCO(max)

2009
112
PLL Instantiation – Checks
• Mismatch on differential signals
• Coupling into refclk, output clocks
• Possible glitches on control inputs
• Signal routes over sensitive areas of PLL (VCO, loop filter,
charge-pump)
• Large buffers on edge of PLL that may inject noise in
substrate (keep-out requirement?)

2009
113
PLL Instantiation – Checks
• Output wires wide enough to handle current load (EM)
• Rise/fall times on inputs/outputs – add maxcap limit into
timing file to flag heavy loads - RC delays
• VDDA/test signal routes to bumps and/or ESD
• VDD/ VSS power supply connections

2009
114
Functional Modes
• Power-Down/Reset/Test Modes
– chicken-and-egg start-up problems – esp. level-shifters, boot-
strapped regulators
– Contention?
• measure current in every device in these modes
• SLOW clock mode
– drive slow output clock at power-on to remove contentious
states in downstream logic
– disable any clock gaters
– mux in separate ring oscillator or force VCO/post-VCO div to
produce low frequency clock in open-loop mode
– avoid glitches when entering/leaving SLOW mode
• Frequency Hopping
– Ensure that FBDIV can‟t fail during frequency transition if
RESET not applied

2009
115
Power/Clocking Domains
• Level-shifters are present when crossing power domains and
are connected to correct supplies
– apply writability analysis with mismatch
– check for overstress
– easy to miss
• Add synchronizers or “walk clocks” when crossing clock
domains – easy to miss
• Check metastability on flops, comparators – is there a
failure mechanism? Calculate MTBF.
• Insert bypass mode mux, preferably such that if the
regulator fails, bypass clock still propagates to output

2009
116
RTL vs. Circuit
• Add assertions to RTL model to flag illegal input states
• Verify that RTL and tester don‟t assume that dividers, etc.
are initialized to known states upon power-on, frequency-
changes, etc. – add logic to establish determinism if needed
• Model/verify all digital logic in RTL
• Specify expected input states at boundaries of all analog
blocks in various operating modes
• Take special care with calibration algorithms outside PLL
• Simulate PLL exhaustively in VerilogA, Nanosim, etc, if
possible

2009
117
RTL vs. Circuit
• Look for incorrect polarity on input control signals (e.g.,
reset, powerDown) and REFCLK
• Look for glitches on feedback clock and other dividers
• Exercise all divider/counter states
• Check for possible VCO run-away conditions during power-
on and frequency changes (e.g., no reset or feedback
divider is halted)
• Verify that unselected inputs of muxes in critical signal paths
are gated (e.g., VCO post-divider muxes)

2009
118
Behavioral Simulations
• Behavioral simulation –before detailed circuit design define
requirements for each block – e.g. PLLUS, Simulink
• Develop/verify jitter budget – e.g. PCI-Express
• Estimate VCO frequency overshoot
• Loop bandwidth vs. reference noise suppression
• Simulate effects of VCO gain variation, loop filter leakage,
charge-pump mismatch, feedback delays, OSR, spread-
spectrum tracking, Vctl-sensitive loop parameters, PFD dead-
zone, parasitic poles

2009
119
Circuit Simulations
• Start-up circuit safety margin - bandgap, VCO, regulators
• Stability of all internal feedback loops
– AC and transient impulse response (ringing)
– e.g., bandgap, regulator, charge-pump bias, VCO bias
– Phase margin, gain margin, # of rings
• VCO - RO stage delays rise vs. fall, stage-to-stage – lower
ISF
• Level-shifters‟ possible corruption of duty-cycle
• Switching-induced noise spikes on regulated power supplies
• Current dissipation in power

2009
120
Circuit Simulations
• PSRR of voltage regulators, ability of regulators to meet
fast-changing current load
• Step reference phase, observe PLL re-lock
– overshoot, relock time
• Simulate entire sequence from power-on to lock
– sanity check

2009
121
Devices/Circuits
• Estimate effects of Vt mismatch BEFORE starting layout
(monte carlo, dVt ~ 1/sqrt(W*L) )
– most sensitive: bandgap, charge-pump, other low I ckts
• Estimate loop parameter variations, static error, reference
spurs due to PVT and mismatch before starting layout
– Kvco, Icp, R, C1 (also vs. Vctl) – esp. dual- charge-pump
designs
– circuit techniques to minimize effects: self-bias,
Icp*Rlpf=const
– self-bias not as effective if not all devices the same Leff
• Diode current density (bandgap) – ideality factor may be
sensitive to current density – stay away from cliff

2009
122
Device Reliability
• Gate Overstress
– especially likely during power-down, reset, test
– hspice .biaschk is useful
• Gate Leakage
– LPF especially, Ileak(LPF) < a few nA
– Switches used for test modes
– Gate loads of high-impedance nodes (e.g. bandgap)
– Large op-amp inputs

2009
123
Device Reliability
• Check PMOS devices for NBTI-sensitivity and NMOS devices
for PBTI-sensitivity
– Vgs of matched devices should be the same at all times,
even when not selected (e.g. current-steering DAC) –
don‟t place switches closest to supply rails
– switching circuits such as VCO and FBDIV should have
enough frequency headroom to allow for aging. High Vgs
is bad! 10-20% margin?
– effects worse at sub-90nm and may not be well-
modeled

2009
124
Lithography/Devices
• Add dummy poly to reduce ACLV (across chip linewidth
variation), esp. in Lmin devices
• Maintain gate poly on fixed pitch in same orientation to
reduce ACLV (esp. in Lmin devices)
• Try to maintain constant poly density – e.g. no large caps
next to sensitive Lmin devices)
• Add dummy devices if stress/strain is applied and matching
is required (e.g., charge-pump)

2009
125
Tips for Design for Test
• Measuring Jitter and Phase Error
• Measuring Loop Dynamics
• Analog Measurements
• Probing

2009
126
Getting Clocks from PLL to Board
• Differential I/O outputs highly desirable to reject common-
mode noise – use fastest, lowest-latency I/O available
• Divide VCO to reduce board attenuation only if necessary
 make divider programmable
• Measuring duty-cycle
– add mux to select either true or inverted VCO clock
– Duty-cycle error = (Duty+ - Duty-) / 2
– E.g. Duty(true) = 56%, Duty(inv) = 54% Error=1%

2009
127
Getting Clocks from PLL to Board
• Ability to disable neighboring I/O when measuring jitter
• Observe REF, VCO, and FBCLK. Gate all but the observed
clock at the inputs of the clock observation mux to minimize
coupling between clocks
• Phase error measurement: trigger scope on REFCLK on
board. Capture internal REFCLK and FBCLK in infinite
persistence. Measure difference between internal REFCLK
and FBCLK on same pin.

2009
128
Measuring Loop Dynamics
• Modulate reference phase at various modulation frequencies
and measure VCO phase using TIE
– used to construct closed-loop transfer function
• On-chip state-machines
– range from simple to sophisticated
– disturb locked PLL in some way and observe re-lock
behavior

2009
129
Analog Measurements
• Need ability to measure key internal analog
signals without injecting noise
– Loop filter control voltage
– Ring Oscillator regulated supply
– Bandgap reference
– Regulated power supplies
– Charge-pump bias voltages and currents
• Metrics
– Measurement BW ~ PLL Bandwidth or less
– Accuracy ~ 5mV?
– Programmable via JTAG

2009
130
Analog Measurements
• Internal A/D
• Can be fairly slow
• Minimize mux switch leakage into A/D front-end
• Minimize coupling to sensitive signals
• May require external analog pin for calibration
• Compare analog voltage to internally-generated
voltage reference
• Use state-machine to minimize # of comparators to
save area
• Disable when not in use to save power

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Analog Measurements
• Analog Observation Pins
• Force or sense voltage/current
• Low BW – high impedance analog signals and high parasitics
• Need ESD (HBM,CDM) to protect signals –watch for leakage
• Can wire-OR analog observation pins from several PLL‟s but watch
for increased pin leakage causing IR drops across pass-gates (e.g.,
3-6kΩ) or causing high-impedance analog signals to droop
• Buffer control voltage before sending off-chip to prevent leakage
and extra load from upsetting feedback loop – watch for gate
leakage in unity-gain buffer

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Analog Measurements
• Two-level transmission-gate analog mux connects analog
signals to outside world
• Pull-down to VSS middle node of two-level mux when not in
use to minimize coupling of noisy pin to analog signals (at
expense of increased leakage).

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Probing On-chip (last resort!)
• If not flip-chip, then put probe pads on top-layer metal
• Probe pad size >1µm  1µm. Prefer > 2µm  2µm
• Place probe pad on a side-branch of analog net to avoid
breaking wire with probe
• Separate probe pads to allow room for multiple probes
• FIB: can add probe pad, add or remove wires
– need room and luck

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Summary: Uncle D‟s PLL Top 5 List
1. Maintain damping factor ~ 1 for low period jitter apps
2. VDD-induced and intrinsic VCO noise – loop can‟t do the
work for you
3. Leaky loop filter gate caps will cost you your job
4. Make FBDIV run faster than VCO
5. Observe VCO, FBCLK, REF, clkTree on differential I/O pins –
you can‟t fix what you can‟t see!

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Special thanks to Alvin Loke for
allowing to me “borrow” some of his
diagrams and ideas for this talk…which
ones? The good ones

2009
136
References

2009
137
Paper References
[1] B. Razavi, Monolithic Phase-Locked Loops and Clock-Recovery Circuits, IEEE Press,
1996. – collection of IEEE PLL papers.
[2] I. Young et al., “A PLL clock generator with 5 to 110 MHz of lock range for
microprocessors,” IEEE J. Solid-State Circuits, vol. 27, no. 11, pp. 1599-1607, Nov.
1992.
[3] J. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased
Techniques,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723-1732. Nov.
1996.
[4] J. Maneatis, “Self-Biased, High-Bandwidth, Low-Jitter 1-to-4096 Multiplier Clock
Generator PLL,” IEEE J. Solid-State Circuits, vol. 38, no.11, pp. 1795-1803. Nov.
2003.
[5] F. Gardner, “Charge-pump phase-lock loops,” IEEE Trans. Comm., vol. COM-28, no.
11, pp 1849-1858, Nov. 1980.
[6] V. von Kaenel, “A 32- MHz, 1.5mW @ 1.35 V CMOS PLL for Microprocessor Clock
Generation,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1715-1722. Nov.
1996.
[7] I. Young, “A 0.35um CMOS 3-880MHz PLL N/2 Clock Multiplier and Distribution
Network with Low Jitter for Microprocessors,” Proc. ISSCC 1997, pp. 330-331.
[8] J. Ingino et al., “A 4-GHz Clock System for a High-Performance System-on-a-Chip
Design,” IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 1693-1698. Nov. 2001.
[9] A. Maxim et al., “A Low-Jitter 125-1250 MHz Process-Independent CMOS PLL Based
on a Sample-Reset Loop Filter,” Proc. ISSCC 2001, pp. 394-395.
[10] N.Kurd et al., “A Replica-Biased 50% Duty Cycle PLL Architecture with 1X VCO,”
Proc. ISSCC 2003, pp.426-427.
[11] K. Wong, et al., ”Cascaded PLL Design for a 90nm CMOS High Performance
Microprocessor,” Proc. ISSCC 2003, pp.422-423.

2009
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Paper References
[12] M. Mansuri, et al., “A Low-Power Adaptive-Bandwidth PLL and Clock Buffer With
Supply-Noise Compensation”, IEEE J. Solid-State Circuits, vol. 38, no.11, pp. 1804-
1812. Nov. 2003.
[13] A. Maxim, “A 160-2550 MHz CMOS Active Clock Deskewing PLL Using Analog Phase
Interpolation,” Proc. ISSCC 2004, pp. 346-347.
[14] J. Lin et al, “A PVT Tolerant 0.18MHz to 660MHz Self-Calibrated Digital PLL in 90nm
CMOS Process,” Proc. ISSCC 2004, pp. 488-489.
[15] J. McNeill, “Jitter in Ring Oscillators,” IEEE J. Solid-State Circuits, vol. 32, no.6, pp.
870-878, Jun. 1997.
[16] A. Abidi, “Phase Noise and Jitter in CMOS Ring Oscillators,” IEEE J. Solid-State
Circuits, vol. 41, no.8, pp. 1803-1816, Aug. 2006.
[17] L. Dai et al., “Design of Low-Phase-Noise CMOS Ring Oscillators,” IEEE Trans.
Circuits and Systems-II: Analog and Digital Signal Processing, vol. 49, no. 5, pp.
328-338, May 2002.
[18] U. Moon et al., “Spectral Analysis of Time-Domain Phase Jitter Measurements,” IEEE
Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 49, no. 5,
pp. 321-327, May 2002
[19] J. Kim et al., “Design of CMOS Adaptive-Bandwidth PLL/DLLs: A General Approach,”
IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 50,
no. 11, pp. 860-869, Nov 2003.
[20] T. Toifl et al., “A 0.94-ps-RMS-Jitter 0.016-mm2 2.5-GHz Multiphase Generator PLL
with 360 Degree Digitally Programmable Phase Shift for 100Gb/s Serial Links,” IEEE
J. Solid-State Circuits, vol. 40, no.12, pp. 2700-2711, Dec. 2005.
[21] S. Wedge, “Predicting Random Jitter,” IEEE Circuits & Devices Magazine, pp. 31-38,
Nov/Dec 2006.
[22] A. Rylyakov et al., “A Wide Power-Supply Range (0.5V-to1.3V) Wide Tuning Range
(500MHz-to-8GHz) All Static CMOS AD PLL in 65nm CMOS SOI,” Proc. ISSCC 2007,
pp. 172-173.

2009
139
Paper References
[24] R. Staszewski et al, “All-Digital PLL and Transmitter for Mobile Phones,” IEEE J.
Solid-State Circuits, vol. 40, no.12, pp. 2469-2482. Dec. 2005.
[25] R. Staszewski et al, “All-Digital PLL with Ultra Fast Settling,” IEEE Trans. On Circuits
and Systems II: Express Briefs, vol. 54, no.2, pp. 181-185. Feb. 2007.
[26] V. Kratyuk et al, “A Design Procedure for All-Digital Phase-Locked Loops Based on a
Charge-Pump Phase-Locked-Loop Analogy,” IEEE Trans. On Circuits and Systems II:
Express Briefs, vol. 54, no.3, pp. 247-251. Mar. 2007.
[27] J. Hein et al, “z-Domain Model for Discrete-Time PLL‟s,” IEEE Trans. On Circuits and
Systems, vol. 35, no.11, pp. 1393-1400. Nov. 1988.

2009
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Monograph References
[1] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.
[2] R. Best, Phase-Locked Loops, McGraw-Hill, 1993.
[3] R. Dorf, Modern Control Theory, 4th Edition, Addison-Wesley, 1986.
[4] P.Gray and R. Meyer, Analysis and Design of Analog Integrated Circuits, 3rd Edition, J.
Wiley & Sons, 1993.
[5] K. Bernstein and N. Rohner, SOI Circuit Design Concepts, Kluwer Academic Publishers,
2000.
[6] A. Hajimiri and T. Lee, The Design of Low Noise Oscillators, Kluwer Academic
Publishers, 1999.
[7] T. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge
University Press, 1998.
[8] F. Gardner, Phaselock Techniques, 3rd Edition, New York, Wiley & Sons, 2005.

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PLL Failures

2009
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PLL Failures
• Observation is that VCO frequency is pinned at max value.
Can‟t observe Vctl or feedback clock. VCO fails to oscillate at
low frequency because of insufficient gain in 3-stage VCO.
When VCO finally starts, FBDIV can‟t keep up, causing “run-
away” Solution: increase gain of delay stage and FBDIV
speed.
• VCO “run-away” when re-locking to higher frequency due to
VCO overshoot and slow FBDIV.
• VCO loses lock occasionally at low frequencies. Due to
insufficient VCO level-shifter gain. Dropped VCO edges.
Required real-time scope for debug
• High jitter at low VCO frequencies due to Vctl approaching
Vt of V2I current source. Solution: operate VCO at 2X.

2009
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PLL Failures
• Occasional high deterministic jitter caused by coupling into
PLL‟s VDDA bondwire.
• Extremely high period jitter – caused by incorrect wiring of
8-bit charge-pump setting. Bandwidth much too high.
Verilog model did not check for legal input settings.
• PLL won‟t start-up at low temp due to weak start-up circuit
in voltage regulator and lack of simulation at corners with
slow VDDA ramp-rate.
• PLL period modulated strongly by 400MHz signal, resulting
from oscillating internal feedback loop in VCO bias ckts.
Ultimate cause, fab misprocessing of compensation cap and
insufficient margin in ckt.

2009
144
PLL Failures
• Metastability condition corrupted digital loop filter due to
slow devices, low Vdd, and insufficient design margin.
• Digital VCO out-of-range due to resistor mis-processing.
Solution: fusable chicken-bits to adjust frequency range.
• Race condition in digital loop filter caused by missing
synchronizers in clock domain crossing.

2009
145
PLL Failures
• CDM ESD failures of analog measurement pins – no visual
inspection and no extraction/simulation of connection to
VSS.
• Duty-cycle corruption (> 57%) – caused by unbalanced
fanouts in delay stages after VCO – exacerbated by single-
ended clocking.
• Contention in analog observation signals due to ESD diodes
wired backward and control logic bugs.
• Inconsistent duty cycle. Failure to initialize state in post-VCO
divider exposed VCO duty-cycle error.

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