Power-Awarness in Coarse-Grained Reconfigurable Designs: a Dataflow Based Strategy

Francesca Palumbo
Università degli Studi di Sassari
PolComIng – Information
Engineering Unit
2014 IEEE International Workshop on gnal rocessing ystems
October 20 – 22 2014, Belfast, UK
and Luigi Raffo
DIEE – Dept. of Electrical and Electronics Eng.
EOLAB - Microelectronics and Bioeng. Lab.

OUTLINE
• Introduction
– Problem statement
– Background
– The power issue
• Automatic Power-Awareness Strategies
– Baseline Multi-Dataflow Composer
– Static Power: Structural Optimization
– Dynamic Power: Behavior Optimization
• Performance Assessment
– Design Under Test
– Structural Evaluation
– Behavior Evaluation
• Final Remarks and Future Directions
SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau2

OUTLINE
• Introduction
– Background
– The power issue

PROBLEM STATEMENT
CONSUMER NEEDS:
• HIGH PERFORMANCES real time applications:
– Media players, video calling...
• UP-TO-DATE SOLUTIONS
– Support for the last audio/video codecs, file formats...
• MORE INTEGRATED FEATURES in mobile devices:
– MP3, Camera,Video, GPS...
• LONG BATTERY LIFE
– Convenient form factor, affordable price...

PROBLEM STATEMENT
CONSUMER NEEDS:
• HIGH PERFORMANCES real time applications:
– Media players, video calling...
• UP-TO-DATE SOLUTIONS
– Support for the last audio/video codecs, file formats...
• MORE INTEGRATED FEATURES in mobile devices:
– MP3, Camera,Video, GPS...
• LONG BATTERY LIFE
– Convenient form factor, affordable price...
POSSIBLE SOLUTION:
• DATAFLOW MODEL OF COMPUTATION
– Modularity and parallelism  EASIER INTEGRATIONAND FAVOURED RE-USABILITY
• COARSE-GRAINED RECONFIGURABILITY
– Flexibility and resource sharing  MULTI-APPLICATION PORTABLE DEVICES

BACKGROUND
DATAFLOW FORMALISM
• Directed graph of actors
(functional units).
• Actors exchange tokens (data
packets) through dedicated
channels.
CHARATERISTICS
• Explicit the intrinsic
application parallelism.
• Modularity favours model
long-term adaptivity.
A
D
C
actions
state
B

BACKGROUND
FINE- GRAINED (FG) RECONFIGURATION
• High flexibility bit-level reconfiguration
• Slow and memory expensive configuration phase
• Suitable for applications with high control flow
COARSE-GRAINED (CG) RECONFIGURATION
• Medium flexibility word-level reconfiguration
• Fast configuration phase
• Suitable for applications with high level of instruction/data parallelism
FG CG
Bit-level Word-level
Flexibility  
Reconf.
Speed  
Config.
Storage  
ASIC
GPP
DSP
RECONFIGURABLE
DESIGNS
Performance
Flexibility

BACKGROUND
1:1
2:1
RVC-Cal Dataflow Description (DPN)
Coarse Grained Reconfigurable
HardwarePlatform
RVC-Cal Dataflow Descriptions (DPNs)
Coarse Grained HardwarePlatform
parser
crc32
inflate
input
output
parser
crc32
inflate
input
output
parser
crc32_x
inflate
input
output
parser
crc32
inflate
input
output
crc32
inflate
input output
crc32_x
SBox
SBox
SBox
parser

THE POWER ISSUE

OUTLINE
• Introduction
– Background
– The power issue
– Static Power Management: Structural Optimization
– Dynamic Power Management: Behavior Optimization

BASELINE
MULTI-DATAFLOW COMPOSER

BASELINE
P
C
I
input
output
P
C
X
I
input
output

BASELINE
P
C
I
input output
CX
S1
S2
S0
SBox D1 D2
S0 0 1
S1 0 1
S2 0 1

BASELINE
crc32
inflate
input output
crc32_x
SBox
SBox
SBox
parser

STATIC POWER MANAGEMENT:
STRUCTURAL OPTIMIZATION
A
B
D
C
E B F

A
B
D
C
E B F
A
B
D
C
E F
S0 S1

A
B
D
C
E B F
A
B
D
C
E F
S0 S1
A
12μW
B
3μW
D
8μW
C
6μW
E
15μW
B
3μW
F
5μW
A
12μW
B
3μW
D
8μW
C
6μW
E
15μW
F
5μW
S0
2μW
S1
2μW

A
B
D
C
E B F
A
B
D
C
E F
S0 S1
A
12μW
B
3μW
D
8μW
C
6μW
E
15μW
B
3μW
F
5μW
A
12μW
B
3μW
D
8μW
C
6μW
E
15μW
F
5μW
S0
2μW
S1
2μW
= 52μW
= 53μW

A
B
DC D B D B D
α β γ

A
B
DC D B D B D
A
B D
C
D
S0 S1 S2
α β γ
αγβ

A
B
DC D B D B D
A
B D
C
D
S0 S1 S2
α β γ
αγβ
longest
chain
2 SBoxes
S1 S2

A
B
DC D B D B D
A
B D
C
D
S0 S1 S2
α β γA
B
D
C
D
S0
S1
S4
S2 S3
S5
S5
αγβ
βαγ
longest
chain
2 SBoxes
S1 S2

A
B
DC D B D B D
A
B D
C
D
S0 S1 S2
α β γA
B
D
C
D
S0
S1
S4
S2 S3
S5
S5
αγβ
βαγ
longest
chain
2 SBoxes
longest
chain
4 SBoxes
S1 S2
S0
S1
S2
S5

Net1
Net2
Net3

…




2
1 !
!
!1
N
k k
N
N   


2
1
, !!1
N
k
kN kNCN
partMerDMerDnotMerDD ___ 

…
…

…
…
 sboxCPCP)(
 )max(),(max kCPCPCP 
 )( kk DPNCPCP critical path
input DPN k
CP
DPNFREQ
1
)( 
FREQ SiPS 2014 - 2014 October 22nd - Belfast (United Kingdom) - Carlo Sau13

i
ipDPNPWR )(
)( ii vAREAa 
 EVDPN ,
verticesVvi 
edgesEei 
)( ii vPWRp 

i
iaDPNAREA )(
AREA/PWR

…
… TOP.p
(full merged)

DYNAMIC POWER MANAGEMENT:
BEHAVIORAL OPTIMIZATION
A
B
D
C
E B FE B F

A
B
D
C
E B F
A
B
D
C
E F
S0 S1
E B F

A
B
D
C
E B F
A
B
D
C
E F
S0 S1
E B FA
B
D
C
A
B
D
C
E F
S0 S1

A
B
D
C
E B F
A
B
D
C
E F
S0 S1
E B FE B F
A
B
D
C
E F
S0 S1

TOP.p
(full merged)

A
B
D
C E
Net 1
Net 2
Net 3

A
B
D
C E
Net 1
Net 2
Net 3
A
B
D
C E
LR1
LR2
LR3
LR4
LR5

label actors
LR1 A
LR2 C
LR3 D
LR4 B
LR5 E
DPN regions
Net1 LR1,LR2,LR3,LR4
Net2 LR1,LR3
Net3 LR3,LR4,LR5

S0
S1
E
C
D
B
A
S3
S4
LR1
LR2
LR3
LR4
LR5
en1
en2
en3
en4
en5
ck
ck
ck
ck
ck

OUTLINE
• Introduction
– Background
– The power issue

DPN #ACTORS #OCC
Min-Max 1 1050
Abs 1 3150
Sbwlabel 17 2722
Median 9 1069
Check_GeneralBilevel 7 3072
Cubic 10 1070
Cubic_Conv 6 408
host
processor
ZOOM
coprocessor
INTERCONNECTION LAYER
APPLICATION # KERNEL # ACTORS # SBOXES
zoom 7 87 54
DESIGN UNDERTEST

[MS:MergedSpecifications]
STRUCTURAL EVALUATION
Synthesis trials have been performed through the Cadence SOC Encounter synthesizer targeting a 90 nm CMOS technology.

POWER OPTIMAL (TOP.p):
all merged

all merged
FREQ OPTIMAL (TOP.f ):
5 over 7 merged

all merged
FREQ OPTIMAL (TOP.f ):
5 over 7 merged
DESIGN
STATIC POWER
ESTIMATION [mW ]
STATIC POWER
MEASURE [mW]
ESTIMATION
ERROR
TOP.f 30.175 29.650 1.77%
TOP.p 25.833 25.716 0.45%
TOP.p vsTOP.f -13.75% -14.39% 7.78%

BEHAVIORAL EVALUATION
NOCG = without clock gating implementation
AUTO = with the synthesizer automatic register-level clock gating implementation
CG = with the proposed high-level clock gating implementation
DESIGN # of LRs
NOCG AREA
[μm2]
CG AREA
[μm2]
CG vs NOCG
TOP.f 9 135819 136076 +0.19%
TOP.p 13 124026 124579 +0.25%
TOP.p vsTOP.f +44.44% -8.68% -8.45% +31.58%

BEHAVIORAL EVALUATION
DESIGN
DYNAMIC POWER
CG vs NOCG CG vs AUTO
TOP.f -74.86% -69.06%
TOP.p -71.30% -63.75%
TOP.p vsTOP.f -13.75% -14.39%
NOCG = without clock gating implementation
AUTO = with the synthesizer automatic register-level clock gating implementation
CG = with the proposed high-level clock gating implementation
DESIGN # of LRs
NOCG AREA
[μm2]
CG AREA
[μm2]
CG vs NOCG
TOP.f 9 135819 136076 +0.19%
TOP.p 13 124026 124579 +0.25%
TOP.p vsTOP.f +44.44% -8.68% -8.45% +31.58%

OUTLINE
• Introduction
– Background
– The power issue

FINAL REMARKS AND FUTURE
DIRECTIONS
• Power consumption management is a challenging issue
in modern embedded system designs

DIRECTIONS
• The Multi-Dataflow Composer aims at:
– Implementing coarse-grained multi-functional devices
– Providing efficient power-aware architectures

DIRECTIONS
• MDC now integrates high-level power aware strategies
reducing both static and dynamic power consumption

DIRECTIONS
• MDC now integrates high-level power aware strategies
reducing both static and dynamic power consumption
• Future developments
– Power gating on different logic regions
– Improvements in the estimation models
– Heuristic for the profiler design space exploration

The research leading to these results has received funding from:
• the Region of Sardinia L.R.7/2007
under grant agreement CRP-18324
[RPCT Project].
• the Region of Sardinia, Young
Researchers Grant, POR Sardegna FSE
2007-2013, L.R.7/2007 “Promotion of
the scientific research and
technological innovation in Sardinia”
ACKNOWLEDGEMENTS

Università degli Studi di Cagliari
DIEE – Dept. of Electrical and Electronics Eng.
EOLAB - Microelectronics and Bioeng. Lab.
2014 IEEE International Workshop on gnal rocessing ystems
October 20 – 22 2014, Belfast, UK

Read full article
• IEEE Xplore Digital Library
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumb
er=6986104&tag=1
• RPCT ProjectWebsite:
http://sites.unica.it/rpct/references/

Reference
• @INPROCEEDINGS{SAU_SIPS2014,
author={F. Palumbo and C. Sau and L. Raffo},
booktitle={2014 IEEE Workshop on Signal
Processing Systems (SiPS)},
title={Power-awarness in coarse-grained
reconfigurable designs: A dataflow based
strategy},
year={2014},
pages={1-6},
doi={10.1109/SiPS.2014.6986104} }
BibTex

Power-Awarness in Coarse-Grained Reconfigurable Designs: a Dataflow Based Strategy

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