presentation on high-performance_dynamic_cmos_circuit

This presentation discusses high-performance dynamic CMOS circuits. It introduces domino logic and how it avoids the race condition of cascaded dynamic CMOS by adding an inverter between logic stages. NP domino (NORA) logic is presented as an elegant solution that alternates N logic and P logic stages with complementary clocks to prevent erroneous evaluation. Other techniques discussed include mixing static and domino logic, zipper CMOS logic to improve charge sharing, and pipelined true single phase clock CMOS with latches between alternating NMOS and PMOS stages evaluated by a single clock signal. The overall goal is high performance, reliability, speed and compact logic design.