Process Variation and Radiation-Immune Single Ended 6T SRAM Cell

ACEEE Int. J. on Signal & Image Processing, Vol. 01, No. 03, Dec 2010

Process Variation and Radiation-Immune Single
Ended 6T SRAM Cell
A. Islam1, M. Hasan2
1
Department of Electronics and Communication Engg., Birla Institute of Technology, Mesra, Ranchi, Jharkhand, India
Email: aminulislam@bitmesra.ac.in
2
Department of Electronics Engineering, Aligarh Muslim University, Aligarh, Uttar Pradesh, India
Email: mohd.hasan@amu.ac.in

Abstract— The leakage power can dominate the system power Low power operation is a feature that has become a
dissipation and determine the battery life in battery-operated necessity in today’s SoCs and µPs (microprocessors);
applications with low duty cycles, such as the wireless sensors, hence, power consumption of SRAM modules must be
cellular phones, PDAs or pacemakers. Driven by the need of reduced and has been under extensive investigation in the
ultra-low power applications, this paper presents single ended
6T SRAM (static random access memory) cell which is also
technical literature [6]. However, with the aggressive
radiation hardened due to maximum use of PMOS scaling in technology, substantial problems are encountered
transistors. Due to process imperfection, starting from the 65 when the conventional 6T (six transistors) SRAM cell
nm technology node, device scaling no longer delivers the architecture is utilized. Therefore, extensive research is
power gains. Since then the supply voltage has remained carried on designing SRAM cells for low power operation
almost constant and improvement in dynamic power has in the deep sub-micron/nanometer regimes [7−9]. The
stagnated, while the leakage currents have continued to common approach to meet the objective of low power
increase. Therefore, power reduction is the major area of design is to add more transistors to the original 6T cell. An
concern in today’s circuit with minimum-geometry devices 8T cell can be found in [7]; this cell employs two more
such as nanoscale memories. The proposed design in this
paper saves dynamic write power more than 50%. It also
transistors to access the read bitline. Two additional
offers 29.7% improvement in TWA (write access time), 38.5% transistors (thus yielding a 10T cell design) are employed
improvement in WPWR (write power), 69.6% improvement in in [8], [9] to reduce the leakage current. However, these
WEDP (write energy delay product), 26.3% improvement in approaches increase the cell area and thus not suitable for
WEDP variability, 5.6% improvement in RPWR (read power) at area constraint cache design.
the cost of 22.5% penalty in SNM (static noise margin) at The objective of this paper is to propose a new SRAM
nominal voltage of VDD = 1 V. The tighter spread in write EDP cell that is scalable to small feature sizes such as 32 nm.
implies its robustness against process and temperature The novelty of this cell is that its design requires only 6
variations. Monte Carlo simulation measurements validate transistors (6T). The architecture of the cell is different
the design at 32 nm technology node.
from that of conventional 6T SRAM cell which is
Index Terms— Random dopant fluctuation (RDF), line edge differential in nature whereas the proposed cell is single
roughness (LER), read access time, static random access ended. Moreover, the design utilizes mostly PMOS
memory (SRAM), drain induced barrier lowering (DIBL), transistors to make it radiation-hardened. The simulation
short channel effect (SCE) results of the proposed single ended PFET-based 6T
SRAM cell (hereafter called SEP-6T) are compared with
I. INTRODUCTION differential 6T SRAM cell (hereafter called Dif-6T) and it
Due to aggressive scaling, fluctuations in device is demonstrated that the proposed scheme offers significant
parameters are more pronounced in minimum-geometry advantages in terms of write dynamic power, write access
devices commonly used in area-constraint circuits such as time, write power, write EDP and read power at the
SRAM (static random access memory) cells [1]. SRAM is expense of static noise margin. Moreover, simulation
a highly used circuit of modern chips. SRAM constitutes results using HSPICE confirm that the proposed SEP-6T is
more than half of chip area and more than half of the suitable for implementation at 32 nm CMOS technology.
number of devices in modern designs [2]. As per ITRS The remainder of the paper is organized as follows.
prediction, embedded cache will occupy 90% of an SoC Various failure mechanisms are briefly reviewed in Section
(system-on-chip) by 2013 [3]. Even today, an H-264 II. Section III briefly discusses impact of scaling – DIBL
encoder for a high-definition television requires, at least, a (Drain-Induced Barrier Lowering) and SCE (Short-Channel
500 kb memory as a search-window buffer that contributes Effect), read stability, and write-ability. Section IV presents
40% to its total power dissipation [4]. The SNM (static brief discussion on read/write operation, cell sizing and
noise margin) model in [5] assumes identical device dynamic power saving of proposed SEP-6T. Section V
threshold voltages across all cell transistors, making it explains the simulation measurement results and compares
unsuitable for predicting the effects of threshold voltage proposed design with Dif-6T. Finally, Section VI
mismatch between adjacent transistors within a cell. concludes the paper.
Therefore, designer will require reinvestigation and
analysis of SNM in scaled technologies to ensure stability
of SRAM cell.

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II. FAIURE MECHANISMS IN SRAM TABLE I.
DIBL EFFECT ON THRESHOLD VOLTAGE
Failures in SRAM cell may be of three types – hard VDS Vt ηDIBL
failures, soft failures and parametric failures. 1) Hard 0 0.6292 Indeterminate
failures are caused by open or short. 2) Soft failures – there 0.1 0.6101 0.191
are major three sources of soft failures. They are alpha 0.2 0.5910 0.191
0.3 0.5719 0.191
particles released from the radioactive impurities such as 0.4 0.5528 0.191
packaging materials, high energy neutrons from terrestrial 0.5 0.5337 0.191
cosmic radiations and the interaction of cosmic ray thermal 0.6 0.5146 0.191
neutron. 3) Parametric failures – since these failures are 0.7 0.4954 0.191
caused by the variations in the device parameters, these are 0.8 0.4763 0.191
0.9 0.4572 0.191
known as the parametric failures. Parametric failures 1.0 0.4381 0.191
include access failure defined as unacceptable increase in
SRAM cell access time; read failure is defined as flipping
of cell content while reading; write failure is defined as
inability to write to a cell and hold failure is defined as
flipping of the cell state in the standby mode, especially
when VDD approaches or falls below DRV (data retention
voltage) [10−13].

III. IMPACT OF SCALING AND READ/WRITE STABILITY

Due to scaling, substantial problems arises while
designing conventional 6T SRAM cell. Therefore, impact
of scaling on read stability and write-ability is required to
be reinvestigated at scaled technology such as 32 nm
technology node.
Figure 1. Threshold voltage (Vt) versus drain to source voltage (VDS) of
A. DIBL and SCE on Scaled Devices NMOS transistor at 32 nm technology node. Vt variation due DIBL
It is well known, that the threshold voltage is given by
effect. The DIBL effect can be modeled as
(
Vt = Vt 0 + γ ( 2 | φ F | +V SB ) − 2 | φ F | ) (1)
Vt = Vt 0 − η DIBLVDS (2)
where Vt0 is the threshold voltage at VSB = 0 V and is
mostly a function of the manufacturing process, difference where Vt0 is the threshold voltage at VDS = 0V, and ηDIBL
in work-function between gate and substrate material, is the DIBL coefficient approximately equal to 0.191 for
oxide thickness, Fermi voltage, charge of impurities NFET. This is computed and verified by simulation using
trapped at the surface, dosage of implanted ions, etc; VSB is BPTM 32 nm technology. The results are tabulated and
plotted in Table I and Fig. 1 respectively, which shows
the source-bulk voltage; φF = VTln(NA/ni) is the bulk Fermi
dependency of Vt on VDS. The Fig. 1 particularly, shows
potential (where VT = kT/q = 26 mV at 300 K is the thermal
that the Vt is 0.6292 V at VDS = 0 V and the Vt drops to
voltage, NA is the doping concentration of acceptor ion of
0.4381V at VDS = 1 V.
substrate, ni is the intrinsic carrier concentration in pure
silicon); γ = √(2qNAεsi)/Cox is the body-effect coefficient B. Read Stability
(where εsi is the permittivity of silicon, Cox = εox/tox is the During correct read operation, the stored data in Q (say,
gate oxide capacitance). storing “1”) and QB (storing “0”) are transferred to the
Equation (1) is suitable for estimating the threshold bitline (BL) and bitline bar (BLB) by leaving BL at its
voltage for long channel devices (> 1 µm). It fails to model precharged value and discharging BLB through MN3 and
threshold voltage of nanoscaled devices. To model MN1 (Fig. 2). A careful sizing of MN1 and MN3 is needed
threshold voltage for nanoscaled devices many factors such to avoid accidental read upset due to building up of VQB at
as SCE (short-channel effect), RSCE (reverse short- QB. Minimum-sized transistors are necessary to design
channel effect), NWE (narrow-width effect), DIBL (Drain small-sized bitcell, which will result in longer read access
Induced Barrier Lowering) effect, etc., are to be taken into time (TRA) because of slow discharging of large bitline
account. In short-channel devices, the depletion region capacitance through small-sized transistor (offering higher
around the drain increases as VDS increases and it extends resistance). As the difference between BL and BLB builds
into the channel region. Conceptually, the drain voltage up, the sense amplifier (not shown) [14] is activated by
assists the gate voltage in the depletion process. Hence, asserting sense enable (SE) high to accelerate the reading
Vt decreases due to DIBL process. At the point of 10% discharge of BLB, sense
amplifier is enabled to sense the differential voltage
between BL and BLB. Full-swing discharge of BLB does
not take place. Hence, condition VDS,MN3 ≥ VGS,MN3 − Vt,MN3
remains valid, which implies that NM3 remains in
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saturation region and MN1 remains in linear region.
Boundary condition on MN1 and MN3 sizing to avoid read
upset is achieved by equating BLB discharging currents
through MN3 and MN1 as given below
β MN 3
2
(
V DD − VQB − Vt ,MN 3 2 )
⎧ (3)
VQB 2 ⎫
= β MN 1 ⎨(V DD − Vt , MN1 )VQB −
⎪ ⎪
⎬
⎪ 2 ⎪
⎩ ⎭
where
β = µ n C ox (W/L). (4)
Figure 3. Voltage ripple (VQB) versus cell ratio while reading Dif-6T
Equation (3) can be solved for VQB by substituting Vt,MN3
and Vt,MN1 using (2) and Table I. The Cell Ratio (CR) (also
called β ratio) is defined as

(W / L) MN 1
CR = . (5)
(W / L) MN 3

CR is required to be set appropriately to avoid
accidental read upset. The Fig. 3 shows the plot of VQB
versus CR of Dif-6T simulated using MN1/MN3 size ratio
from 0.1 to 3.5 with minimum-sized transistors (i.e. MP1 =
MP2 = MN2 = MN4 = 32 nm/32 nm). It is observed from
Fig. 3, that the voltage rise at QB with CR = 0.1 is 0.3285
V, whereas Vtn ranges from 0.4381 V to 0.6292 V for VDS Figure 4. Voltage ripple versus pull-up ratio while writing to Dif-6T
ranging from 1 V to 0 V (Fig. 1) in 32 nm technology node. C. Write-Ability
It implies that read upset may not occur due to voltage rise
A reliable write operation is possible if node storing “1”
while reading, if CR is lowered even up to 0.1. Read
(say, Q in Fig. 2) is pulled low enough – below the
stability also largely depends on DIBL, which is inherent to
threshold voltage of MN1, so that writing a “1” is possible
technology scaling (i.e. SCE). To understand the
to the other storage node (say, QB) by flipping the cell
dependence of read upset on DIBL, consider the case when
state. Sizing of the transistors MP2 and MN4 should be
VQB is increasing from 0. The increase in VQB will increase
such that this occurs causing flipping of state, failing which
the VDS, MN1, (Drain to source voltage of MN1). It is obvious
will cause write failure. The size ratio between MP2 and
(Fig. 1), that this will reduce the Vt of MN1 thereby making
MN4 called pull-up ratio (PR) (also called γ ratio) is
it stronger. This unexpected mismatch in threshold voltage
will affect the SNM of the SRAM cell (decrease in Vt will defined as
decrease SNM) [5]. An SRAM cell should be designed (W / L) MP 2
such that under all conditions some SNM is reserved to PR = . (6)
cope with dynamic disturbances. Therefore, considering (W / L) MN 4
the trade- off between SNM and cell size, CR is set to 1 for Fig. 4 plots the simulated results of VQ versus PR
the analysis in this paper (i.e. Dif-6T and SEP-6T cells are with minimum-sized transistors (i.e. MP1 = MN1 = MN2 =
made with minimum-sized devices). It is therefore obvious MN3 = 32 nm/32 nm). As observed from Fig. 4, to avoid
that, neither the proposed design nor its counter part will write failure, PR must be chosen such that VQ falls below
suffer from read upset problem. threshold voltage of MN1. As mentioned above, threshold
voltage Vtn = 0.4381 V at VDS ═ 1 V (Fig. 1) at 32 nm
technology node. As observed from Fig. 4, VQ ═ 0.4808 V
at PR ═ 3, which implies that PR should be set below 3 to
avoid write failure. The PR for the proposed design as well
as Dif-6T in this paper is set to unity which ensures their
write-ability.

IV. SINGLE ENDED PFET-BASED 6T SRAM CELL
Fig. 5 shows the proposed design. It consists of two
Figure 2. Standard 6T SRAM cell cross-coupled inverters connected in a positive feed-back
loop through transistor MP5. Unlike, conventional
differential 6T SRAM cell, only one PMOS transistor MP3
is used as access transistor for accessing the cell.
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A. Read/Write operation and Cell sizing speed [14]. In this analysis, read operation is simulated
Writing as well as reading takes place only through with QB holding “1”. This is illustrated in Fig. 8, which
BLB. Thus, single ended writing and sensing (reading) shows various node voltages while reading with QB
scheme is required for the proposed design. All the holding “1”.
transistors (four PMOS and two NMOS) are of minimum-
sized (each 32 nm × 32 nm) to achieve smallest cell area.
PMOS transistors are used as major devices to get the
benefit of its higher radiation tolerance. Leakage currents
in NMOS transistors increase after radiation bombardment,
but leakage currents in PMOS devices remain almost
unaffected [15]. Excessive leakage in access transistor may
corrupt the stored data in storage node of the cell.
Therefore, usage of PMOS transistors will improve the
hold failure probability of the SRAM cell. Moreover,
PMOS devices have an order of magnitude smaller gate
leakage than NMOS transistors [16].
Before and after each write operation BLB is
precharged low, by asserting PCL (pre-charge low) high at Figure 5. Proposed single ended 6T SRAM cell (SEP-6T)
the gate of an NMOS whose drain and source are
connected to BLB and GND (not shown). Write operation
of SEP-6T is initiated by switching MP5 off applying W =
“1” (in other time, i.e., read and hold time MP5 remains
on). This breaks the feedback path and makes writing
easier. In the literature single ended 5T SRAM cell is found
[17], which exhibits problem while writing “1” and needs
write assist method. BLB carries the complement of the bit
to be stored in storage node Q (or equivalently BLB carries
the bit to be stored at storage node QB). On application of
WL = “0”, bit applied on BLB gets complemented and
stored at Q. This bit in turn drives INV1 (inverter 1) and
finally a bit applied at BLB gets stored at QB. Thus, write
operation involves two inverters’ delay. As MP3 passes a
Figure 6. Voltage transfer curve (VTC) of various nodes while writing
bad “0”, at the end of write “0” operation at QB, VQ2 is at “0” @ QB
higher potential than GND (QB). This is evident from Fig.
6, which shows various node voltages while writing “0” @ TABLE II.
QB. Just after write operation, when W is pulled down in THRESHOLD VOLTAGE FOR OPTIMUM RESULTS
hold mode, MN2 may partially conduct causing short- Device Dif- 6T SEP-6T
circuit current to pass from VDD to GND through MP2. MP1, MP2 Vtp0 −0.5808 V −0.63 V
This problem can be mitigated in two ways; 1) by using MP3, MP5 Vtp0 − −0.30 V
low-Vt (absolute value) MP5 to reduce voltage difference MN1, MN2 Vtn0 0.63 V 0.63 V
MN3, MN4 Vtn0 0.63 V −
between Q2 and QB and 2) using high-Vt MN2 to reduce
the possibility of it being on due to residual VQ2. Zero bias
threshold voltage (Vtn0) of NMOS is 0.63 V at BPTM 32
nm technology. It is already quite high compared to zero
bias threshold voltage (Vtp0) of PMOS. Therefore, in this
paper low-Vt (absolute value) MP5 is used (−0.3 V in spite
of −0.5808 V). Extensive simulations are performed to
obtain optimum results by selecting different Vts. Optimum
results in terms of various design metrics are obtained with
the Vts as shown in Table II. During write “0” to QB
operation, BLB is precharged initially to GND but not
charged. During write “1” operation at QB, BLB is initially
precharged to GND and then charged by the write circuit
(not shown). This reduces the switching activity factor,
which helps in saving dynamic power dissipation. The Figure 7. VTC of various nodes while writing “1” @ QB
write “1” to QB operation is illustrated in Fig. 7, which
shows various node voltages during write operation. For
the single ended read operation an inverter can be used to
sense the BLB, but other single ended sensing mechanism
such as charge re-distribution amplifier could improve read
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variations affect the performance and reliability of a
design.
A. Write Access Time
Write access time (TWA) is estimated at different
voltages while writing “1” @ QB. Table III presents the
measured TWA of both the designs. Fig. 9 plots the
simulated results for making the comparison easier. The
TWA is estimated as the time required for writing “1” at QB
from the point when WL reaches 50% of its full swing
from its initial high level to the point when QB rises to
90% of its full swing from its initial low level. As
mentioned in Section IV-A, for writing a bit @ QB, the
Figure 8. VTC of various nodes while reading with QB storing “1” write operation is completed after a two inverter delays
B. Dynamic Power Saving when QB settles to its new state. Therefore, the TWA is
longer than TRA (read access time) as shown in Section V-
The dynamic power is one of the major contributors to D. To understand why the TWA of SEP-6T is lower than
the total power consumption in the SRAM cell. The that of Dif-6T, remember that, Vt of MP2 (Vtp0 = − 0.5808
dynamic power consists mainly of two components – write V) of Dif-6T is lower (absolute value) than that of MP2
power and read power. These power dissipations occur due (Vtp0 = − 0.63 V) of SEP-6T, Thus, MP2 of Dif-6T is
to charging/discharging of large bitline capacitances. The stronger than that of SEP-6T. This prevents MN4 of Dif-6T
bitline capacitance consists of source/drain diffusion to drop VQ quickly. Another reason of lower write delay in
capacitance of access transistor, interconnect capacitance SEP-6T is that the MP3 (Vtp0 = − 0. 3 V) of SEP-6T passes
and contact capacitance. The expression for bitline a strong “1” from BLB to drive INV2 (inverter 2) harder
capacitance is given by and MP2 of SEP-6T is also made weaker by increasing its
C BL = C BLB = C S / D ,cap + C int + C contact . (7) Vt (absolute value). This helps MN2 to quickly pull down
storage node Q, which in turn drives INV1 and quickly
The dynamic power dissipation during write operation flips QB. As observed from the Table III, proposed design
contributes 70% to the total dynamic power dissipation in offers 29.7% improvement in TWA at nominal voltage of
SRAM cell [18]. Write dynamic power dissipation while VDD = 1 V.
TABLE III.
writing to a cell is given by WRITE ACCESS TIME
2
PWRITE = α BL × C BL × V DD × FWRITE (8) SRAM TWA while writing “1” @ QB (s) VDD
(V)
where αBL is the switching activity factor, FWRITE is writing 3.853e-11 1
frequency to SRAM cell. Writing to a conventional Dif-6T Dif-6T 4.751e-11 0.95
cell (Fig. 2) requires discharging (from initial high value) 5.467e-11 0.90
of one of the bitlines per write operation whereas the 6.542e-11 0.85
proposed design requires charging (from initial precharged 8.047e-11 0.80
GND value) of its only bitline (BLB) while storing “1” at 2.709e-11 1.00
SEP-6T 3.163e-11 0.95
storage node QB (or “0” @ storage node Q). This reduces
αBL to ≤ 0.5. It is therefore, obvious from (8), that PWRITE is 3.962e-11 0.90
improved by more than 50% if proposed design is used 5.741e-11 0.85
replacing Dif-6T. 7.794e-11 0.80

V. SIMULATION MEASUREMENT RESULTS AND DISCUSSION
This Section presents measurements of various design
metrics which are measured during simulation on HSPICE
using BPTM 32 nm technology [19]. Monte Carlo
simulations are performed for the measurements. During
Monte Carlo simulation, process parameters such as L
(channel length), W (width), tox, (oxide thickness), u0 (zero
bias carrier mobility) and R□ (sheet resistance) are varied
by ±10% with Gaussian distribution function. The
temperature is varied from 24°C to 134°C as well using
absolute Gaussian function. Simulation measurements are Figure 9. Write access time while writing “1” QB
taken for both the designs applying ±3σ variation. Monte
Carlo simulation is a method for iteratively evaluating a B. Write Power Measurement
design. The goal is to determine how random PVT Write dynamic power defined in (8) is caused due to
charging/discharging of bitline. Dynamic power dissipation
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during accessing a cell through its devices is generally
ignored, though it contributes a large portion to the total
dynamic power consumption. During write access in SEP-
6T, while writing “1” at QB, VDD finds path to GND
through two pull-down transistors MN1 and MN2 (Fig. 5).
BLB is asserted high for writing “1” @ QB. BLB is
connected to Q2 through MP3 while writing. The supply at
BLB does not find path to GND. Therefore, major dynamic
power dissipation during transition (accessing) is through
MN1 and MN2. Thus, total average write transition power
of SEP-6T is given by
PW , SEP−6T = PAVG, MN1 + PAVG, MN 2 (9)
Figure 10. Total average write transition power versus VDD
where PAVG,MN1 and PAVG,MN2 are average write transition
power through MN1 and MN2 while writing “1” @ QB. In
case of Dif-6T, BLB is biased at VDD and BL is grounded
by write circuit (not shown). BL pulls-down storage node
Q below switching threshold of INV1 and finally flips the
cell to write a “1” @ QB. During this transition, VDD finds
path to GND through three transistors MN1, MN2 and
MN4. Therefore, total average write transition power of
Dif-6T is given by:
PW , Dif − 6T = PAVG , MN 1 + PAVG , MN 2 + PAVG , MN 4 (10)

where PAVG,MN1, PAVG,MN2 and PAVG,MN4 are average write
transition power through MN1, MN2 and MN4 while Figure 11. Write EDP (WEDP) estimated at different voltages while writing
“1” @ QB versus VDD
writing “1” @ QB. Total average write transition power,
i.e., PW,SEP-6T and PW,Dif-6T, commonly abbreviated as WPWR
is estimated at different voltages while writing “1” @ QB
and the results are plotted in Fig. 10, which shows that the
SEP-6T outperforms Dif-6T at all supply voltages.
Equations (9), (10) and the above discussion clarify the
reason of its superiority. As observed from the Fig. 10,
proposed design offers 38.5% improvement in WPWR at
nominal voltage of VDD = 1 V.
C. Write EDP Measurements
Reduction of EDP is a good direction for optimizing
any digital circuit including SRAM cell. Since EDP reflects Figure 12. Write EDP (WEDP) variability estimated at different voltages
while writing “1” @ QB versus VDD
the battery consumption (E) for completing a job in a
certain time (D), it is an important design metrics. The measurements of WEDP are taken at various
Therefore, EDP of SEP-6T and Dif-6T are estimated and operating voltages starting from nominal voltage of VDD = 1
results are compared. The write energy delay product V down to the minimal operating voltage of 0.8 V beyond
(WEDP) is estimated using write delay and write power which write failure begins to occur under the used writing
while writing “1” @ QB. The WEDP of SEP-6T is defined as condition (if write condition is changed write failure may
2
not occur). The results are plotted in Fig. 11, which shows
W EDP, SEP −6T = PW , SEP −6T × TWA, SEP −6T . (11) that the SEP-6T outperforms Dif-6T at all supply voltages.
As observed from the Fig. 11, proposed design particularly
The WEDP of Dif-6T is defined as offers 69.6% improvement in WEDP at nominal voltage of
2
W EDP , Dif − 6T = PW , Dif − 6T × TWA, Dif − 6T . (12) VDD = 1 V.
Write EDP (WEDP) variability (σ/µ) is estimated at
various supply voltages and the results are plotted in Fig.
12. As observed from Fig. 12, fluctuations in WEDP of Dif-
6T at lower voltages are quite satisfactory, but it shoots up
at 0.95 V, whereas variations in SEP-6T are moderate at all
supply voltages. To make both the circuits variation
immune in terms of WEDP, they are to be operated at 0.9 V.
As observed from the Fig. 12, proposed design offers

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26.3% improvement in WEDP variability at nominal voltage of Dif-6T whereas in case of SEP-6T, CBLB is charged
of VDD = 1 V. through low-Vt MP3 (Vtp0 = − 0. 3 V). It implies that MN4
does not get on till 0.63 V is applied at its gate through
D. Read Access Time
WL, whereas only |0.3 V| applied through WL is sufficient
As mentioned in Section IV-A, for single ended read to put MP3 on. Since slew rate of WL is same for both the
operation an inverter can be used to sense the BLB, but cases CBLB begins to charge up earlier than CBL begins to
other single ended sensing mechanism could decrease the discharge down.
read delay. Read access time (TRA) is estimated at different
voltages with QB storing “1” for both the design at iso- E. Read Power Measurement
measuring condition (i.e., with equal WL slew rate, on time Read power is measured with QB holding “1”. During
and same operating voltage). The measured results are read access in SEP-6T, VDD finds path to GND through two
reported in Table IV. The results are also plotted in Fig. 13 pull-down transistors MN1 and MN2 and storage node
for making comparison easier. holding “1” charges CBLB through MP5 and MP3 (Fig. 5).
The TRA (for Dif-6T) is estimated as the time required Therefore, total average read transition power of SEP-6T is
for reading with QB storing “1” from the point when WL given by
reaches 50% of its full swing from its initial low level to
the point when BL falls by 10% of its full swing from its PR , SEP −6T = PR _ AVG , MN 1 + PR _ AVG , MN 2 + PBLB (13)
initial high level. The TRA (for SEP-6T) is estimated as the
time required for reading with QB storing “1” from the where PR_AVG,MN1 and PR_AVG,MN2 are average read
point when WL reaches 50% of its full swing from its transition power through MN1 and MN2 and PBLB is power
initial high level to the point when BLB rises to 90% (so dissipated for charging CBLB while reading with QB storing
that inverter connected to BLB to sense its voltage is able “1”. The PBLB per read operation is given by
to do so without fail) of its full swing from its initial low
2
level. As observed from Fig. 13, SEP-6T outperforms Dif- PBLB = C BLB × V DD × f t (14)
6T at all supply voltages except at nominal voltage of VDD
= 1 V (where TRA of SEP-6T equals TRA of Dif-6T). where ft is transition or read frequency. In case of Dif-6T,
BL and BLB are biased at VDD before each read operation.
During read transition VDD finds path to GND through
TABLE IV.
READ ACCESS TIME MN1 and MN2. CBL discharges through MN2 via storage
node Q. Therefore, total average read transition power of
SRAM TRA with QB storing “1” VDD Dif-6T is given by
(s) (V)
1.667e-11 1 PR , Dif −6T = PR _ AVG , MN 1 + PR _ AVG , MN 2 (15)
Dif-6T 1.913e-11 0.95
2.255e-11 0.90 where PR_AVG,MN1 and PR_AVG,MN2 are average read
2.764e-11 0.85 transition power through MN1 and MN2 while reading
3.574e-11 0.80 with QB storing “1”.
5.040e-11 0.75
1.644e-11 1 Total average read transition power, i.e., PR_SEP-6T and
SEP-6T 1.790e-11 0.95 PR_Dif-6T, commonly abbreviated as RPWR is estimated at
1.984e-11 0.90 different voltages while reading with QB storing “1” and
2.242e-11 0.85 the results are plotted in Fig. 14. As observed from Fig. 14,
2.588e-11 0.80 the proposed design outperforms the conventional Dif-6T
3.028e-11 0.75 at all higher supply voltages staring from 0.85 V

Figure 14. Total average read transition power ( RPWR) estimated at
different voltages while reading with QB storing “1” versus VDD

Figure 13. Read access time while writing “1” QB
to nominal voltage of 1 V. At lower voltages such as 0.75
V and 0.8 V, Dif-6T outperforms SEP-6T. As observed
To understand why the TRA of SEP-6T is lower than that of from the Fig. 14, proposed design offers 5.6%
Dif-6T, remember that, large CBL discharges (while reading improvement in RPWR at nominal voltage of VDD = 1 V.
with QB holding “1”) through high-Vt MN4 (Vtn0 = 0.63 V)

©2010 ACEEE 43
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F. Read EDP Measurements
The Read Energy Delay Product (REDP) of SEP-6T and
Dif-6T are estimated and results are compared. REDP is
estimated using read delay and read power while reading
with QB holding “1”. The REDP of SEP-6T is defined as
2
REDP, SEP − 6T = PR, SEP − 6T × TRA, SEP − 6T (16)

The REDP of Dif-6T is defined as
2
REDP , Dif − 6T = PR , Dif − 6T × TRA, Dif − 6T (17)
Figure 15. Read EDP versus VDD
The measurements of REDP are taken at various supply
voltages starting from nominal voltage of VDD = 1 V down
to the minimal supply voltage of VDD = 0.75 V beyond
which read failure begins to occur under the used reading
condition (if read condition is changed read failure may not
occur). The results are plotted in Fig. 15. As observed from
Fig. 15, SEP-6T outperforms Dif-6T at all supply voltages.
G. Static Noise Margin Measurements
The SNM of SRAM cell is defined as the minimum DC
noise voltage necessary to flip the state of the cell. SNM of
an SRAM is a widely-used design metric that measures the
cell stability. Fig. 16 and 17 show conceptual test setup for
measuring SNM for SEP-6T and Dif-6T respectively. The
measured results when plotted is called "butterfly curve". Figure 16. Test circuit for measurement of SNM of SEP-6T
Fig. 18 plots the combined “butterfly curve” of Dif-6T and
proposed SEP-6T at iso-measuring condition. The butterfly
curve for SEP-T is obtained in the following way using the
test circuit: 1) W and BLB are biased at GND voltage and
WL is biased at supply voltage. 2) Voltage of N1 is swept
from 0 V to supply voltage while measuring voltage of QB.
3) Voltage of N2 is swept from 0 V to supply voltage while
measuring voltage of Q in the same way. 4) Measured
voltages are plotted to get butterfly curves. The side length
of Maximum Square that can be embedded within the
smaller lobe of the butterfly curve represents the SNM of
the cell. This definition holds good because, when the Figure 17. Test circuit for measurement of SNM of Dif-6T
value of noise voltage (VN1 or VN2) increases from 0, the
VTC (voltage transfer characteristic) for INV1 formed with
MP1 and MN1 moves to the right and the VTC−1 (inverse
VTC) for INV2 formed with MP2 and MN2 moves
downward. Once they both move by the SNM value, the
curves meet at only two points and any further noise flips
the cell [20]. As observed from Fig. 18, SEP-T shows
22.5% penalty in SNM.
H. Comparitive Study of Cell Area
In multi-port design, area would be the major concern. Figure 18. Static noise margin of Dif-6T and proposed SEP-6T cell
As multi-core µPs, SoCs, and NoCs (network-on-Chip)
will dominate future technological innovation, on-chip
cache deigned with high density and low bitline switching
power is an attractive choice. In 65 nm technology node,
RD-8T (read decoupled 8T) SRAM cell proposed in [21],
isolates read port from storage node thereby increasing read
stability (without improving write margin significantly) at
cost of 30% area penalty compared to dense 6T cell (which
might me used for higher level caches). Differential data-
aware power-supplied D2AP 8T cell with a boosted bitline
scheme proposed in [22], incurs an area overhead similar to
©2010 ACEEE 44
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