Programmable_System-on-Chip_for_Silicon_Prototyping.pdf

830 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 3, MARCH 2011
Programmable System-on-Chip
for Silicon Prototyping
Chun-Ming Huang, Member, IEEE, Chien-Ming Wu, Member, IEEE, Chih-Chyau Yang, Shih-Lun Chen,
Chi-Shi Chen, Jiann-Jenn Wang, Kuen-Jong Lee, Member, IEEE, and Chin-Long Wey, Senior Member, IEEE
Abstract—This paper presents a programmable system-on-chip
(SoC) design methodology which integrates multiple heteroge-
neous SoC design projects into a single chip such that the total
silicon prototyping cost for these projects can be greatly reduced
by sharing a common SoC platform. In this implementation, an
integrated SoC platform is comprised of eight SoC projects. When
these eight SoC projects are designed separately, the total area
is approximately 143.03 mm2
, while the area of the integrated
platform is about 24.43 mm2
. The area reduction is significant,
so is the fabrication cost. Once the integrated platform chip is
fabricated, three programming schemes are carried out to allow
the integrated chip to act as the individual SoC design projects. A
test chip is designed and implemented using the TSMC 0.13-µm
CMOS generic logic process technology.
Index Terms—Multiple-project system-on-chip (MP-SoC),
platform-based SoC, programmable SoC, silicon prototyping.
I. INTRODUCTION
WITH THE fast advance of IC fabrication and electronic
design automation (EDA) technologies, the system-on-
chip (SoC) design technology has become more and more
practical. A complex system can be integrated into a single
chip via SoC design methodology achieving lower power, lower
cost, and higher speed than the traditional board level design.
Among the existing SoC design methodologies, the platform-
based methodology [1], [2] is the most off-the-shelf one, where
a platform is defined as an architectural framework consisting
of a set of prequalified software and hardware IPs that are
integrated into some specified on-chip connection architecture.
Based on a well-defined and verified SoC platform, even a
small design team can design and implement a complex SoC
because they only need to focus on the creation of function-
specific IP blocks and the related embedded software. Although
Manuscript received May 29, 2008; revised January 13, 2009; accepted
April 6, 2009. Date of publication May 15, 2009; date of current version
February 11, 2011.
C.-M. Huang, C.-M. Wu, C.-C. Yang, C.-S. Chen, and J.-J. Wang are
with the National Chip Implementation Center, Hsinchu 300, Taiwan (e-mail:
cmhuang@cic.org.tw; wucm@cic.org.tw; ccyang@cic.org.tw; cschen@cic.
org.tw; wjj@cic.org.tw).
S.-L. Chen is with the National Chip Implementation Center, Hsinchu 300,
Taiwan, and also with the Department of Electrical Engineering, National
Cheng Kung University, Tainan 701, Taiwan (e-mail: slchen@cic.org.tw).
K.-J. Lee is with the Department of Electrical Engineering, National Cheng
Kung University, Tainan 701, Taiwan (e-mail: kjlee@mail.ncku.edu.tw).
C.-L. Wey is with the National Chip Implementation Center, Hsinchu
300, Taiwan, and also with the Department of Electrical Engineering, Na-
tional Central University, Jhongli 32001, Taiwan (e-mail: clwey@cic.org.tw;
clwey@ee.ncu.edu.tw).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2009.2022075
the platform-based design methodology is very helpful for
SoC design, due to the fabrication cost, it is not easy to pro-
vide silicon prototyping opportunity for academic SoC design
projects. More specifically, Fig. 1(a) shows an ARM-based 2-D
discrete cosine transform (DCT)/inverse DCT (IDCT) SoC
implemented with UMC 0.18-µm 1P6M process. The 150-pin
platform-based SoC takes an area of 4488 × 3493 µm2
, or
15.68 mm2
. Moreover, the ARM922T embedded processor
core takes approximately 2378 × 3400 µm2
, or 8.09 mm2
,
in area. The commonly used components in the platform,
as shown in Fig. 1(b), include embedded processors, on-
chip memories, on-chip connection architectures, peripheral
devices, and input/output (I/O) pads. Experimental results show
that approximately 98% of the entire silicon area is occupied
by the third party silicon IPs. Only a small portion of the SoC
design is contributed by the design team.
In the last decades, multiple-project chip (MPC) service
model [3]–[5], as shown in Fig. 2, has been provided by many
fabrication service institutions such as National Chip Imple-
mentation Center (CIC), Hsinchu, Taiwan; CMP, France; and
International Democratic Education Conference, South Korea.
The service model has effectively reduced the mask tooling and
chip fabrication cost. However, the MPC concept cannot reduce
the high fabrication cost for the large silicon area demanded by
each individual SoC project.
Instead of verifying an SoC design project through silicon
prototyping, virtual prototyping via hardware/software cosim-
ulation environments such as Seamless CVE [6] and Platform
Architect (ConvergenSC) [7], or rapid prototyping via embed-
ded processor-included field programmable devices such as
Virtex II [8], Nios II Development Kit [9], and System Explorer
MP4CF [10], is also commonly used. Due to the obvious ad-
vantages of field-programmable logic array (FPGA), including
flexibility of design/implementation approach and hardware
platform reuse, FPGA can now be considered as an appropriate
solution to boost the performances of controllers, by enabling
the implementation of new control methods and/or by designing
concurrent architectures. Thus, FPGA has recently received
special attention by industrial electronics society [11]–[18].
However, FPGA solutions can be used for functional verifica-
tion, but not for siliconproof results of real chips.
Recently, a novel service model, multiple-project SoC
(MP-SoC), has been initiated and implemented by the CIC. As
shown in Fig. 3, the MP-SoC design methodology integrates
multiple SoC design projects sharing a common SoC platform
into a single chip [19]. The common SoC platform typically
includes embedded processors, on-chip memories, on-chip
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HUANG et al.: PROGRAMMABLE SYSTEM-ON-CHIP FOR SILICON PROTOTYPING 831
Fig. 1. Platform-based SoC design. (a) ARM-based 2-D DCT/IDCT SoC. (b) Block diagram.
Fig. 2. CIC MPC service.
connection architecture, peripheral devices, and I/O pads. Since
a common SoC platform is shared by all SoC design projects,
only one common SoC platform is fabricated and thus the total
fabrication cost can be dramatically reduced. Fig. 3. Basic concept of MP-SoC.

TABLE I
AREA, PERFORMANCE, AND POWER CONSUMPTIONS SUMMARY (SHARED AREA: 15 582 008 µm2)
Once the integrated platform is fabricated, the performance
of each individual SoC design project is measured by pro-
gramming the integrated platform. By programming, which
means that, for each individual SoC project, the signal lines
of all IPs which are not associated with this project are dis-
abled or disconnected. As such, the platform is, in fact, the
same as the individual SoC design. There are three schemes:
1) electrical configuration; 2) physical disconnection; and
3) power gating proposed in this paper for programming the
signal lines. This paper will address the design tradeoffs among
these schemes.
In the next section, the motivation and design concepts of
MP-SoC is explored. Section III presents the MP-SoC design
methodology. The design and implementation of the test chip
called the MP-SoC-I chip is illustrated in Section IV. Section V
describes the programmability. Finally, the concluding remark
is given in Section VI.
II. MOTIVATION AND DESIGN CONCEPTS
The key idea of the MP-SoC methodology is to reduce the
total chip area of the projects integrated into a single chip
by sharing the common resources. The area saving can be
formulated as follows.
Assume that N SoC projects are integrated into a single chip.
Let Atotal denote as the total area of the N SoC projects when
they are implemented individually, and AMP-SoC as the area
required if the N SoC projects are implemented by the proposed
MP-SoC methodology. Both terms Atotal and AMP-SoC can be
formulated as (1) and (2), respectively
Atotal = N × Ashared +
N

i=1
AIP,i +
N

i=1
Aoverhead1,i (1)
AMP-SoC = Ashared +
N

i=1
AIP,i +
N

i=1
Aoverhead2,i (2)
where Ashared, AIP,i, Aoverhead1,i, and Aoverhead2,i indicate the
area of the common components shared by all SoC projects,
the area of the dedicated IPs used only for the ith SoC project,
the overhead area due to the integration of dedicated IPs of the
ith project to a dedicated SoC, and the overhead area due to the
integration of dedicated IPs for the ith project to the MP-SoC
chip, respectively.
Applying this MP-SoC mechanism, the area cost saving can
be advantaged from the reduction of (N − 1) × Ashared. Here,
we define a cost evaluation index Rsaving for the proposed
MP-SoC mechanism as follows:
Rsaving =
Atotal −AMP-SoC
Atotal
=
(N − 1)×Ashared −
N

i=1
(Aoverhead2,i −Aoverhead1,i)
Atotal
.
(3)
Clearly, the larger value in (3) is, the more fabrication cost
saving can be anticipated.
For simplicity of discussion, consider two platform-based
SoC designs: 1) performance-driven configurable motion esti-
mation (ME) engine [20], referred to as ME-SoC; and 2) ad-
vanced encryption standard (AES) cryptographic engine [21],
referred to as AES-SoC. The portion developed by the design
team for the accelerator module for ME takes 106 437 µm2
,
in area. The total area of the ARM-based ME-SoC design
is approximately 4165 × 4164 µm2
, or 17 343 060 µm2
. In
other words, the area of the third party’s IPs is approximately
17 236 623 µm2
. On the other hand, the total area of the
ARM-based AES-SoC design is about 3998 × 3998 µm2
, or
15 984 004 µm2
. In this experiment, we integrate both de-
signs into the same platform. Its area is 4213 × 4212 µm2
, or
17 745 156 µm2
.
Table I summarizes the estimated area, performance, and
power consumptions in each experiment. The shared area is
approximately 15 582 008 µm2
. The total area of IP for ME
and the IPs dedicated for ME-SoC is 1 761 052 µm2
. This
implies that the percentage of the area dedicated to ME over the
ME-SoC is 10.15%. On the other hand, the area dedicated to
AES is 402 096 µm2
, or the area percentage is 2.52%. In the
integrated case, the area percentage is 12.1%.
The max frequencies of AES/ME-SoC, AES/ME-SoC taking
off ME and AES/ME-SoC taking off AES are 110.9 MHz,
110.3 MHz, and 130.5 MHz, respectively, and the power con-
sumptions are 248.302 mW, 226.22 mW, and 240.589 mW,
respectively. The max frequencies of AES-SoC and ME-SoC
are 111.5 MHz and 153.4 MHz, respectively, and the power
consumptions of AES-SoC and ME-SoC are 181.134 mW and
189.667 mW, respectively.
Based on Table I, when both AES-SoC and ME-SoC are fab-
ricated separately, the total area (Atotal) is 33.33 mm2
. How-
ever,whenbothareintegrated,thearea(AMP-SoC)is17.75mm2
.
Thus, we can obtain around 47% area saving (Rsaving). The
area reduction is significant, and so is the fabrication cost.

Fig. 4. Comparison of Atotal and AMP-SoC for various number of SoC
projects.
TABLE II
PERCENTAGE OF AREA SAVING
Note that in this implementation, the components (or IPs) can
be classified into three categories: (a) common to both ME and
AES; (b) used only by AES; and (c) used only by ME. Once the
integrated platform is fabricated, it can be used as a ME-SoC by
disabling/disconnecting all components only used by the AES,
or as an AES-SoC by disabling/disconnecting all components
only used by the ME.
By Table I, the ratio Ashared/AAES(dedicated) = 15 582 008/
402 096, or 39 and Ashared/AME = 9. The average ratio of
Ashared/AIP is (39 + 9)/2, or 24. Since the overhead areas
due to the integration of dedicated IPs of the ith project to a
dedicated SoC, and the overhead areas due to the integration
of dedicated IPs for the ith project to the MP-SoC chip are
very small, for example, the arbiter circuit was modified for
the master IPs and the decoder circuit was modified for the
slave IPs. It is approximately assumed that the overhead area
Aoverhead1,i = Aoverhead2,i = 0. By substituting Aoverhead,i =
0, Ashared = 24, and AIP,i = 1 into (1)–(3), both Atotal and
AMP-SoC can be calculated for the integrated platform with
various number of SoC projects, as shown in Fig. 4, while the
area saving ratio can be simplified as
Rsaving =
(N − 1) × 24
N × 25
. (4)
By (4), Table II lists the ratio of area saving in the inte-
grated case for different number of SoC projects. When N =
8, we can obtain around 84% area saving. In this paper, the
MP-SoC-I includes eight SoC design projects, i.e., N = 8, the
experimental results discussed shortly show that the area saving
is approximately 82.9%.
III. MP-SOC DESIGN PLATFORM AND DESIGN FLOWS
A. Design Platform
The MP-SoC design methodology can be regarded as a new
innovative design/implementation service model. It allows the
integration of multiple SoC projects into a single chip to reduce
the total fabrication and verification cost, and hence enables the
Fig. 5. Coordination structure. (a) Conventional. (b) MP-SoC.
academic researchers to tape out real SoC chips. To implement
heterogeneous SoC projects with an MP-SoC chip, the provided
common platform must accommodate all the requirements of
each SoC project such as clock-rate specification, memory
allocation, system bus utilization, etc. In addition, how to
efficiently manage the existing environment and seamlessly
integrate the available CAD toolboxes at each design stage into
an environment suitable for the development of an MP-SoC
design is also very critical. In this paper, we not only develop
a highly sharable SoC design platform (called the MP-SoC
Common Platform), but also derive a complete, user-friendly
suite of design flows that can facilitate quick hardware/software
development and verification without sacrificing development
time and resulting performance.
The proposed MP-SoC common platform is different from
the conventional design platform in several aspects. First,
MP-SoC means that multiple SoC designs are integrated into
a single platform to share common resources. For the conven-
tional SoC designs, only those IPs associated with the SoC are
integrated into one platform. Second, MP-SoC allows multiple
heterogeneous applications to be implemented in a single plat-
form. On the other hand, the conventional SoC design usually
targets only for one application. Third, the conventional acad-
emic SoC design is usually carried out within one university in
terms of the platform management, as shown in Fig. 5(a). How-
ever, MP-SoC needs to leverage SoC designs from different
universities; thus, a new coordination/management structure,
as shown in Fig. 5(b), is needed. Due to the requirement to
integrate many SoCs into one chip, sophisticated and reliable
isolation, arbitration, and testing mechanisms for the platform
have to be employed.
As shown in Fig. 6, the MP-SoC common platform differs
from the conventional single-project platform in many aspects
including functional capability, communication facility, design
flexibility, etc. In this figure, the solid blocks present the shared
system blocks in MP-SoC system, while the dashed blocks
indicate the empty blocks reserved for individual IPs.
Each design team needs only to connect their IP/IPs to the
reserved dashed block, and follow the system map planning to
complete their application program. Thus, this is a plug and
play platform. The platform in conjunction with the developed
design flows results in a very time-efficient design and imple-
mentation environment for individual IPs to be integrated in the
MP-SoC chip.
B. Design Flow
In order to achieve the objectives of the first-ever MP-SoC
design concept, a set of innovative design flows is presented in

Fig. 6. MP-SoC common platform.
this section. The design flows have been developed as follows,
including a system architecture design flow, an IP block design
flow, a logic implementation design flow, and a physical imple-
mentation design flow [19].
System Architecture Design Flow: In order to offer the
verifying system-level performance and features, we created
a system architecture design flow. First, we investigated the
specifications of all IPs to determine the IP requirements such
as the memory space for slave IPs, internal memory size and
the number of external pins. Second, the system memory map
for all ARM high-performance bus (AHB) slave IPs and the
arbitration mechanism for all AHB master IPs are decided
according to the system performance and design complexity.
Finally, the MP-SoC platform, which consists of an implemen-
tation platform and a verification environment, was created. In
the meantime, the system/IP specifications such as chip/IP IO
pins and constraints are developed and used in the following IP,
logic, and physical implementation flows.
IP Block Design Flow: In order to integrate the IPs into our
platform easily and smoothly, we created an IP block design
flow. Project teams start with their own IP design according
to their functional specifications. Next, integrates the IP into
MP-SoC implementation platform by a standard AHB wrapper.
Logic and Physical Implementation Design Flows: To en-
sure the complex SoC system can be realized successfully is the
goal of these two implementation flows. After all IPs’ register-
transfer-level (RTL) designs from universities are gathered, the
whole chip RTL simulation is performed to ensure the correct
functions. The whole chip design is synthesized according to
the whole chip constraints, and then static timing analysis and
gate-level simulation are performed. The prelayout gate-level
netlist is then delivered to physical implementation design flow.
The layout is produced by a PR tool. The RC extraction,
static timing analysis, and whole chip postgate-level simulation
are performed, with DRC and LVS also done to ensure the
layout correctness. Finally, the GDSII is taped out to the TSMC
foundry. In summary, the design flows described in this section
Fig. 7. Overall MP-SoC design flow.
not only provide an environment for IP creation and integration
but also seamlessly leverage the various state-of-the-art EDA
tools to accomplish the necessary design tasks.
Fig. 7 shows the high-level view of the MP-SoC system
design flow, where the shaded rectangles represent jobs done by
universities and the nonshaded rectangles represent jobs done
by CIC, and the dotted rectangles are those done by CIC and
universities collaboratively.
First, the test environment planning and architecture of the
system are specified in this design flow. In this stage, the test
planning is decided, the basic hardware components are identi-
fied, and the component interfaces, including data and control
signals, are fixed. Next, the multipoint control protocol and the
whole chip verification environment are created. The system
and the IP specifications are derived as well. The system/IP
specifications and implementation platform are then used for
IP development. In the IP block design stage, the universities
joining the MP-SoC project are required to follow the pro-
posed IP block design guideline and to verify their IPs using
the proposed verification environment. After all the IPs are

Fig. 8. MP-SoC-I block diagram.
designed and well verified, all IPs are integrated into the
MP-SoC platform and the logic implementation according to
the system specification is performed. The physical implemen-
tation is finally completed and the resultant circuit is sent to
TSMC for tape out.
IV. DESIGN AND IMPLEMENTATION
OF MP-SOC-I TEST CHIP
A. Chip Design and Implementation
Based on the design flows presented in Section III, design-
ers can easily describe their design concepts, use EDA tools
and the design flows, and tape out chips to accomplish an
MP-SoC system design. To further demonstrate the efficiency
of the MP-SoC design concept and methodology, a test chip,
referred to as MP-SoC-I, has been designed and implemented,
as shown in Fig. 8. The test chip is constructed with the ARM
AMBA bus architecture [22] containing an AHB for high-
performance devices and an ARM peripheral bus (APB) for
low-cost peripheral devices.
The major components of the AHB bus include an
ARM922T CPU core, some internal memory, and a TIC mod-
ule, while the main components of the APB bus are a timer,
an interrupt controller, and a remap/pause controller. The com-
munication protocols between the MP-SoC chip and the off-
chip devices are the external memory interface, debug interface,
interrupt, and some control signals. In addition, there are two
kinds of off-chip memory systems provided in our MP-SoC
system: One consists of Flash and SDRAM memory and the
other consists of ROM and SRAM memory. Users can select
the appropriate memory interface for their design.
The MP-SoC project includes eight SoC design projects
developed by four universities in Taiwan and CIC. The IPs
developed by university partners include an AES engine for
communication systems, a discrete wavelet transform engine
for image compression, a reduced instruction set computer
(RISC) processor (A7 RISC) for system control, a scaled dis-
crete cosine transform type IV and an inverse modified discrete
cosine transform engine for MP3 application, two advanced test
platforms (ATP) for SoC testing, and a ME devices engine for
video compression.
This integrated platform is capable of handling various ap-
plications, such as communication, image, and video/audio
processing, as well as SoC testing.
B. Chip Measurement Results
Based on the design flow, the integrated platform was de-
signed and fabricated, as shown in Fig. 9, where the TSMC
0.13-µm 1P8M logic process was employed.
Table III summarizes the features and measured character-
istics of the integrated platform. The resulting core size is
about 3700 × 3700 µm2
and the overall chip size is 4950 ×
4938 µm2
including the 256 I/O pads, i.e., 104 power pads and
152 signal pads. The chip was successfully operated at 10-ns
clock cycle time, i.e., 100-MHz system clock rate. The gate
count of each project IP was calculated from the layout areas,
which were estimated the layout area of a two-input NAND
for a gate. From the layout view and die photo, one can see
that the ARM922T CPU occupies a large portion of the total
chip area. Experimental results also show that the integrated
chip is 4950 × 4938 µm2
, or 24.43 mm2
. On the other hand,
if these eight SoC projects were fabricated individually, the
sum of their areas is 143.03 mm2
. Thus, our MP-SoC-I test
chip can save around 82.91% silicon area as compared to the
individually fabricated chips. The fabrication cost reduction is
significant.
This chip has been tested by the Agilent 93000 ATE equip-
ment through a customized development board. A shmoo plot
is a graphical display of the response of a test chip varying over
a range of conditions and inputs. It is often used to represent
the results of test chip. The plot usually shows the range
of conditions in which the test chip will operate [23]. With
variations of supply voltage and operating frequency, Fig. 10
shows the shmoo plot of the MP-SoC-I test chip. Results show
that the test chip can successfully operate at 100-MHz clock

Fig. 9. Integrated SoC. (a) Layout view. (b) Die photo.
TABLE III
FABRICATION DATA OF INTEGRATED SoC
rate when the power supply is 1.2 V. In fact, the measurement
confirms the aforementioned result.
V. PROGRAMMABILITY
This implementation integrates the individual SoC projects
into a single chip to share the common platform. When the
individual projects are to perform their own functions and to
measure their own performance, this implementation provides
Fig. 10. Shmoo plot of measurement result using the ATE.
three different schemes for isolating each individual project
from the others.
Since the master IPs issue the read or write requests to the
slave IPs, the interference due to inappropriate request from
master IPs must be taken into consideration. In this implemen-
tation, as shown in Fig. 11, there are six masters on AHB bus
and the priority lists from high to low are TIC, pause controller,
ATP1, ATP2, A922T, and A7 RISC. In order to avoid the bus
interference from master IPs, an isolation mechanism is shown
in Fig. 11. It is comprised of four sets of 2-to-1 multiplexers,
which are used to select one of the four masters using four
external isolation pins ATP1_EN, ATP2_EN, A922T_EN, and
A7_EN.
As for the arbitration mechanism, in general, four basic types
of arbitrator algorithms can be used: Fixed, Round Robin [24],
Lottery, and time-division multiplexing (TDM) [25]. The main
concern is the tradeoff between hardware overhead and speed
requirement. Table IV shows the comparisons of arbitrator area
cost for different arbitration algorithms when these arbiters
are implemented in TSMC 0.13-µm technology. Although the
Round Robin, Lottery, and TDM algorithms can provide a
better performance, we still adopted the Fixed architecture in
the MP-SoC-I test chip due to its simplicity and better success
opportunity for this first MP-SoC design.
However, the aforementioned programmable scheme does
not guarantee the IP protection. It is necessary to physically
isolate the unwanted IPs to each individual project. An alterna-
tive way is to apply a power source to the individual IP. The
individual IP is isolated when the power is off. There are two
ways to turn off the power sources.
The second programming scheme is to apply the laser cut. In
other words, the unwanted IPs are physically isolated from the
integrated platform. This is referred to as physical programming
scheme.
The third programmable scheme is the use of power-gating
scheme to isolate the unwanted IPs. The use of isolation cell, as
shown in Fig. 12, can prevent unknown signals from entering
the receiving island. The cell is used only if both islands are at
the same voltage whenever they are powered up.
The physical programming scheme using laser cut can be
applied to the integrated platform only once, and the signal
lines are permanently isolated. Thus, one can easily estimate the
performance and power consumption. On the other hand, the
electrical programming scheme using power-gating approach
can reprogram the platform. However, extra circuitry may be
needed to implement the power-gating scheme.

Fig. 11. Isolation mechanism.
TABLE IV
COMPARISONS OF ARBITRATOR AREA COST FOR DIFFERENT
ARBITRATION ALGORITHMS
Fig. 12. Power-gating scheme.
VI. CONCLUSION
Low-cost silicon prototyping techniques are very helpful
for verifying the functionality and performance of SoC design
projects. This paper proposes a novel platform-based SoC
design methodology that integrates many SoC design projects
and shares the common platform and associated IPs. The ex-
perimental results show that the silicon area can be signifi-
cantly reduced. Once the integrated platform is fabricated, each
individual SoC design must be isolated from other projects
in order to measure its functionality, performance, and power
consumption. Three programming schemes were developed for
the isolation.
It should be mentioned that the FPGA devices can be im-
plemented for the purpose of prototyping. It can be perfectly
employed for functional verification. However, the speed per-
formance has limited for the high-speed real time operation and
for siliconproof of real chips. This motivates the development
of MP-SoC.
The CIC is a nonprofit organization serving the university
faculty in Taiwan to realize their SoC design projects. Under the
constraint of limited budget for chip fabrication, the innovative
service model using proposed MP-SoC design methodology
has successfully provided the opportunity to silicon prototype
the university SoC projects.
ACKNOWLEDGMENT
The authors would like to thank the anonymous referees for
providing many valuable comments to improve the quality of
this paper.
REFERENCES
[1] H. Chang, L. R. Cooke, M. Hunt, G. Martin, A. McNelly, and
L. Todd, Surviving the SoC Revolution: A Guide to Platform-based
Designs. Norwell, MA: Kluwer, 1999.
[2] W. Cesario, D. Lyonnard, G. Nicolescu, Y. Paviot, S. Yoo,
A. A. Jerraya, L. Gauthier, and M. Diaz-Nava, “Multiprocessor
SoC platforms: A component-based design approach,” IEEE Des. Test.
Comput., vol. 19, no. 6, pp. 52–63, Nov./Dec. 2002.
[3] J. S. Hwang, “Multi-project chip service for university and industry in
Taiwan,” in Proc. IEEE Asia South Pacific Des. Autom. Conf., 1997,
pp. 359–363.
[4] B. Courtois, “MPC services available worldwide,” in Proc. IEEE Asia-
Pacific Conf. Circuits Syst., 1994, pp. 266–275.
[5] C. M. Kyung, I.-C. Park, and H.-J. Song, “Multi-project chip activities in
Korea-IDEC perspective,” in Proc. IEEE Asia South Pacific Des. Autom.
Conf., 1997, pp. 353–357.
[6] Seamless CVE, Mentor Graphics Corp., Wilsonville, OR. [Online].
Available: http://www.mentor.com
[7] Platform Architect, CoWare, Inc., San Jose, CA. [Online]. Available:
http://www.coware.com
[8] Virtex II Pro Protoboard, Xilinx, Inc., San Jose, CA. [Online]. Available:
http://www.xilinx.com
[9] Nios II Development Kit, Stratix II Edition, Altera Corp., San Jose, CA.
[Online]. Available: http://www.altera.com
[10] System Explorer MP4CF, Aptix Corp., Sunnyvale, CA. [Online].
Available: http://www.aptix.com
[11] J. J. Rodriguez-Andina, M. J. Moure, and M. D. Valdes, “Features, design
tools, and application domains of FPGAs,” IEEE Trans. Ind. Electron.,
vol. 54, no. 4, pp. 1810–1823, Aug. 2007.
[12] E. Monmasson and M. N. Cirstea, “FPGA design methodology for in-
dustrial control systems—A review,” IEEE Trans. Ind. Electron., vol. 54,
no. 4, pp. 1824–1842, Aug. 2007.
[13] M. N. Cirstea and A. Dinu, “A VHDL holistic modeling approach and
FPGA implementation of a digital sensorless induction motor control
scheme,” IEEE Trans. Ind. Electron., vol. 54, no. 4, pp. 1853–1864,
Aug. 2007.
[14] E. Ishii, H. Nishi, and K. Ohnishi, “Improvement of performances in bi-
lateral teleoperation by using FPGA,” IEEE Trans. Ind. Electron., vol. 54,
no. 4, pp. 1876–1884, Aug. 2007.
[15] M.-W. Naouar, E. Monmasson, A. A. Naassani, I. Slama-Belkhodja, and
N. Patin, “FPGA-based current controllers for ac machine drives—A
review,” IEEE Trans. Ind. Electron., vol. 54, no. 4, pp. 1907–1925,
Aug. 2007.
[16] S. Sanchez-Solano, A. J. Cabrera, I. Baturone, F. J. Moreno-Velo, and
M. Brox, “FPGA implementation of embedded fuzzy controllers for ro-
botic applications,” IEEE Trans. Ind. Electron., vol. 54, no. 4, pp. 1937–
1945, Aug. 2007.
[17] F. Iannuzzo, “Race-control algorithm for the full-bridge PRCP converter
using cost-effective FPGAs,” IEEE Trans. Ind. Electron., vol. 55, no. 4,
pp. 1519–1526, Apr. 2008.
[18] Z. Shu, Y. Guo, and J. Lian, “Steady-state and dynamic study of active
power filter with efficient FPGA-based control algorithm,” IEEE Trans.
Ind. Electron., vol. 55, no. 4, pp. 1527–1536, Apr. 2008.

[19] C.-M. Huang, K.-J. Lee, C.-C. Yang, W.-H. Hu, S.-S. Wang, J.-B. Chen,
L.-D. Van, C.-M. Wu, W.-C. Tsai, and J.-Y. Jou, “Multi-project system-
on chip (MP-SoC): A novel test vehicle for SoC silicon prototyping,” in
Proc. IEEE SoC Conf., 2006, pp. 137–140.
[20] Y.-K. Lai and L.-F. Chen, “High-throughput configurable motion estima-
tion processor core for video applications,” Jpn. J. Appl. Phys., vol. 45,
no. 4B, pp. 3330–3335, 2006.
[21] H.-C. Wang, C.-H. Lin, and A.-Y. Wu, “Design and implementation of
cost-effective AES cryptographic engine,” Dept. Elect. Eng., Nat. Taiwan
Univ., Taipei, Taiwan, Tech. Rep., Jun. 2003.
[22] ARM Ltd., AMBA Specification Revision 2.0, May 1999. [Online].
Available: http://www.arm.com
[23] K. Baker and J. Van Beers, “Shmoo plotting: The black art of IC testing,”
IEEE Des. Test. Comput., vol. 14, no. 3, pp. 90–97, Jul.–Sep. 1997.
[24] E. S. Shin, V. J. Mooney, III, and G. F. Riley, “Round-robin arbiter design
and generation,” in Proc. Int. Symp. Syst. Synthesis, 2002, pp. 243–248.
[25] K. Lahiri, A. Raghunathan, and G. Lakshminarayana, “LOTTERYBUS:
A new high-performance communication architecture for system-on-chip
designs,” in Proc. IEEE/ACM Des. Autom. Conf., 2001, pp. 15–20.
Chun-Ming Huang (M’03) received the B.S. degree
in mathematical science from National Chengchi
University, Taipei, Taiwan, in 1990 and the M.S. and
Ph.D. degrees in computer science from National
Tsing-Hua University, Hsinchu, Taiwan, in 1992 and
2005, respectively.
Since 1993, he has been with the National Chip
Implementation Center, Hsinchu, where he is cur-
rently a Researcher and Department Manager in the
Design Service Department. His research interests
include very large scale integration design and test-
ing, platform-based system-on-a-chip design methodologies, and multimedia
communication.
Dr. Huang is a member of Phi Tau Phi Scholastic Honor Society.
Chien-Ming Wu (M’08) received the B.S. and
M.S. degrees in electronic engineering from National
Yunlin University of Science and Technology,
Yunlin, Taiwan, in 1997 and 1999, respectively, and
the Ph.D. degree from the Graduate School of En-
gineering Science and Technology, National Yunlin
University of Science and Technology, in 2003.
He is currently a Researcher and Deputy Depart-
ment Manager with the National Chip Implementa-
tion Center, Hsinchu, Taiwan. His research interests
include very large scale integration design in com-
munication, coding theory, platform-based system-on-a-chip design, and digital
signal processing.
Chih-Chyau Yang received the B.S. degree in elec-
trical engineering from National Cheng Kung Uni-
versity, Tainan, Taiwan, in 1996 and the M.S. degree
in electronics engineering from National Chiao Tung
University, Hsinchu, Taiwan, in 1999.
Since 2000, he has been with the National Chip
Implementation Center, Hsinchu, where he is cur-
rently an Associate Researcher and Section Manager
in the Design Service Department. His research in-
terests include very large scale integration design,
computer architecture, and platform-based system-
on-a-chip design methodologies.
Shih-Lun Chen received the B.S. and M.S. degrees
in electrical engineering from National Cheng Kung
University, Tainan, Taiwan, in 2002 and 2004, re-
spectively, where he is currently working toward the
Ph.D. degree.
He is currently an Associate Researcher with the
National Chip Implementation Center, Hsinchu. His
research interests include very large scale integration
design, image process, wireless sensor network, re-
configurable processor, and platform-based system-
on-a-chip design methodologies.
Chi-Shi Chen received the B.S. and M.S. degrees
in electronics engineering from National Chiao Tung
University, Hsinchu, Taiwan, in 1997 and 1999,
respectively.
He is currently an Associate Researcher and
Deputy Department Manager with the National
Chip Implementation Center, Hsinchu. His research
interests include very large scale integration de-
sign and platform-based system-on-a-chip design
methodologies.
Jiann-Jenn Wang received the B.S. degree in
physics from the National Tsing Hua University,
Hsinchu, Taiwan, in 1979 and the M.S. degree in
electronics engineering from National Chiao-Tung
University, Hsinchu, in 1984.
He is currently the Deputy Director General of
National Chip Implementation Center, National Ap-
plied Research Laboratories, Hsinchu. His current
research interests include very large scale integra-
tion design, system-on-a-chip design, and computer
architecture.
Kuen-Jong Lee (M’84) received the B.S. degree in
electrical engineering from National Taiwan Univer-
sity, Taipei, Taiwan, the M.S. degree in electrical and
computer engineering from the University of Iowa,
Iowa City, and the Ph.D. degree in electrical engi-
neering from the University of Southern California,
Los Angeles.
He joined the faculty of National Cheng Kung
University, Tainan, Taiwan, in 1991 and is currently
a Professor with the Department of Electrical En-
gineering. He is the holder of five R.O.C. and four
U.S. patents. His interests include the design and test of digital circuits with
main focuses on system-on-a-chip testing/debugging and electronic system
level design.
Dr. Lee was a Program Cochair of 2000 Asian Test Symposium (ATS), a
General Cochair of ATS 2004, the General Chair of 2002 Very Large Scale In-
tegration (VLSI)/Computer-Aided Design Symposium and the Program Chair
of 2009 VLSI Design, Automation and Test Symposium. He founded the
IEEE Circuits and Systems Tainan Chapter and served as the first chairman
during 2005–2006. He received the Exceptional Contribution Award from
National Applied Research Laboratories in 2007 and the Outstanding Project
Achievement Award from the National Science Council of Taiwan in 2007.
Chin-Long Wey (M’83–SM’97) received the Ph.D.
degree in electrical engineering from Texas Tech
University, Lubbock, in 1983.
He was the Dean of College of Electrical En-
gineering and Computer Science, National Central
University (NCU), Jhongli, Taiwan, in 2003–2006.
He came to NCU from Michigan State University,
where he was a tenured Full Professor of the Electri-
cal and Computer Engineering Department and had
worked with MSU for 20 years (1983–2003). He is
currently the Taiwan Semiconductor Manufacturing
Company Distinguished Chair Professor of electrical engineering with NCU,
and the Vice President and Director General with the National Chip Implemen-
tation Center, Hsinchu, Taiwan. His research interests include design, testing,
and fault diagnosis of analog/mixed-signal very large scale integration circuits
and systems; digital circuit design automation; defect/fault-tolerant and reliable
embedded computing systems; and reliable real-time embedded computing
systems. He has published more than 200 technical journal and conference
papers in these areas.

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