PROJECT PPT.Wallace tree multiplier using Adder
- 1. Bapuji Educational Association® Bapuji Institute of Engineering and Technology Davangere-577 004 Department of Electronics & Communication Engineering 2024-25 Presentation on Project title confirmation: “VLSI Implementation of Wallace Tree Multiplier Using Ladner-Fischer Adder” Project Associates, CHANDAN K. 4BD21EC403 NANDITHA D. 4BD21EC412 NAVEEN N. 4BD21EC413 NESARA M. 4BD21EC414 1 Dr.Nirmala S O M.Tech, Ph.D. Project Guide Dr.G S Sunitha M.Tech. (DEAC), Ph.D., MISTE, FIETE., FIE Program Coordinator
- 2. BAPUJI INSTITUTE OF ENGINEERING AND TECHNOLOGY, DAVANGERE-577004 Vision of the Institute: To be a centre of excellence recognized nationally and internationally, in distinctive areas of engineering education and research, based on a culture of innovation and invention. Mission of the Institute: BIET contributes to the growth and development of its students by imparting a broad based engineering education and empowering them to be successful in their chosen field by inculcating in them positive approach, leadership qualities and ethical values. 2
- 3. Department of Electronics and Communication Engineering Vision of the Department: To be in the forefront in providing quality technical education and research in Electronics & Communication Engineering to produce skilled professionals to cater to the challenges of the society. Mission of the Department: ⚬To facilitate the students with profound technical knowledge through effective teaching learning process for a successful career. ⚬To impart quality education to strengthen students to meet the industry standards and face confidently the challenges in the programme. ⚬To develop the essence of innovation and research among students and faculty by providing infrastructure and a conducive environment. ⚬To inculcate the student community with ethical values, communication skills, leadership qualities, entrepreneurial skills and lifelong learning to meet the societal needs. 3
- 4. OBJECTIVE: 4 The following objectives are considered for the project: 1. To design and implement Wallace Tree Multiplier. 2. To develop Enhanced WTM using Ladner Fischer Adder. 3. To compare performance of different multiplier architectures. 4. To evaluate FPGA resource utilization.
- 5. BLOCK DIAGRAM: 5 Figure : Block diagram of proposed WTM
- 6. 6 • Figure shows the block diagram of the project.It follows a structured approach to efficiently compute multiplication using optimized addition techniques. • It begins with the Input Operands stage, where two 16-bit binary numbers (A and B) are provided as inputs. • These numbers are then processed in the Partial Product Generator, where 256 partial products are generated using simple AND gates by multiplying each bit of the multiplicand with each bit of the multiplier. • To manage this large number of partial products, the design employs CSA Stages 1 and 2, where 4:2 compressors are used to efficiently reduce the number of bits at each stage, minimizing carry propagation delay. • The process continues in CSA Stage 3, where another layer of 4:2 compressors is used to further compress the partial products, ensuring that the design remains optimized for high-speed operations. • Once the partial products are sufficiently reduced, they are summed in the Final LFA, which minimizes routing congestion and ensures faster computation by handling the final summation efficiently. • Finally, the processed data reaches the Output Stage, where the final 32-bit product of the 16×16 multiplication is obtained, making the overall design highly efficient in terms of speed and logic utilization.
- 7. METHODOLOGY: The process begins with Partial Product Generation (PPG), where the 16-bit multiplicand and multiplier are multiplied bit- by-bit to produce partial products, which are then aligned according to their respective bit positions. In the first stage, Carry-Save Adders (CSAs) with 4:2 compressors are used to group these partial products into sets of four and reduce them into two rows of sums and carries. These sums and carries are propagated to the next stage. In the second stage, the outputs from the first CSA stage are further reduced by using additional 4:2 compressors, combining the sums and carries into two rows. A final CSA stage follows, further minimizing the number of rows to two through similar CSA structures. The final addition is performed with a LFA, which efficiently adds the remaining two rows of sums and carries to generate the final 16-bit product output. Performance optimization is achieved by minimizing delay and ensuring efficient resource utilization, particularly through strategic placement and pipelining of the 4:2 compressors and the LFA. Finally, the design is mapped to FPGA resources, where key Preamblemetrics such as area, power, and timing are evaluated and compared with alternative architectures.
- 8. APPLICATION: 7 • Further Power Optimization: Implementing low-power techniques, such as clock gating and operand isolation, can help reduce dynamic power consumption in the design. • Implementation on FPGA and ASIC: The proposed design can be synthesized on FPGAs like Spartan-6 or Intel FPGAs and optimized for ASIC fabrication to evaluate real-time performance. • Exploring Different Compressors: Investigating higher-order compressors (e.g., 7:3 or 9:4 compressors) could further improve speed and reduce hardware complexity. • Pipeline Implementation: Introducing pipelining techniques can enhance the throughput, making the multiplier suitable for real-time DSP and AI applications. • Comparative Analysis with Other Adders: Future work could explore KoggeStone or Han-Carlson adders in place of Ladner-Fischer to determine the best trade-off between area, speed, and power. • Application in Cryptographic Systems: The optimized WTM can be integrated into hardware-based encryption algorithms such as AES, ECC, and RSA, improving their computational efficiency.