Range Extended Second Order Digital Phase Locked Loop

ACEEE International Journal on Communication, Vol 1, No. 2, July 2010

Range Extended Second Order
Digital Phase Locked Loop
Santanu Chattopadhyay
Physics Department, J K College, Purulia
West-Bengal, India
E-mail: chattopadhyaysantanu@yahoo.co.in; santanuphy@yahoo.in

Abstract — A new structure of second order digital phase establish the merit of extension of the FAR of the
locked loop (DPLL) called modified second order DPLL modified structure keeping the advantages of quick
(MSODPLL) has been proposed. The phase error convergence. Determination of acquisition properties
dynamics of a conventional second order DPLL of the loop analytically is very tough, if not
(CSODPLL) and that of a MSODPLL have been studied
using digital computers. Ranges of initial conditions
impossible. So we relied on simulation results of the
leading to the phase locking condition were determined loop acquisition process. In section II the system
from computer simulation of both conventional and equation of the loop has been shown. In section III the
modified second order DPLL Using these observations simulation results of the acquisitions of the
the larger frequency acquisition range (FAR) of the conventional and modified loop have been shown.
MSODPLL compared to the CSODPLL has been From these simulation results the superiority in respect
established. of the FAR of the MSODPLL over CSODPLL has
been established.
I. INTRODUCTION
Nonuniforms sampling digital Phase Locked Loops II. SYSTEM MODEL
(DPLLs) are widely used in coherent communication Fig 1 shows the block diagram of the CSODPLL.
system. The most popularly used DPLL is the positive The input signal to the DPLL Asin (ωt + ϑ(t)) is
going zero-crossing sampling type digital phase-locked sampled by the pulses from the digitally controlled
loop (ZC1-DPLL). Application of second order ZC1- oscillator (DCO).
DPLL is extensive for extraction of carrier phase from
the received signal [1,2,11,12]. INPUT SAMPLER &
DELAY
QUANTIZER
The following points about a conventional second
order ZC1-DPLL (CSODPLL) can be revealed from
earlier works reported in literature. (i) The system +
dynamics of a CSODPLL is sensitive to the initial
value of the state variables [3-5, 8-10]. (ii) The choice
G
DELAY
of the loop design parameters is a critical issue to get a 1

stable locked state of the loop and at the same time
convergence time to steady state of the loop is also
dependent on loop design parameters [6-8]. (iii) The
boundary region of initial condition leading to signal
DCO + G 2
0

acquisition is not smooth; this region is very much
DIGITAL
sensitive to the initial condition [4, 5]. (iv) CSODPLL FILTER (2nd
Ord)
has a finite frequency acquisition range (FAR), SUM (0)

bounded on both side of the loop nominal frequency Figure 1 Block diagram of a CSODPLL with SUM as initial
(f0), determined by loop parameters [3, 5].In this paper control parameter.
a modification algorithm of a CSODPLL has been
proposed to extend the FAR. This proposed modified The algorithm of the loop DCO is given by
second order DPLL (MSODPLL) is almost similar to
the modified structure used in [6-8], in which a T(k+1) = T0 – y(k) = t(k+1) – t(k) ( 1)
weighted error signal added with the sampled signal, in Where T0 is the DCO nominal period and y(k) is the
addition it possesses the facilities of initialization of its output
accumulator contents and the gain of the additional of the loop digital filter (LDF) at the k-th sampling
error signal can be controlled. In [7] quick acquisition instant at t(k). In terms of the LDF parameters (G 1 and
of the loop was established, whereas in [8] authors G2) and the sampler output ( Asinφ(k) ), the LDF
established the extension of limit before bifurcation of output y(k) is given as
the steady state phase error. The aim of this paper is to
University Grants Commission - India

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© 2010 ACEEE
DOI: 01.ijcom.01.02.01


k–1 MSODPLL. In a MSODPLL the input to LDF at the k-
y(k) = (G1+G2)Asinφ(k)+G2A ∑sinφ(i) (2) th instant is
i=0 Asin φ(k) + P{Asin φ(k) – Asin φ(k–1)} (8)

Where φ (k) is the loop phase error defined as The MSODPLL becomes the conventional loop if P
is equal to zero and there is no initialization of SUM
k–1 (SUMI) input. Following similar procedure the phase
φ(k)= (ω−ω0)t(k) + θ(t(k)) –ω0∑y(i) (3) governing equation of the MSODPLL can be had as
i=0 φ(k+2) = 2φ(k+1) – φ(k) – Z(K1+K2) (1+P) sinφ(k+1)
+
Defining the content of the accumulator as a state
variable SUM (k) as Z{K1{1+ 2P) + K2P} sinφ(k) + ZK1 P sinφ(k-1)
k–1 (9)
SUM (k) = ∑ sinφ(i) (4)
It is easy to note that when P = 0, eqn. “(9)” reduces to
i=0 eqn. “(6)”. From this one can easily study and confirm
the quick acquisition of the loop [7].
Therefore from “(3)” one can have the system
phase governing equation for a modulation free input
signal (i.e. θ(t(k)) = θ(t(k-1)) )as FREQUENCY LOGIC To SUM Input and
DISCRIMINATOR CIRCUIT GAIN Control

φ(k+1) = 2π(Z–1) + φ(k) – Z(K1+K2)sinφ(k)
– K2ZSUM(k) (5) INPUT SAMPLER &
QUANTIZER

Where Z = ω/ω0, K1= G1Aω0 and K2= G2Aω0. The GAIN Control
phase error dynamics for a given loop (K 1 & K2) with an (From Logic
Circu it)
incoming signal ω (i.e. given Z) can be examined with
DELAY

“(5)” for a set of variable with initial φ(0) and SUM(0).
By taking the difference of two consecutive phase errors
in “(5)” one can come to another phase governing
COMP GAIN
(P) +
equation as in [9]. This equation is as follows

φ(k+2) = 2φ(k+1) – φ(k) – Z(K1+K2)sinφ(k+1)
+ ZK1 sinφ(k) (6) DIGITAL
DCO FILTER(2nd
It is easy to find from “(5)” or “(6)” that if the Ord)

acquisition of the signal is achieved (i.e. iteration
converges to a steady state value), the steady state SUMI (From Logic
phase error value of φ is zero. Thus there is no phase Circuit)

error between the incoming signal and the DCO pulses Figure 2 Block diagram of MSODPLL.
in the steady state of the loop. With a little bit of
algebra it can easily be proved that the acquisition is
achieved only in the range of K1Z [4, 6]
III. SIMULATION RESULTS
0 < K1Z <4/1(1+r) (7)
The phase error dynamics of the DPLL have been
i.e. Z has an upper limit, but the lower limit is zero. observed by simulating the system in real time in a
But in [3, 5] the authors established that Z has both digital computer. In our study the system was simulated
upper and lower limit. It has also been established in [9]
by simulating each individual ideal building block of
that acquisition time is minimum when K 1 = K2 = 1.
Thus if one wants to increase the loop frequency the DPLL in real time in a digital computer. Then the
acquisition range there is degradation due to increased time development of the loop phase errors for a given
loop convergence time. In [6, 7] authors proposed loop loop parameters (K1 & K2) was noted by noting the
structure to achieve quick convergence of the loop. In output from S/H block and hence the loop phase error
this paper we want to propose a modification algorithm value in each sampling instant is obtained. In this
to increase the loop FAR keeping the advantages of simulation the loop parameters (K1 & K2), or the centre
quick convergence. frequency of the DCO (2π/T0), or the incoming signal
Now let us come to the structure and system equation of frequency (ω0/2π), or the initial accumulator content
MSODPLL. Fig 2 gives the block diagram of the SUM(0) etc. can be given as input in the simulation

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© 2010 ACEEE
DOI: 01.ijcom.01.02.01


program. The phase errors φ(k)’s are taken as modulo using the simulations we want establish that we can
2π quantity within -π to π because of the sinusoidal non increase this FAR using MSODPLL.
linearity term in the system equation. The upper limit of Now let us consider the frequency of the incoming
initial value of the accumulator content SUM(0) is signal other than the DCO nominal frequency. Figure 4
specified from physical consideration that the (k+1)-th represents the ranges of initial condition (φ(0) and
SI should be later than k-th SI. So from “(1)” one SUM(0)) leading to the locked state of the CSODPLL
obtains the initial value of the SUM(0) should be less with K1 & K2 = 1.2 and Z=1.2. It is easy to note from
than (2π/K2). figure-4 that a CSODPLL does not converges to steady
From the simulation initial condition (φ(0) and state for signal detuning value Z =1.2 in the large
SUM(0)) leading to the locked state of the CSODPLL portion of the initial values of the state variables (φ(0)
is found out. Actually all initial condition may not lead and SUM(0)). Therefore a CSODPLL can’t acquire
to proper locking of the loop though the incoming this incoming signal with increased incoming signal
signal frequency is within locking range or even the frequency or in other word this incoming frequency is
incoming signal frequency is same as DCO nominal outside the FAR of this CSODPLL.
frequency [5]. the simulation result shows the steady
state output from the sampler of the loop is zero in the
locked state if the lock is achieved, as expected from
eqn. “(5)” or “(6)”. Therefore in the locked state the
phase of the DCO is same as the phase of incoming
signal, and its increment in each step is 2π. This is the
advantage of the second order DPLL over first order
DPLL. In a second order DPLL accumulator content
provides the DCO control signal.
The dots in figure 3 represents the ranges of initial
condition (φ(0) and SUM(0)) leading to the locked state
of the CSODPLL with K1 & K2 = 1. Loop parameters
K1 & K2 = 1 produce fastest acquisition in a CSODPLL
[1, 5, 7, 9]. From the figure it is found that the loop Figure 4. Ranges of initial condition of CSODPLL with K1 & K2 =
converges to steady state for both positive and negative 1.2 leading to frequency locking for Z =1.2
values of initial SUM in the entire ranges of initial
phase error PHI (φ) between - π to π. Now let us consider the case of acquisition of a
MSODPLL with same loop parameter and incoming
signal frequency. It is found from figure 5 that a
MSODPLL with same parameter values converges to
steady state in the large portion of initial values of the
state variables in same signal condition. Therefore a
MSODPLL can acquire this incoming signal which was
beyond the FAR of a CSODPLL.

Figure 3 Ranges of initial condition of a CSODPLL leading to
same frequency locking for Z =1

Taking zero initial SUM, the ranges of Z leading to
proper acquisition of the signal (i.e. DCO is phase
coherent with incoming signal) by a CSODPLL (with
different K1 & K2) for all possible initial phase of the
incoming signal have been found out from the Figure 5. Ranges of initial condition of MSODPLL with K1 & K2 =
1.2 and P = -0.1 leading to frequency locking for Z =1.2
simulation. This gives us the FAR of the conventional .
loop. Variations of FAR of a CSODPLL with different
Similarly figure 6 shows that a CSODPLL (with loop
K1 & K2 have been found out and it is shown in figure
parameter K1 & K2 = 1.2) does not converges to steady
9. This result establishes the fact that the upper limit of
state for signal detuning value Z = 0.8 in the large
FAR of a CSODPLL is almost as per equation “(7)”
portion of initial values of the state variables. So it
but there is a lower limit [3, 5]. In the present paper

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© 2010 ACEEE
DOI: 01.ijcom.01.02.01


cannot also lock the lower incoming signal frequency variation of the upper and lower limit of Z that can be
beyond a range shown in figure 9. acquired has been shown in figure 8. It is clear from
the result that the FAR can be increased using SUM
initializing.

Figure 6. Ranges of initial condition of CSODPLL with K1 &
K2 = 1.2 leading to frequency locking for Z = 0.8

But a MSODPLL with same parameter values and
same detuning as in fig. 6 converges to steady state in
the large portion of initial parameter values. This can
be seen from fig.7. So a MSODPLL can acquire a
signal frequency which was beyond the FAR of a Figure 8. Variation of FAR of MSODPLL (K1=K2=1,P=0) with
initial SUM (positive when Z>1 and negative when Z<1).
CSODPLL in the lower side range. Similar results were
obtained from the simulation with other values of loop
parameters and signal detuning.

Figure 7 Ranges of initial condition of MSODPLL with K1 & K2 =
1.2 and P = -0.1 leading to frequency locking for Z =0.8

These ranges of initial condition leading to
frequency locking are very important as it determines
the range of frequency that can be acquired by a Finally let us consider the effect of control of gain
CSODPLL or a MSODPLL. Therefore from Fig 4 – 7 of the difference signal in a MSODPLL. This effect of
we can conclude that a MSODPLL can acquire signal gain control of the difference signal increases the FAR
with larger limit of Z, i.e. it acquires signal with larger of MSODPLL; this result has been shown in figure 9.
band width, which was not possible with a CSODPLL. Actually when P = 0 in a MSODPLL, it becomes a
Thus the FAR of a MSODPLL is larger than a CSODPLL. From the figure it is found from the
CSODPLL. frequency acquisition range of MSODPLL is much
From the simulation study it is also found that with larger than CSODPLL.
initial SUM other than zero in a second order ZC 1-
DPLL we can acquire a signal which was beyond the IV. CONCLUSION
FAR of a CSODPLL. So we can change the limit of Simulation study clearly shows that MSODPLL
locking of frequency of a second order ZC 1-DPLL with same values of loop parameter converges to the
using initializing the initial SUM at the input. The locked state with larger ranges of signal detuning value

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Z than a CSODPLL. Therefore the lock range is more in [5] B.C.Sarkar and S.Chattopadhyay , “A new look into the
a MSODPLL than a CSODPLL. So MSODPLL is more acquisition properties of a second - order digital phase
locked loop,” IEEE Trans. Commun , vol. 42 , no.-5
suitable in communication systems where larger PP 2087 – 2091 ,May 1994
bandwidth is required like FH spread spectrum or any
[6] B.C.Sarkar and S.Chattopadhyay, “ Novel quick
other similar systems. response digital phase locked loop ”, Electronics
Letters (UK), vol. 24,no. 20,Sept.29, 1988,pp1263
–1264
ACKNOWLEDGMENT [7] B.C.Sarkar and S.Chattopadhyay, “On the structure and
The author thanks the University Grants performance of an extended range quick response
second order DPLL,” Journal of IETE (India),vol.
Commission, India for sponsoring the project (No. 38,no. 6,pp365 – 368 ,1992
F.PSW-029/09-10(ERO)) [8] T. Banerjee, B.C. Sarkar, Phase error dynamics of a
class of modified second-order digital phase locked
loops in the background of cochannel interference,
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DOI: 01.ijcom.01.02.01

Range Extended Second Order Digital Phase Locked Loop

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