REALIZATION OF TRANSMITTER AND RECEIVER ARCHITECTURE FOR DOWNLINK CHANNELS IN 3-GPP LTE

International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.1, February 2013
DOI : 10.5121/vlsic.2013.4102 11
REALIZATION OF TRANSMITTER AND RECEIVER
ARCHITECTURE FOR DOWNLINK CHANNELS
IN 3-GPP LTE
S. Syed Ameer Abbas#1a
, J. Rahumath Nisha#1
,M. Beril Sahaya Mary#1
,
S. J. Thiruvengadam#2b
a
Assistant Professor, b
Professor
#
Department of Electronics and Communication Engineering
1
Mepco Schlenk Engineering College, Sivakasi- 626005, India
1
abbas_mepco@yahoo.com
2
Thiagarajar College of Engineering, Madurai- 625015, India
2
sjtece@tce.edu
ABSTRACT
Long Term Evolution (LTE), the next generation of radio technologies designed to increase the capacity
and speed of mobile networks. The future communication systems require much higher peak rate for the air
interface but very short processing delay. This paper mainly focuses on to improve the processing speed
and capability and decrease the processing delay of the downlink channels using the parallel processing
technique. This paper proposes Parallel Processing Architecture for both transmitter and receiver for
Downlink channels in 3GPP-LTE. The Processing steps include Scrambling, Modulation, Layer mapping,
Precoding and Mapping to the REs in transmitter side. Similarly demapping from the REs, Decoding and
Detection, Delayer mapping and Descrambling in Receiver side. Simulation is performed by using
modelsim and Implementation is achieved using Plan Ahead tool and virtex 5 FPGA.Implemented results
are discussed in terms of RTL design, FPGA editor, power estimation and resource estimation.
KEYWORDS
PBCH, PMCH, PDCCH, PDSCH, PCFICH, OFDM, MBSFN, MBMS
1. INTRODUCTION
The LTE PHY is a highly efficient means of conveying both data and control information
between an enhanced base station and mobile user equipment. LTE physical layer is quite
complex and consists of mixture of technologies. LTE takes advantage of OFDMA, a multi-
carrier scheme that allocates radio resources to multiple users. LTE standard has six physical
layer channels namely, physical Hybrid ARQ Indicator Channel (PHICH), Physical Control
format Indicator Channel(PCFICH), Physical Downlink Control Channel (PDCCH), Physical
Broadcast channel (PBCH), Physical Multicast Channel (PMCH) and Physical Downlink Shared
Channel (PDSCH) for downlink operation[1]. The control signals are transmitted at the start of
each subframe.
LTE supports peak data rates of up to 100 Mbps on the downlink and 50 Mbps on the uplink
when using a 20 MHz channel bandwidth.LTE supports both frequency-division duplex (FDD)
and time-division duplex (TDD), as well as a wide range of system bandwidths in order to operate
in a large number of different spectrum allocations. Throughout this specification, unless

12
otherwise noted, the size of various fields in the time domain is expressed as a number of time
units Ts=1/ (15000 x 2048) seconds. Downlink and uplink transmissions are organized into radio
frames with Tf=307200xTs=10 ms duration. Two radio frame structures are supported and FDD
type is adopted in this paper.Frame structure type 1 is applicable to both full duplex and half
duplex FDD. Each radio frame is Tf =307200xTs=10 ms long and consists of 20 slots of length
Tslot=15360xTs=0.5 ms, numbered from 0 to 19. A subframe is defined as two consecutive slots
where subframe i consists of slots 2i and 2i+1.
Figure 1 Frame Structure for FDD
The transmitted signal in each slot is described by a resource grid of subcarriers and OFDM
symbols. The resource grid structure is illustrated in Figure 2. The quantity
DL
RBN depends on the
downlink transmission bandwidth configured in the cell and shall full fill which is given in (1).
DLmax,
RB
DL
RB
DLmin,
RB NNN ≤≤ ..... (1)
Where 6DLmin,
RB =N and 110DLmax,
RB =N are the smallest and largest downlink bandwidths,
respectively, supported by the current version of this specification [1]. The number of OFDM
symbols in a slot depends on the cyclic prefix length and subcarrier spacing configured. In case of
multi-antenna transmission, there is one resource grid defined per antenna port. An antenna port
is defined by its associated reference signal. The set of antenna ports supported depends on the
reference signal configuration in the cell.Cell-specific reference signals support a configuration of
one, or two antenna ports and the antenna port number shall fulfil 0 or 0 and 1 respectively.
MBSFN reference signals are transmitted on antenna port 3.Each element in the resource grid for
antenna port P is called a resource element and is uniquely identified by the index pair (k,l) in a
slot where 1,...,0 RB
sc
DL
RB −= NNk
and
1,...,0 DL
symb −= Nl
are the indices in the frequency and time
domains, respectively. Resource blocks are used to describe the mapping of certain physical
channels to resource elements. A physical resource block is defined as consecutive OFDM
symbols in the time domain and consecutive subcarriers in the frequency domain. A physical
resource block thus consists of product of the above two resource elements, corresponding to one
slot in the time domain and 180 kHz in the frequency domain. Resource element groups are used
for defining the mapping of control channels to resource elements. A resource-element group is
represented by the index pair (k’,l’) of the resource element with the lowest index k in the group
with all resource elements in the group having the same value of l. The set of resource elements
(k,l) in a resource-element group depends on the number of cell-specific reference signals
configured. Mapping of a symbol-quadruplet <z(i), z(i+1), z(i+2), z(i+3)> onto a resource-
element group represented by resource-element (k’,l’) is defined such that elements z(i) are
mapped to resource elements (k,l) of the resource-element group not used for cell-specific
reference signals in increasing order of i and k.
This paper is organized as follows: Section 2 discusses about the LTE Physical downlink
channels and their functions. Section 3 describes the system model of transmitter and receiver for
the Physical downlink channels based on 3GPP specifications. Section 4 discusses the proposed
architecture for the SISO, MISO and MIMO transmitters and receivers. Section 5 gives the

13
simulated and implemented results for the proposed system of transmitter and receiver. Finally
this paper is concluded with section 6.
Figure 2 Downlink Resource Grid of LTE
2. LTE PHYSICAL DOWNLINK CHANNELS
The Physical Downlink Shared Channel (PDSCH) is used to send common user data and control
information such as paging messages to all mobile devices operating within its coverage area. The
user data is carried on the Physical Downlink Shared Channel. The PDSCH is utilized basically
for data and multimedia transport. It is designed for very high data rates. Modulation schemes in
PDSCH include QPSK, 16QAM and 64QAM. The PDSCH is the main data bearing channel
which is allocated to users on a dynamic and opportunistic basis. In typical cellular systems the
basic system information which allows the other channels in the cell to be conﬁgured and
operated is carried by a Broadcast Channel. The Physical broadcast channel (PBCH) in LTE is
Physical Broadcast Channel. This data are classified into two categories such as Master
Information Block and System Information Block. PBCH is used to carry the system information
to all mobile devices. The PBCH is transmitted using Space Frequency Block Code (SFBC), a
form of transmit diversity, in case of multiple antennas thereby allowing for greater coverage.
The PBCH is designed to be detectable without prior knowledge of system bandwidth and to be
accessible at the cell edge.
Physical Multicast Channel (PMCH) is used for the multimedia data transport.
Multimedia Broadcast and Multicast Services (MBMS) enables a set of eNBs to transfer
information simultaneously for a given duration. This transmission is known as
Multicast/Broadcast over a Single Frequency Network (MBFSN). Multimedia Broadcast
Multicast Services (MBMS) are performed either in a single cell or a multi cell. Transmission of
PDSCH and PMCH in the same subframe is not possible.The Physical Downlink Control
Channel (PDCCH) is the most important control channel. The Physical Downlink Control
Channel carries downlink control information, including downlink scheduling assignments,
uplink scheduling grants and uplink power control commands. PDCCH carries the downlink
resource allocation related to the Physical Downlink Shared Channel (PDSCH) which is a
transport channel. The control information carried by PDCCH is known as Downlink Control
Information (DCI) which is transmitted as an aggregation of Control Channel Elements (CCEs).

International Journal of VLSI design & Communication Systems (VL
CCEs consists of Resource Element
(REs) with a RE carrying two bits. PDCCH carries information about the Resource Block (RB)
allocation, modulation, coding scheme and power control information. PDCCH occupies the first
1, 2, 3 OFDM symbols of a subframe.
DCI for error detection
The Physical Control Format Indicator Channel (PCFICH
OFDM symbols used by the PDCCH to carry the scheduling assignments and other control
information. The information carried by the PCFICH is called as Control Format Indicator (CFI)
and is located in the first OFDM symbol of eac
and 4 (Reserved) and are represented using two bits
(PHICH) is the hybrid indicator channel
PUSCH. The acknowledgement may be positive (ACK) or negative (NACK) depending upon
whether the transmitted data is correctly received or not. If NACK is received then
retransmitted. Multiple PHICHs are mapped to the same set of resource elements (REs). This set
of REs constitutes a PHICH group. The PHICHs within a PHICH group are separated through
different orthogonal sequences. Each PHICH group is mapped to RE groups that have not already
been assigned to the PCFICH.A PHICH group is not dedicated to a single mob
shared amongst eight mobiles, by assigning each mobile a different orthogonal sequence index.
Together the PHICH group number and orthogonal sequence index are known as a PHICH
resource.
3. SYSTEM MODEL
In LTE, the data which is given
processing steps. Figure 3 shows the channel processing steps of transmitter.
channel processing steps of receiver.
Figure
Figure
3.1 CHANNEL PROCESSING ST
3.1.1 Scrambling
The bit by bit code word is bit wise EX
a pseudo random sequence generated using a length 31 gold sequence generator. The cell specific
sequence is used for the purpose of inter
transmitted are passed through this module initially [3]. It is the process of making the code as an
unintelligible to the intruder. The scrambling is performed using (2)
consists of Resource Element Groups (REGs) each containing four Resource Elements
1, 2, 3 OFDM symbols of a subframe. A cyclic redundancy check (CRC) bits are appended to the
Physical Control Format Indicator Channel (PCFICH) carries the information of number of
and is located in the first OFDM symbol of each subframe. The CFI can take the values of 1, 2, 3
and 4 (Reserved) and are represented using two bits [2].The Physical Hybrid Indicator Channel
s the hybrid indicator channel indicates acknowledgement for the uplink channel
ement may be positive (ACK) or negative (NACK) depending upon
whether the transmitted data is correctly received or not. If NACK is received then data should be
Multiple PHICHs are mapped to the same set of resource elements (REs). This set
been assigned to the PCFICH.A PHICH group is not dedicated to a single mobile, instead it is
In LTE, the data which is given to the transmitter should experience the following ch
shows the channel processing steps of transmitter. Figure
channel processing steps of receiver.
Figure 3 General Modules for Transmitter
Figure 4 General Modules for Receiver
HANNEL PROCESSING STEPS OF TRANSMITTER
The bit by bit code word is bit wise EX-OR ed with a cell specific scrambling sequence, which is
sequence is used for the purpose of inter-cell interference rejection. The data which are to be
unintelligible to the intruder. The scrambling is performed using (2)
SICS) Vol.4, No.1, February 2013
14
Resource Elements
ncy check (CRC) bits are appended to the
the information of number of
h subframe. The CFI can take the values of 1, 2, 3
Physical Hybrid Indicator Channel
indicates acknowledgement for the uplink channel
ement may be positive (ACK) or negative (NACK) depending upon
data should be
Multiple PHICHs are mapped to the same set of resource elements (REs). This set
ile, instead it is
to the transmitter should experience the following channel
Figure 4 shows the
OR ed with a cell specific scrambling sequence, which is
rejection. The data which are to be

15
)()()(
~
icibib qq
+= ... (2)
Where q represents the codeword, c is the gold sequence used, b is the encoded sequence. The
gold sequence is generated using the formulae of (3), (4) and (5)
( ) 2mod)()()( 21 cc NnxNnxnc +++= ... (3)
( ) 2mod)().3()31( 111 nxnxnx ++=+ ... (4)
2mod
)()1(
)2().3(
)31(
22
22
2 





+++
+++
=+
nxnx
nxnx
nx ... (5)
where the first m-sequence shall be initialized with 30,...,2,1,0)(,1)0( 11 === nnxx . The
initialization of the second m-sequence is denoted by ∑ =
⋅=
30
0 2init 2)(
i
i
ixc with the value
depending on the application of the sequence. In 4, x2(n) is varying for every channel.
Expressions (6),(7) and (8) are used to generate x2(n) for PDSCH, PBCH and PMCH respectively
and the golden sequence c(i) is initialised for the channels PDCCH, PCFICH and PHICH by (9),
(10) and (11) [6].
‫ݔ‬ଶ(݅ሻ = ݊ோே்ூ . 2ଵସ
+ ‫.ݍ‬ 2ଵଷ
+ ቔ
௡௦
ଶ
ቕ . 2ଽ
+ ܰூ஽
௖௘௟௟
݂‫ݎ݋‬ ܲ‫ܪܥܵܦ‬ ... (6)
‫ݔ‬ଶ(݅ሻ = ܰூ஽
௖௘௟௟
for PBCH ... (7)
‫ݔ‬ଶ(݅ሻ = ቔ
௡௦
ଶ
ቕ . 2ଽ
+ ܰூ஽
ெ஻ௌிே
݂‫ݎ݋‬ ܲ‫ܪܥܯ‬ ... (8)
ܿ௜௡௜௧ = ቔ
௡ೞ
ଶ
ቕ . 2ଽ
+ ܰூ஽
௖௘௟௟
݂‫ݎ݋‬ ܲ‫ܪܥܥܦ‬ ... (9)
ܿ௜௡௜௧ = ቀቔ
௡ೞ
ଶ
ቕ + 1ቁ ⋅ ൫2ܰூ஽
௖௘௟௟
+ 1൯ ⋅ 2ଽ
+ ܰூ஽
௖௘௟௟
݂‫ݎ݋‬ ܲ‫ܪܥܫܨܥ‬ ... (10)
ܿ௜௡௜௧ = ቀቔ
௡ೞ
ଶ
ቕ + 1ቁ ⋅ ൫2ܰூ஽
௖௘௟௟
+ 1൯. 2ଽ
݂‫ݎ݋‬ ܲ‫ܪܥܫܪ‬ ... (11)
Where nRNTI is the Radio Network Temporary Identifier, q refers to the codeword number, ns is
slot number and NIDcell is the physical layer cell identity. ܰூ஽
ெ஻ௌிே
is the MBSFN Area Identity for
PMCH.
3.1.2 Modulation
In general LTE follows four different types of modulation techniques such as BPSK, QPSK, 16
QAM and 64 QAM. Channels and their corresponding modulation techniques are shown in Table
1.
Table 1 Channel and Modulations
Channels Type of Modulation
PBCH,PCFICH,PDCCH QPSK
PDSCH QPSK, 16 QAM, 64 QAM
PMCH QPSK, 16 QAM, 64 QAM
PHICH BPSK

16
The scrambled sequence is then modulated to create a block of modulated symbols. In QPSK
modulation pairs of bits are mapped to complex valued modulation symbols I+ jQ, as shown in
Table 2 and hence the all the bits are converted to 16 complex modulated symbols. The outputs
are represented by 16 bit numbers. Similarly the distributed arithmetic processing is applied for
16QAM, 64QAM [1].
Table 2 QPSK Modulation
3.1.3 Layer Mapping
The modulated symbols are then layer mapped to one or more layers depending upon the number
of antenna ports selected .The complex modulated input symbols d(0)
(i) are mapped to layers
x(0)
(i), x(1)
(i),... x(v-1)
(i). The input symbols are mapped to layers according to the Table 3[1]
Table 3 Layer Mapping to different layers
3.1.4 Precoding
The precoder takes a block from the layer mapper x(0)
(i), x(1)
(i),... x(v-1)
(i), and generates a
sequence for each antenna port, y(p)
(i), p is the transmit antenna port number and is {0},{0,1} or
{0,1,2,3}[4]. For transmission over a single antenna port processing is carried out by (12).
‫ݕ‬(௣ሻ
(݅ሻ = ‫ݔ‬(଴ሻ
(݅ሻ … . (12ሻ
Precoding for transmit diversity is available on two or four antenna ports. In two antenna port
precoding, an Alamouti scheme is used for precoding. This precoding procedure for two antenna
case is defined by (13)
( )
( )
( )
( )

























−
−
=














+
+
)(Im
)(Im
)(Re
)(Re
001
010
010
001
2
1
)12(
)12(
)2(
)2(
)1(
)0(
)1(
)0(
)1(
)0(
)1(
)0(
ix
ix
ix
ix
j
j
j
j
iy
iy
iy
iy
... (13)
b(i),b(i+1) I Q
00
21 21
01 21 21−
10 21− 21
11 21− 21−
Number of
layers
Layer mapping
i=0,1,..., Mlayer
symb-1
1 X(0)
(i)=d(0)
(i)
2
X(0)
(i)=d(0)
(2i) Mlayer
symb=M(0)
symb/2
X(1)
(i)=d(0)
(2i+1)
4
X(0)
(i)=d(0)
(4i)
X(1)
(i)=d(0)
(4i+1)
X(2)
(i)=d(0)
(4i+2) Mlayer
symb=M(0)
symb/4
X(3)
(i)=d(0)
(4i+3)

17
For 1,...,1,0 layer
symb −= Mi with layer
symb
ap
symb 2MM = .During transmission on four antenna ports,
{ }3,2,1,0∈p , the output [ ]T
iyiyiyiyiy )()()()()( )3()2()1()0(
= , 1,...,1,0 ap
symb −= Mi of the
precoding operation is defined by (14)
( )
( )
( )
( )
( )
( )
( )
( )











































































−
−
−
−
=




















































+
+
+
+
+
+
+
+
+
+
+
+
)(Im
)(Im
)(Im
)(Im
)(Re
)(Re
)(Re
)(Re
0000100
00000000
0001000
00000000
0001000
00000000
0000100
00000000
00000000
0000001
00000000
0000010
00000000
0000010
00000000
0000001
2
1
)34(
)34(
)34(
)34(
)24(
)24(
)24(
)24(
)14(
)14(
)14(
)14(
)4(
)4(
)4(
)4(
)3(
)2(
)1(
)0(
)3(
)2(
)1(
)0(
)3(
)2(
)1(
)0(
)3(
)2(
)1(
)0(
)3(
)2(
)1(
)0(
)3(
)2(
)1(
)0(
ix
ix
ix
ix
ix
ix
ix
ix
j
j
j
j
j
j
j
j
iy
iy
iy
iy
iy
iy
iy
iy
iy
iy
iy
iy
iy
iy
iy
iy
..... (14)
For 1,...,1,0 layer
symb −= Mi with
( )



≠−
=
=
04modif24
04modif4
)0(
symb
layer
symb
)0(
symb
layer
symbap
symb
MM
MM
M .
3.1.5 Mapping to Resource Elements
The data channels modulated symbols are mapped to the resource element groups (REG), and
data is mapped only in the first OFDM symbol of each subframe and are transmitted through the
channel. To do this module the designer has know the row, column and slot value.
3.2 CHANNEL PROCESSING STEPS OF RECEIVER
3.2.1 Demapping From Resource Elements
While data is received on the antenna ports, the block of complex-valued symbols
)1(),...,0( ap
symb
)()(
−Myy pp
shall be demapped in sequence starting with )0()( p
y from resource
elements( )lk, .
3.2.2 Decoding
The decoder takes as input a block of vectors [ ]Tp
iyiy ...)(...)( )(
= , 1,...,1,0 ap
symb −= Mi demapped
from resources on each of the antenna ports, where )()(
iy p
represents the signal from antenna
port p and generates a block of vectors [ ]T
ixixix )(...)()( )1()0( −
= υ
, 1,...,1,0 layer
symb −= Mi for the
delayer mapping. For reception on a single antenna port, decoding is defined by (15). Similarly
for reception on two antenna ports, { }1,0∈p , the output of the decoding operation is defined by
(16).
‫ݔ‬(଴ሻ
(݅ሻ = ‫ݕ‬(௣ሻ
(݅ሻ ... (15)

18
( )
( )
( )
( ) 













+
+












−
−
=














)12(
)12(
)2(
)2(
00
00
0110
1001
2
)(Im
)(Im
)(Re
)(Re
)1(
)0(
)1(
)0(
)1(
)0(
)1(
)0(
iy
iy
iy
iy
jj
jj
ix
ix
ix
ix
...(16)
3.2.3 Delayer Mapping
The complex-valued symbols for each of the code words to be received are demapped from one
or several layers [5]. Complex-valued symbols )1(),...,0( (q)
symb
)()(
−Mdd qq
for codeword q shall be
demapped from the layers [ ]T
ixixix )(...)()( )1()0( −
= υ
, 1,...,1,0 layer
symb −= Mi where υ is the
number of layers and layer
symbM is the number of symbols per layer. Delayer mapping for single
antenna is defined by (17). Similarly for two antenna port, delayer mapping is defined by (18)
݀(଴ሻ
(݅ሻ = ‫ݔ‬(଴ሻ
(݅ሻ with M0
symb=Mlayer
symb ..... (17)
݀(଴ሻ
(2݅ሻ = ‫ݔ‬(଴ሻ
(݅ሻ
݀(଴ሻ
(2݅ + 1ሻ = ‫ݔ‬(ଵሻ
(݅ሻ
with M0
symb=2Mlayer
symb ..... (18)
3.2.4 Demodulation
The complex-valued symbols )1(),...,0( (q)
symb
)()(
−Mdd qq
of code word q , shall be demodulated
using a demodulation scheme which is reverse of transmitter, resulting in a block of bits
)1(
~
),...,0(
~ (q)
bit
)()(
−Mbb qq
3.2.5 Descrambling
The demodulated symbols in a code word q , after descrambling results in the block of bits
)1(),...,0( )(
bit
)()(
−qqq
Mbb , where )(
bit
q
M is the number of bits in code word q received on each
control channels in one sub frame. The descrambling is defined by (19).
ܾ(௤ሻ(݅ሻ = ቀܾ෨(௤ሻ(݅ሻ + ܿ(௤ሻ(݅ሻቁ ݉‫2݀݋‬ ........ (19)
where ܿ(௤ሻ
(݅ሻ is the generated pseudo random Gold sequence. The descrambling sequence is
initialized with same values as that of the transmitter at start of each subframe.
4. NOVEL ARCHITECTURE OF PHYSICAL DOWNLINK CHANNELS FOR
LTE
4.1 TRANSMITTER ARCHITECTURE
The transmitter side of the architecture consists of Scrambling, Modulation, Layer Mapping,
Precoding and Mapping to the Resource Elements as shown in figure 6.

Figure 6 Parallel Processing Architecture of Transmitter for downlink
Scrambling is common for all the six channels. For this the 32 bit input codeword is XORed with
the 32 bit Gold sequence. Based on the
of scrambling bits to be generated
scrambling bits generated and so the number of Hardware lines. The PBCH, PCFICH and
PDCCH channels employ QPSK modulation. F
8. The PDSCH and PMCH employ
number of hardware lines required is 24
antenna, the maximum number of hardware lines
Table 4
Channel
PBCH
PDSCH
PMCH
PCFICH
PDCCH
PHICH
PHICH uses BPSK modulation. In
corresponding complex-valued modulated output.
modulated symbols to different layers. For SISO the modulated bits get transmitte
mapping is needed. When two antenna ports are used, modulator output is layer mapped as a
block of vector in two layers. When four antenna ports are used, modulator output is layer
mapped as a block of vector in four layers.
mapped data. Similar to layer mapping,
layers. Precoded data are mapped to the LTE grid structure
Parallel Processing Architecture of Transmitter for downlink
Channels in LTE
old sequence. Based on the type of modulation and transmitter diversity
of scrambling bits to be generated varies. The following Table 4 depicts the number of
generated and so the number of Hardware lines. The PBCH, PCFICH and
channels employ QPSK modulation. For this, the maximum number of hardware lines is
and PMCH employ QPSK, 16QAM, 64QAM modulations. The maximum
number of hardware lines required is 24 for PDSCH. Since PMCH is transmitted only on 4
the maximum number of hardware lines required is 8.
Table 4 Number of Scrambling bits generated
Type of
Modulation
Layers No. of Scrambling
bits to be
generated
QPSK 1/2/4 2/4/8
QPSK
16 QAM
64 QAM
1/2/4
2/4/8
4/8/16
6/12/24
QPSK/16QAM/64
QAM
1 2/4/6
QPSK 1/2/4 2/4/8
QPSK 1/2/4 2/4/8
BPSK 1/2/4 1
modulation. In modulation process, a pair of scrambled bit is converted to
valued modulated output.Layer mapping involves mapping of the
modulated symbols to different layers. For SISO the modulated bits get transmitte
When two antenna ports are used, modulator output is layer mapped as a
mapped as a block of vector in four layers. Precoding is the process of creating vectors for layer
mapped data. Similar to layer mapping, precoding can also be performed on single
Precoded data are mapped to the LTE grid structure.
19
modulation and transmitter diversity, the number
s the number of
generated and so the number of Hardware lines. The PBCH, PCFICH and
the maximum number of hardware lines is
he maximum
Since PMCH is transmitted only on 4th
, a pair of scrambled bit is converted to
Layer mapping involves mapping of the
modulated symbols to different layers. For SISO the modulated bits get transmitted as such, no
When two antenna ports are used, modulator output is layer mapped as a
process of creating vectors for layer
on single, two or four

4.2 RECEIVER ARCHITECTURE
The receiver side of the architecture
Decoding and Detection, Delayer Mapping and Descrambling
receiver architecture is designed with two receiving antennas. When the transmitter diversity is
SISO (1x1) or MISO (2x1 and 4x1) antenna 1 is enabled to receive. Similarly when MIMO (2x2
and 4x2) case occurs both the antennas are enabled to receive.
to demap the data from the grids.
Figure 7 Parallel Processing Architecture of Receiver for downlink
After demapping the data from the grid, decoding is performed by the receiver.
demapping module is given to a buffer in order to st
(2x1) and MISO (4x1) .For MIMO(2x2) and MIMO(4x
data in two layers. The data from the buffer module is given to the decoding. Based on the
transmitter diversity the 16 bit data is stored for further process
performed by comparing the decoded results with the predefined modulation values and
generating the resultant bits corresponding to the modulation scheme.
QPSK modulation, 4 for 16 QAM and 6 for 64 QAM
detected bits are concatenated to form a single layer in delayer mapping module.
descrambling is performed by XORing the detected bits with the
transmitter and produces the origi
5. RESULTS AND DISCUSSIONS
5.1 Simulation output for SISO transmitter
The Simulation output for the SISO transmitter for PDC
variables clk, rst, td, and ‘mod_pdcch
modulation. So based on the ‘mod_pdsch
the number of hardware lines varies. For
generate the output thus giving 2 input bits to the modulation mapper to produce a single s
at a single clock cycle. Variable
Scrambling output is directly given as the input to mo
is the modulated output of the modulation module which is given to the layer mapping module.
The layer mapped output is given by
RCHITECTURE
The receiver side of the architecture consists of Demapping from the Resource Elements,
Decoding and Detection, Delayer Mapping and Descrambling as shown by the Figure
1 and 4x1) antenna 1 is enabled to receive. Similarly when MIMO (2x2
and 4x2) case occurs both the antennas are enabled to receive. In the receiver side, the first step is
rids.
Parallel Processing Architecture of Receiver for downlink Channels in LTE
After demapping the data from the grid, decoding is performed by the receiver. The output of the
demapping module is given to a buffer in order to store 16 bit data for the SISO (1
(2x1) and MISO (4x1) .For MIMO(2x2) and MIMO(4x2) the buffer will store two segments of
transmitter diversity the 16 bit data is stored for further processing. Detection process is
generating the resultant bits corresponding to the modulation scheme. The resultant bits are 2
, 4 for 16 QAM and 6 for 64 QAM modulations respectively. Demodulated and
detected bits are concatenated to form a single layer in delayer mapping module.
descrambling is performed by XORing the detected bits with the same Gold sequence
original control and data messages.
ISCUSSIONS
Simulation output for SISO transmitter
for the SISO transmitter for PDCCH channel is shown in Figure
mod_pdcch’ are the inputs given. The PDCCH employs QPSK
mod_pdsch’ and td, the number of scrambling bits generated and
varies. For QPSK ‘scr_pdcch1’ and ‘scr_pdcch2’
g 2 input bits to the modulation mapper to produce a single s
‘canc_pdcch’ is the clock generated from the scrambling module.
Scrambling output is directly given as the input to modulation module. Variable ‘modpdc
ped output is given by ‘layer1pdcch’. Layer mapped output is given to the
20
consists of Demapping from the Resource Elements,
as shown by the Figure 7. The
1 and 4x1) antenna 1 is enabled to receive. Similarly when MIMO (2x2
, the first step is
Channels in LTE
The output of the
ore 16 bit data for the SISO (1x1), MISO
2) the buffer will store two segments of
Detection process is
he resultant bits are 2 for
Demodulated and
detected bits are concatenated to form a single layer in delayer mapping module. The
old sequence used in the
Figure 8. The
CH employs QPSK
and td, the number of scrambling bits generated and
are made to
g 2 input bits to the modulation mapper to produce a single segment
is the clock generated from the scrambling module.
modpdcchpara1’
. Layer mapped output is given to the

21
precoding module. The output of the precoding module is one segment represented as
‘prelayer1_pdcch’. The final transmitted output through the antenna is given by ‘transmit_0’.This
explanation suits well for all the other channels.
Figure 8 Simulation result for SISO (1X1) PDCCH
.
5.2 Simulation output for MISO (2x1) transmitter
The simulation result for the transmitter using MISO (2x1) concept for PCFICH channel is shown
in Figure 9. The variables clk, rst, td, and ‘mod_pcfich’ are the inputs given. For MISO (2x1) the
process is similar to SISO (1x1).But in layer mapping same modulated data is layer mapped into
two layers. The layer mapped output is given by ‘layer1pcfich’ and ‘layer2pcfich’. Layer mapped
output is given to the precoding module; the output is ‘prelayer1_pcfich’ and ‘prelayer2_pcfich’,
which consists of two segments in two layers. The final transmitted output through the antenna is
given by ‘transmit_0’ and ‘transmit_1’. The above explained procedure is similar for all the other
channels.
Figure 9 Simulation result for MISO (2X1) PCFICH
5.3 Simulation output for MISO (4x1) transmitter
The simulation result of MISO (4x1) transmitter for PMCH channel is shown in Figure 10. The
variables clk, rst, td, and ‘mod_pmch’ are the inputs given. For MISO (4x1) the process is similar
to SISO (1x1). For PMCH channel the modulated data is layer mapped into a single layer. The
layer mapped output is given by ‘singlepmch’. Layer mapped output is given to the precoding
module, the output is ‘single_prepmch’. The final transmitted output through the antenna is given
by ‘transmit_3’.

22
Figure 10 Simulation result for MISO (4X1) PMCH
5.4 Simulation output for MIMO (2x2) transmitter
The simulation result for the MIMO (2x2) transmitter for channel PDSCH is shown in Figure 11.
For MIMO (2x2) the number of scrambling bits to be generated is 4/8/12bits for
QPSK/16QAM/64QAM modulations. For 64QAM, the scrambler module outputs are
‘scr_pdsch1’,‘scr_pdsch2’,‘scr_pdsch3’,‘scr_pdsch4’,‘scr_pdsch5’,‘scr_pdsch6’, ‘scr_pdsch7’,
‘scr_pdsch8’,‘scr_pdsch9’,‘scr_pdsch10’, ‘scr_pdsch11’,‘scr_pdsch12’. Variable ‘canc_pdsch’ is
the clock generated from the scrambling module. Scrambling output is directly given as the input
to modulation module. Variable ‘modpdschpara1’and ‘modpdschpara2’ are the modulated output
of the modulation module which shows two different data to be given directly to the layer
mapping module. The layer mapped output is given by ‘layer1pdsch’ and ‘layer2pdsch’. Layer
mapped output is given to the precoding module; the output is ‘prelayer1_pdsch’ and
‘prelayer2_pdsch’, which is of two different segments in two layers. The final transmitted output
through the antenna is given by ‘transmit_0’ and ‘transmit_1’.These explanations are similar for
PBCH, PCFICH and PDCCH channels also.
Figure 11 Simulation result for MIMO (2X1) PDSCH
5.5 Simulation output for MIMO (4x2) transmitter
The simulation result for the MIMO transmitter of PBCH channel is shown in Figure 12.For
QPSK, the scrambler module outputs are ‘scr_pbch1’, ‘scr_pbch2’, ‘scr_pbch3’, ‘scr_pbch4’,
‘scr_pbch5’, ‘scr_pbch4’, ‘scr_pbch7’, ‘scr_pbch8’.Variable ‘canc_pbch’ is the clock generated
from the scrambling module. Scrambling output is directly given as the input to modulation
module. Variable ‘modpbchpara1’, ‘modpbchpara2’, ‘modpbchpara3’ and ‘modpbchpara4’ are

23
the modulated output of the modulation module which shows four different data to be given
directly to the layer mapping module. The layer mapped output is given by ‘layer1pbch’,
‘layer2pbch’, ‘layer3pbch’ and ‘layer4pbch’. Layer mapped output is given to the precoding
module, the output is ‘prelayer1_pbch’, ‘prelayer2_pbch’, ‘prelayer3_pbch’ and
‘prelayer4_pbch’, which is of four segments in four layers. The final transmitted output through
the antenna is given by ‘transmit_0’, ‘transmit_1’, ‘transmit_2’ and ‘transmit_3’.
Figure 12 Simulation result for MIMO (4x2) PBCH
5.6 Simulation output for SISO (1x1), MISO (2x1) and MISO (4x1) Receiver
The Simulation output for the SISO (1x1), MISO (2x1) and MISO (4x1) receiver for PBCH
channel is shown in Figure 13. The variables clk, rst, td, are the inputs given.The variables
‘as_pdsch’, ‘as_pbch’, ‘as_pdcch’, ‘as_pcfich’ and ‘as_phich’ are the antenna selection variables
which has value 01 indicating single receiver antenna. The variable ‘prelayer1pbch’ is the output
of the data demapping module, which exclusively demaps the received data from antenna. The
variable ‘singlepbch’ is the decoded value for the PBCH channel. In detection module the
variable ‘singlepbchqpsk’ is the output, which is of two bits for the PBCH channel. The variables
‘delayersinglepbch’ is the delayermapped value. The variables ‘descr_pbch1’ and ‘descr_pbch2’
are the variables indicating the descrambled bits for the channel PBCH. Similarly for PDCCH and
PCFICH also. Since PDSCH employs QPSK, 16QAM and 64QAM modulations, the output of
the detector module ‘singlepdsch_demod’ consists of 2 bits/4 bits/6 bits for QPSK/ 16QAM
/64QAM modulations respectively. The variables ‘descr_pdsch1’, ‘descr_pdsch2’,
‘descr_pdsch3’, ‘descr_pdsch4’, ‘descr_pdsch5’, ‘descr_pdsch6’, are the variables indicating the
descrambled bits for the channel PDSCH.
Figure 13 Simulation output for SISO (1x1), MISO (2x1) and MISO (4x1) Receiver-PBCH

24
5.7 Simulation output for MIMO (2x2) and MIMO (4x2)
The Simulation output for the MIMO (2x2) and MIMO (4x2) receiver for PBCH channel is
shown in Figure 14.The variable ‘as_pbch’ is the antenna selection variable which has value 10
indicating two antenna receivers. The variables ‘prelayer1pbch’ and ‘prelayer2pbch’ are the
output of the data demapping module, which exclusively demap the received data from antenna.
The variables ‘prelayerpbch1_1decode’, ‘prelayerpbch1_2decode’, ‘prelayerpbch2_1decode’ and
‘prelayerpbch2_2decode’ are the decoded values for the PBCH channel. In detection module the
variable ‘qpsk_prepbch1’ and ‘qpsk_prepbch2’ are the output, which is of two bits for the PBCH
channel. The variables ‘delayersinglepbch’ is the delayermapped value. The variables
‘descr_pbch1’, ‘descr_pbch2’, ‘descr_pbch3’and ‘descr_pbch4’ are the variables indicating the
descrambled bits for the channel PBCH. Similarly for PDCCH and PCFICH also.
PDSCH employs QPSK, 16QAM and 64QAM modulations. Each of the two output variables
‘twopdsch_demod1’ and ‘twopdsch_demod2’ of the detector module consists of 2 bits/4bits/6bits
for QPSK/16QAM/64QAM modulations respectively. The variables descr_pdsch1, descr_pdsch2,
descr_pdsch3, descr_pdsch4, descr_pdsch5, descr_pdsch6, descr_pdsch7, descr_pdsch8,
descr_pdsch9, descr_pdsch10, descr_pdsch11, descr_pdsch12, are the variables indicating the
descrambled bits for the channel PDSCH shown in Figure 15.
Figure 14 Simulation output for MIMO (2x2) and MIMO (4x2) Receiver –PBCH
Figure 15 Simulation output for MIMO (2x2) and MIMO (4x2) Receiver - PDSCH (QPSK)

25
5.8 Implementation Results
Simulated programs are implemented on Plan Ahead 13.4 Virtex-5 board and the implemented
results are discussed in terms of RTL Design, Power Estimation, Resource Estimation and FPGA
Editor. Register-transfer-level abstraction is used in hardware description languages (HDLs) like
Verilog and VHDL to create high-level representations of a circuit, from which lower-level
representations and ultimately actual wiring can be derived. One of the peculiarities of the Plan
Ahead tool is that it provides RTL elaboration capabilities to compile RTL source files in the
project. The Figure 16 provides the RTL diagram of transmitter showing the different modules
like scrambling, modulation, layer mapping, precoding and Resource element mapping. Inside
various blocks we can see the Muxes, Look up tables, various interconnections and Gates. The
Figure 17 provides the RTL diagram of receiver showing the different modules like
descrambling, de modulation, delayer mapping, decoding and Demapping from the resource
elements.
The resource estimation for the transmitter and receiver is shown in the Figure 18a and 18b. From
the graphical representation it is clear that out of the total resources about 1% is used for registers,
6% for Look up tables, 10% for the slices, 15% for the IO, 21% for BUFG in transmitter side, 1%
is used for registers, 25% for Look up tables, 36% for the slices, 7% for the IO, 15% for BUFG in
receiver side .One of the peculiarities of the Plan Ahead software is that it performs power
estimation to provide an early view of your design power distribution at the RTL level. The
power estimation is a graphical representation of the total on chip power and its distribution to the
device static, core dynamic, and I/O as shown in Figure 19a and 19b.The total on chip power of
1379 mw for the transmitter is distributed among I/O, core dynamic and Device static as 245mw,
459mw and 455 .The total on chip power of 1263 mw for the receiver is distributed among I/O,
core dynamic and Device static as 33mw, 777mw and 454 mw. The FPGA editor shows the
placing and routing in the device xc5vlx50tff1134. The utilization of the IC is shown in the
Figure 20a and 20b.
Figure 16 RTL Diagram of the Transmitter

26
Figure 17 RTL Diagram of Receiver
Figure 18a and 18b Resource utilization of the Transmitter and Receiver
Figure 19a and 19b Power estimation of Transmitter and Receiver

27
Figure 20a and 20b FPGA editor of the Transmitter and Receiver
6. CONCLUSIONS
The transmitter architecture of LTE Physical Downlink channels consists of five steps namely
Scrambling, Modulation, Layer Mapping, Precoding and Mapping to Resource Elements. Initially
the single codeword say 32 bits is taken and is scrambled using gold sequence. The scrambled
output is modulated by any one of the modulation scheme according to the information obtained
from the higher layers. The modulated stream of bits is layer mapped according to the number of
antenna ports present. The layer mapped output is precoded. Then precoded output is mapped to
resource elements at the respective positions of each channel leaving space for reference and
synchronization signals. The receiver architecture of LTE Downlink Physical channels consists of
five steps namely Demapping from Resource Elements, Decoding, Detection, Delayer mapping
and Descrambling. At receiver, the data is received from the grid and the reverse process
demapping, decoding, detection, delayer mapping, for respective channels and finally
descrambled to get the original transmitted codeword at all channel. The implementation of the
transmitter and receiver architectures of all channels are carried by Verilog HDL programming
and synthesized in Plan Ahead 13.4 with Virtex-5 specification. Simulation results and
implementation results (RTL design, power estimation, resource estimation and FPGA editor) for
transmitter and receiver of LTE downlink channels are discussed.
ACKNOWLEDGEMENT
The authors wish to express their sincere thanks to All India Council for Technical Education,
New Delhi for the grant to do the project titled “Design of Testbed for the Development of
Optimized Architectures of MIMO Signal Processing” (No: 8023/RID/RPS/039/11/12) .They are
also thankful to the Management and Principal of Mepco Schlenk Engineering College, Sivakasi
for their constant support and encouragement to carry out this part of the project work
successfully.
REFERENCES
[1] 3GPP TS 36.211,” Evolved Universal Terrestrial Radio Access (E- UTRA); Physical Channels and
Modulation (Release 8)”.
[2] S. J. Thiruvengadam, Louay M. A. Jalloul, “Performance Analyis of the 3GPP-LTE Physical Control
Channels,” EURASIP Journal on Wireless Communications and Networking, vol. 2010, Article ID
914934, 10 pages, Nov. 2010.

28
[3] S .Syed Ameer Abbas, Geethu K .S, S.J Thiruvengadam, “Implementation of SISO Architecture for
LTE Downlink Control Channels in Virtex 5”, International Journal of Engineering and Innovative
Technology (IJEIT) Volume 1, Issue 5, May 2012.
[4] S. Syed Ameer Abbas, A. Kanimozhi , S. J. Thiruvengadam ,“Realization of the SISO Architecture for
Downlink Data Channels of 3GPP-LTE using PlanAhead Tool and Virtex-5 Device”, IFRSA
International Journal Of Electronics Circuits And Systems |Vol 1|issue 2|July 2012.
[5] Abbas, S. S. A, Praba. R. L, Thiruvengadam. S. J, “PCFICH Channel Design for LTE using FPGA” in
Proceedings of Recent Trends in Information Technology(ICRTIT) 2011 International Conference, pp
53-63, Chennai, Tamilnadu.
[6] 3GPP TS36.212, “Evolved Universal Terrestrial Radio Access (EUTRA); Multiplexing and Channel
Coding (Release 8)”.
Authors
Mr.S.Syed Ameer Abbas has completed his M.E degree in Applied Electronics and now
pursuing his Ph.D. in the area of VLSI Signal processing at Anna University, Chennai. At
present he is working as Assistant profess or in ECE department, Mepco Schlenk
Engineering College, Sivakasi Tamil Nadu, India. He has published more than 35 papers
in International Journals, International and National Conferences. He has been as
Principal Investigator and Co-ordinator for two AICTE projects.
Rahumath Nisha .J received the B.E degree in the department of Electronics and
Communication Engineering. Now she is currently doing her M.E degree in
Communication Systems in Mepco Schlenk Engineering College, Sivakasi, Tamilnadu,
India.
Beril Sahaya Mary. M received the B.E degree in the department of Electronics and
Communication Engineering. Now she is currently doing her M.E degree in
Communication Systems in Mepco Schlenk Engineering College, Sivakasi, Tamilnadu,
India.
Dr.S.J.Thiruvengadam has completed his Ph.D.in the area of Signal Processing and Post
Doctoral Studies in MIMO Wireless Communications at Stanford University, USA. At
present he is working as Professor, Electronics and Communication Department,
Thiagarajar College of Engineering, Madurai, Tamil Nadu, India. He has published papers
in more than 12 International journals and 60 International Conferences. He has been as
Principal Investigator for more than 10 Government Projects.

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